vee
217 lines
11 KiB
Plaintext
217 lines
11 KiB
Plaintext
/* __DISCLAIMER_START__ */
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/******************************************************************************
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* (c) 2014-2017, Cypress Semiconductor Corporation
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* or a subsidiary of Cypress Semiconductor Corporation. All rights
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* reserved.
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*
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* This software, including source code, documentation and related
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* materials ( "Software" ), is owned by Cypress Semiconductor
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* Corporation or one of its subsidiaries ( "Cypress" ) and is protected by
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* and subject to worldwide patent protection (United States and foreign),
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* United States copyright laws and international treaty provisions.
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* Therefore, you may use this Software only as provided in the license
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* agreement accompanying the software package from which you
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* obtained this Software ( "EULA" ).
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*
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* If no EULA applies, Cypress hereby grants you a personal, nonexclusive,
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* non-transferable license to copy, modify, and compile the
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* Software source code solely for use in connection with Cypress' s
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* integrated circuit products. Any reproduction, modification, translation,
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* compilation, or representation of this Software except as specified
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* above is prohibited without the express written permission of Cypress.
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*
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* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
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* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
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* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE. Cypress reserves the right to make
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* changes to the Software without notice. Cypress does not assume any
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* liability arising out of the application or use of the Software or any
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* product or circuit described in the Software. Cypress does not
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* authorize its products for use in any products where a malfunction or
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* failure of the Cypress product may reasonably be expected to result in
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* significant property damage, injury or death ( "High Risk Product" ). By
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* including Cypress' s product in a High Risk Product, the manufacturer
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* of such system or application assumes all risk of such use and in doing
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* so agrees to indemnify Cypress against all liability.
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******************************************************************************/
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/* __DISCLAIMER_END__ */
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/*****************************************************************************/
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// Check that necessary definitions are available
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#if (!defined(_LINK_flash_)) && (!defined(_LINK_sram_))
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#error "Link location not defined or not supported!"
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#endif
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#if (!defined(_CORE_cm0plus_)) && (!defined(_CORE_cm7_0_)) && (!defined(_CORE_cm7_1_))
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#error "Target core not defined or not supported!"
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#endif
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#if defined(_CORE_cm7_0_) || defined(_CORE_cm7_1_)
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#define _CORE_cm7_x_
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#endif
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//=======================================================================================
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// memory_map.ld contains symbol and memory area definitions used by this linker file
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//=======================================================================================
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//============================================================================================================
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// CONFIGURATION
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//------------------------------------------------------------------------------------------------------------
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// Select whether the CM7 stack and heap are linked to SRAM or DTCM, by uncommenting or commenting the following define.
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// Note: Some examples/drivers are not yet supporting DTCM linkage because local variables (stack) will need to
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// be accessed by other masters (e.g. DMA) and address conversions for DTCM addresses are missing
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#define LINK_CM7_STACK_HEAP_TO_SRAM_NOT_DTCM
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//============================================================================================================
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//
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// Program layout
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//
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SECTIONS
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{
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//============================================================================================================
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// ROM type sections
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//------------------------------------------------------------------------------------------------------------
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#if defined(_LINK_flash_)
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#define MEMORY_FOR_ROM_TYPE_SECTIONS CODE_FLASH
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#elif defined(_LINK_sram_)
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#define MEMORY_FOR_ROM_TYPE_SECTIONS SRAM
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#endif
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// Note: .intvec must be the first section in ROM in order for __cmx_vector_base_linker_symbol to be correctly calculated!
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.intvec ALIGN(intvec_alignment) : > MEMORY_FOR_ROM_TYPE_SECTIONS
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.picbase : > .
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.text : > .
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.intercall : > .
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.interfunc : > .
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.fixaddr : > .
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.fixtype : > .
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.secinfo : > .
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.robase : > .
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.rodata : > .
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.ROM.syscall ROM(.syscall) : > .
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.ROM.data ROM(.data) : > .
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#if defined(_LINK_sram_)
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// Cypress (ROM and Flash) boot firmware needs an area in SRAM (e.g. for stack). This may cause issues in case of
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// RAM build configurations when code/const sections are loaded there by the debugger, but may get overwritten
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// if reset is triggered by the debug script later on. So in case of RAM build configurations the following
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// statement checks if the area of ROM type sections overlaps the boot area.
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// Comment the statement if the sections shall be linked there anyway.
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//
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// A simple check is sufficient because the boot area is from SRAM_MAX-6KB to SRAM_MAX-2KB and it is unlikely that the ROM sections would only
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// start in the last 2KB (which are anyway not accessible in early MCU revisions because of private SROM RAM area)
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//
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// !!! This statement should be the last entry in the ROM type sections !!! (Note: The symbol will not be used, it is just used to implement the error check)
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__rom_type_sections_end_address = (. < sram_used_by_boot_base) ? . : error("ROM type sections are overlapping the area used by Cypress boot firmware. Check comment in linker file!");
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#endif
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//============================================================================================================
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// RAM type sections
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//------------------------------------------------------------------------------------------------------------
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// >>> SRAM <<<
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.sram_base ALIGN(ecc_init_width) : > SRAM
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.pidbase ALIGN(8) : > .
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.data ALIGN(8) : > .
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.bss ALIGN(8) CLEAR : > . // can be changed to NOCLEAR when RAM ECC initialization is enabled in startup_customize.h to improve startup time
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.intvec_ram ALIGN(intvec_alignment) NOCLEAR : > .
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.syscall ALIGN(8) : > .
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#if defined(_CORE_cm0plus_) || defined(LINK_CM7_STACK_HEAP_TO_SRAM_NOT_DTCM)
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.heap ALIGN(8) PAD(heap_reserve) : > .
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.stack ALIGN(ecc_init_width) PAD(stack_reserve) : > .
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#endif
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#ifdef _CORE_cm7_x_
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// >>> DTCM <<<
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.dtcm_base : > SELF_DTCM
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// Placeholder: add/move sections for DTCM address space here
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#if (!defined(LINK_CM7_STACK_HEAP_TO_SRAM_NOT_DTCM))
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.heap ALIGN(8) PAD(heap_reserve) : > .
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.stack ALIGN(ecc_init_width) PAD(stack_reserve) : > .
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#endif
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// >>> ITCM <<<
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.itcm_base : > SELF_ITCM
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// Placeholder: add/move sections for ITCM address space here
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// (Note: corresponding .ROM.xyz sections are needed as well to copy section contents on startup)
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#endif
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//============================================================================================================
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// These special symbols mark the bounds of RAM and ROM memory.
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// They are used by the MULTI debugger.
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//------------------------------------------------------------------------------------------------------------
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__ghs_romstart = MEMADDR(CODE_FLASH);
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__ghs_romend = MEMENDADDR(SFLASH_ALT);
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__ghs_ramstart = MEMADDR(SRAM);
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__ghs_ramend = MEMENDADDR(SRAM);
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//============================================================================================================
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// These special symbols help GHS to identify the run type of this build: RAM, ROM, ROM-to-RAM
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//------------------------------------------------------------------------------------------------------------
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#if defined(_LINK_flash_)
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__ghs_rombootcodestart = MEMADDR(CODE_FLASH);
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__ghs_rombootcodeend = MEMENDADDR(CODE_FLASH);
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__ghs_rambootcodestart = 0;
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__ghs_rambootcodeend = 0;
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#elif defined(_LINK_sram_)
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__ghs_rombootcodestart = 0;
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__ghs_rombootcodeend = 0;
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__ghs_rambootcodestart = 0;
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__ghs_rambootcodeend = 0;
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#endif
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//============================================================================================================
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// The start of the main CPU(s) vector table is required by CM0+ application to correctly
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// set CPUSS->CMx_VECTOR_TABLE_BASE register before releasing the main CPU(s) from reset
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// Following statements also ensure that the created symbol has the correct alignment
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//------------------------------------------------------------------------------------------------------------
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#ifdef _CORE_cm0plus_
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#if defined(_LINK_flash_)
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__cm7_0_rom_start = MEMADDR(CODE_FLASH) - cm0plus_code_flash_offset + cm7_0_code_flash_offset;
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__cm7_1_rom_start = MEMADDR(CODE_FLASH) - cm0plus_code_flash_offset + cm7_1_code_flash_offset;
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#elif defined(_LINK_sram_)
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__cm7_0_rom_start = MEMADDR(SRAM) - cm0plus_sram_offset + cm7_0_sram_offset;
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__cm7_1_rom_start = MEMADDR(SRAM) - cm0plus_sram_offset + cm7_1_sram_offset;
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#endif
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__cm7_0_vector_base_linker_symbol = (__cm7_0_rom_start + cm7_intvec_alignment - 1) & ~(cm7_intvec_alignment - 1);
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__cm7_1_vector_base_linker_symbol = (__cm7_1_rom_start + cm7_intvec_alignment - 1) & ~(cm7_intvec_alignment - 1);
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#endif
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//============================================================================================================
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// These symbols will be used by startup.c / startup_customize.h for RAM ECC initialisation
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//------------------------------------------------------------------------------------------------------------
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#if defined(_LINK_sram_)
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// If "ROM type" sections are linked to SRAM they shall not be cleared by the startup code
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__ecc_init_sram_start_address = ADDR(.sram_base); // The empty .sram_base section is a marker for the start of "RAM type" sections in SRAM
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#else
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__ecc_init_sram_start_address = MEMADDR(SRAM);
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#endif
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__ecc_init_sram_end_address = MEMENDADDR(SRAM) - 1;
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#ifdef _CORE_cm7_x_
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__ecc_init_dtcm_start_address = MEMADDR(SELF_DTCM);
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__ecc_init_dtcm_end_address = MEMENDADDR(SELF_DTCM) - 1;
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__ecc_init_itcm_start_address = MEMADDR(SELF_ITCM);
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__ecc_init_itcm_end_address = MEMENDADDR(SELF_ITCM) - 1;
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#endif
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}
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