vee
234 lines
12 KiB
Plaintext
234 lines
12 KiB
Plaintext
/* __DISCLAIMER_START__ */
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/******************************************************************************
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* (c) 2014-2017, Cypress Semiconductor Corporation
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* or a subsidiary of Cypress Semiconductor Corporation. All rights
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* reserved.
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*
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* This software, including source code, documentation and related
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* materials ( "Software" ), is owned by Cypress Semiconductor
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* Corporation or one of its subsidiaries ( "Cypress" ) and is protected by
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* and subject to worldwide patent protection (United States and foreign),
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* United States copyright laws and international treaty provisions.
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* Therefore, you may use this Software only as provided in the license
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* agreement accompanying the software package from which you
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* obtained this Software ( "EULA" ).
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*
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* If no EULA applies, Cypress hereby grants you a personal, nonexclusive,
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* non-transferable license to copy, modify, and compile the
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* Software source code solely for use in connection with Cypress' s
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* integrated circuit products. Any reproduction, modification, translation,
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* compilation, or representation of this Software except as specified
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* above is prohibited without the express written permission of Cypress.
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*
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* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
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* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
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* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE. Cypress reserves the right to make
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* changes to the Software without notice. Cypress does not assume any
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* liability arising out of the application or use of the Software or any
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* product or circuit described in the Software. Cypress does not
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* authorize its products for use in any products where a malfunction or
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* failure of the Cypress product may reasonably be expected to result in
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* significant property damage, injury or death ( "High Risk Product" ). By
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* including Cypress' s product in a High Risk Product, the manufacturer
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* of such system or application assumes all risk of such use and in doing
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* so agrees to indemnify Cypress against all liability.
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******************************************************************************/
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/* __DISCLAIMER_END__ */
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/*****************************************************************************/
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// Only 2 MB of non-contiguous flash memory is available in PSVP and we use following hard-coded assignment for now
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// IMPORTANT: only change the "code_flash" related definitions below if you know what you are doing
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// CM0+ :: 0x10000000 to 0x1007ffff (512 KB)
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// CM7_0 :: 0x10080000 to 0x100fffff (512 KB)
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// CM7_1 :: 0x10400000 to 0x104fffff (1024 KB)
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// Please note:
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// The whole SRAM area of this device consists of several SRAM areas (SRAM0, 1, ...) each having
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// its own SRAM controller. Please check the device datasheet for the exact memory to SRAM controller distribution.
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// For achieving the best CM7 performance it is recommended - if possible - to ensure that data with temporal
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// locality (e.g. data belonging to one task) does not span multiple SRAM controllers. Otherwise a stalling of AXI
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// transactions may occur, if they are originating from the same CM7 AXI transaction ID to different SRAM controllers.
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// Check that necessary definitions are available
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#if (!defined(_LINK_flash_)) && (!defined(_LINK_sram_))
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#error "Link location not defined or not supported!"
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#endif
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#if (!defined(_CORE_cm0plus_)) && (!defined(_CORE_cm7_0_)) && (!defined(_CORE_cm7_1_))
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#error "Target core not defined or not supported!"
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#endif
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#if (!defined(CY_MCU_rev_a)) && (!defined(CY_MCU_rev_b)) && (!defined(CY_MCU_rev_c)) && (!defined(CY_MCU_rev_d))
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#error "MCU revision is not defined or not supported!"
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#endif
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//=======================================================================================
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// Description of special symbols
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//=======================================================================================
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// sram_private_for_srom:
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// The SROM code needs an area for private data during system call processing. It will
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// not be accessible by user software in protection state NORMAL and beyond.
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// So it needs to be excluded from the total SRAM available to the user. The location of
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// this RAM depends on the MCU revision.
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//
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// sram_used_by_boot_base:
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// Cypress (ROM and Flash) boot firmware needs an area in SRAM (e.g. for stack). This may cause issues in case of
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// RAM build configurations when code/const sections are loaded there by the debugger, but may get overwritten
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// if reset is triggered by the debug script later on. So in case of RAM build configurations the linker should
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// check if the area of ROM type sections overlaps the boot area.
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//
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// sram_can_lin_boot_reserve:
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// Cypress CAN/LIN Bootloader is entered only if several conditions apply (refer Architecture TRM, "Flash Boot" chapter).
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// It will then use an area of SRAM for its data.
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// This may cause issues in case of RAM build configurations when code/const sections are loaded there by the debugger,
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// but may get overwritten if reset is triggered by the debug script later on. Therefore, this area shall be reserved.
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//
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// ecc_init_width:
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// Defines the most restrictive native ECC width (in bytes) of all "normal" memories (SRAM, DTCM, ITCM) in any
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// Traveo II derivate in order to keep the startup code dealing with ECC initialization generic
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//=======================================================================================
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// Following symbol and memory area definitions are used by linker_directives.ld
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//=======================================================================================
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DEFAULTS
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{
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// Constants
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code_flash_total_size = 8384K // no need to adapt for PSVP, only used by silicon #else below
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sram_total_size = 1024K
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sram_base = 0x28000000
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sram_used_by_boot_base = sram_base + sram_total_size - 6K
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sram_private_for_srom = 2K
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cm0plus_intvec_alignment = 256 // CPU specific vector table alignment requirement
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cm7_intvec_alignment = 128 // CPU specific vector table alignment requirement
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ecc_init_width = 8
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#if defined(_LINK_sram_)
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sram_can_lin_boot_reserve = 512
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#else
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sram_can_lin_boot_reserve = 0
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#endif
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#if defined(CY_MCU_rev_a) || defined(CY_MCU_rev_b)
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sram_user_start_offset = 0 + sram_can_lin_boot_reserve
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sram_user_end_offset = sram_total_size - sram_private_for_srom
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#else
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sram_user_start_offset = sram_private_for_srom + sram_can_lin_boot_reserve
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sram_user_end_offset = sram_total_size - 0
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#endif
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//===================================================================================
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// USER CONFIGURATION
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//===================================================================================
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// Specify how much SRAM and CODE_FLASH shall be used by CM0+ application and CM7_0 application,
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// the rest of the memory will be automatically assigned to CM7_1 application
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cm0plus_sram_reserve = 128K - sram_user_start_offset
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cm7_0_sram_reserve = 512K
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#if CY_USE_PSVP == 1
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// PSVP
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cm0plus_code_flash_reserve = 512K // <- hardcoded for PSVP
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cm7_0_code_flash_reserve = 512K // <- hardcoded for PSVP
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#else
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// Silicon
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cm0plus_code_flash_reserve = 1024K
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cm7_0_code_flash_reserve = 4096K
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#endif
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//-----------------------------------------------------------------------------------
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// Specify stack and heap sizes for CM0+, CM7_0 and CM7_1 application independently
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cm0plus_heap_reserve = 1K
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cm0plus_stack_reserve = 1K
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cm7_0_heap_reserve = 1K
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cm7_0_stack_reserve = 1K
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cm7_1_heap_reserve = 1K
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cm7_1_stack_reserve = 1K
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//===================================================================================
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// Calculation of SRAM distribution among all cores
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cm0plus_sram_offset = sram_user_start_offset
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cm7_0_sram_offset = cm0plus_sram_offset + cm0plus_sram_reserve
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cm7_1_sram_offset = cm7_0_sram_offset + cm7_0_sram_reserve
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cm7_1_sram_reserve = sram_user_end_offset - cm7_1_sram_offset
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// Calculation of CODE_FLASH distribution among all cores
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cm0plus_code_flash_offset = 0
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cm7_0_code_flash_offset = cm0plus_code_flash_offset + cm0plus_code_flash_reserve
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#if CY_USE_PSVP == 1
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cm7_1_code_flash_offset = 0x00400000 // <- hardcoded for PSVP
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cm7_1_code_flash_reserve = 1M // <- hardcoded for PSVP
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#else
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cm7_1_code_flash_offset = cm7_0_code_flash_offset + cm7_0_code_flash_reserve
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cm7_1_code_flash_reserve = code_flash_total_size - cm7_1_code_flash_offset
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#endif
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// Map core dependent definition to generic name for memory and section definition
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#if defined(_CORE_cm0plus_)
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self_itcm_size = 0
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self_dtcm_size = 0
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heap_reserve = cm0plus_heap_reserve
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stack_reserve = (cm0plus_stack_reserve + (ecc_init_width - 1)) & (~((ecc_init_width - 1))) // Ensure that stack size is an integer multiple of ECC init width (round up)
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sram_offset = cm0plus_sram_offset
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sram_reserve = cm0plus_sram_reserve
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code_flash_offset = cm0plus_code_flash_offset
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code_flash_reserve = cm0plus_code_flash_reserve
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intvec_alignment = cm0plus_intvec_alignment
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#elif defined(_CORE_cm7_0_)
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self_itcm_size = 16K
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self_dtcm_size = 16K
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heap_reserve = cm7_0_heap_reserve
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stack_reserve = (cm7_0_stack_reserve + (ecc_init_width - 1)) & (~((ecc_init_width - 1))) // Ensure that stack size is an integer multiple of ECC init width (round up)
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sram_offset = cm7_0_sram_offset
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sram_reserve = cm7_0_sram_reserve
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code_flash_offset = cm7_0_code_flash_offset
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code_flash_reserve = cm7_0_code_flash_reserve
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intvec_alignment = cm7_intvec_alignment
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#elif defined(_CORE_cm7_1_)
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self_itcm_size = 16K
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self_dtcm_size = 16K
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heap_reserve = cm7_1_heap_reserve
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stack_reserve = (cm7_1_stack_reserve + (ecc_init_width - 1)) & (~((ecc_init_width - 1))) // Ensure that stack size is an integer multiple of ECC init width (round up)
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sram_offset = cm7_1_sram_offset
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sram_reserve = cm7_1_sram_reserve
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code_flash_offset = cm7_1_code_flash_offset
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code_flash_reserve = cm7_1_code_flash_reserve
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intvec_alignment = cm7_intvec_alignment
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#endif
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}
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MEMORY
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{
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SELF_ITCM : ORIGIN = 0x00000000, LENGTH = self_itcm_size
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CODE_FLASH : ORIGIN = 0x10000000 + code_flash_offset, LENGTH = code_flash_reserve
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WORK_FLASH : ORIGIN = 0x14000000, LENGTH = 0x00040000 // 256 KB
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SFLASH : ORIGIN = 0x17000000, LENGTH = 0x00008000 // 32 KB
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SFLASH_ALT : ORIGIN = 0x17800000, LENGTH = 0x00008000 // 32 KB
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SELF_DTCM : ORIGIN = 0x20000000, LENGTH = self_dtcm_size
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SRAM : ORIGIN = sram_base + sram_offset, LENGTH = sram_reserve
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SMIF0_DEV0_MEMMAPPED : ORIGIN = 0x60000000, LENGTH = 0x04000000 // 64 MB
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SMIF0_DEV1_MEMMAPPED : ORIGIN = 0x64000000, LENGTH = 0x04000000 // 64 MB
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CM7_0_ITCM : ORIGIN = 0xa0000000, LENGTH = 0x00004000 // 16 KB
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CM7_0_DTCM : ORIGIN = 0xa0010000, LENGTH = 0x00004000 // 16 KB
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CM7_1_ITCM : ORIGIN = 0xa0100000, LENGTH = 0x00004000 // 16 KB
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CM7_1_DTCM : ORIGIN = 0xa0110000, LENGTH = 0x00004000 // 16 KB
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}
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// Note: The SMIFx_DEVy_MEMMAPPED size is not fixed within a SMIFx instance and can be changed according to the actual SMIF user configuration.
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// This linker file just evenly distributes the available memory to all SMIF devices.
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