feat: update CAN integration and T2G seat firmware
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/***************************************************************************//**
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* \file cy_device_headers.h
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*
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* \brief
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* Common header file to be included by the drivers.
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*
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* \note
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* Generator version: 1.5.0.1277
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* Database revision: TVIIBH8M_B0_CFR_WW1922
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
|
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* the software package with which this file was provided.
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*******************************************************************************/
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#ifndef _CY_DEVICE_HEADERS_H_
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#define _CY_DEVICE_HEADERS_H_
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#if defined (CYT4BF8CES)
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#include "cyt4bf8ces.h"
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#elif defined (CYT4BF8CEE)
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#include "cyt4bf8cee.h"
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#elif defined (CYT4BF8CDS)
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#include "cyt4bf8cds.h"
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#elif defined (CYT4BF8CDE)
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#include "cyt4bf8cde.h"
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#elif defined (CYT4BFBCJS)
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#include "cyt4bfbcjs.h"
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#elif defined (CYT4BFBCJE)
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#include "cyt4bfbcje.h"
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#elif defined (CYT4BFBCHS)
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#include "cyt4bfbchs.h"
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#elif defined (CYT4BFBCHE)
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#include "cyt4bfbche.h"
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#elif defined (CYT4BFCCJS)
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#include "cyt4bfccjs.h"
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#elif defined (CYT4BFCCJE)
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#include "cyt4bfccje.h"
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#elif defined (CYT4BFCCHS)
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#include "cyt4bfcchs.h"
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#elif defined (CYT4BFCCHE)
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#include "cyt4bfcche.h"
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#elif defined (CYT4A0100S)
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#include "cyt4a0100s.h"
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#else
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#error Undefined part number
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#endif
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#endif /* _CY_DEVICE_HEADERS_H_ */
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/* [] END OF FILE */
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/***************************************************************************//**
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* \file cyip_backup_v3.h
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*
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* \brief
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* BACKUP IP definitions
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*
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* \note
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* Generator version: 1.5.0.1277
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* Database revision: TVIIBH8M_B0_CFR_WW1922
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#ifndef _CYIP_BACKUP_V3_H_
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#define _CYIP_BACKUP_V3_H_
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#include "cyip_headers.h"
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/*******************************************************************************
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* BACKUP
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*******************************************************************************/
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#define BACKUP_SECTION_SIZE 0x00010000UL
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/**
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* \brief Control (BACKUP_CTL)
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*/
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typedef struct stc_BACKUP_CTL_field {
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uint32_t :3;
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uint32_t u1WCO_EN:1;
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uint32_t :4;
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uint32_t u2CLK_SEL:2;
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uint32_t :2;
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uint32_t u2PRESCALER:2;
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uint32_t :2;
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uint32_t u1WCO_BYPASS:1;
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uint32_t u2VDDBAK_CTL:2;
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uint32_t u1VBACKUP_MEAS:1;
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uint32_t :4;
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uint32_t u8EN_CHARGE_KEY:8;
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} stc_BACKUP_CTL_field_t;
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typedef union un_BACKUP_CTL {
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uint32_t u32Register;
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stc_BACKUP_CTL_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_CTL_t;
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/**
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* \brief RTC Read Write register (BACKUP_RTC_RW)
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*/
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typedef struct stc_BACKUP_RTC_RW_field {
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uint32_t u1READ:1;
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uint32_t u1WRITE:1;
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uint32_t :30;
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} stc_BACKUP_RTC_RW_field_t;
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typedef union un_BACKUP_RTC_RW {
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uint32_t u32Register;
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stc_BACKUP_RTC_RW_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_RTC_RW_t;
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/**
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* \brief Oscillator calibration for absolute frequency (BACKUP_CAL_CTL)
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*/
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typedef struct stc_BACKUP_CAL_CTL_field {
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uint32_t u6CALIB_VAL:6;
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uint32_t u1CALIB_SIGN:1;
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uint32_t :21;
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uint32_t u2CAL_SEL:2;
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uint32_t :1;
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uint32_t u1CAL_OUT:1;
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} stc_BACKUP_CAL_CTL_field_t;
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typedef union un_BACKUP_CAL_CTL {
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uint32_t u32Register;
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stc_BACKUP_CAL_CTL_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_CAL_CTL_t;
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/**
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* \brief Status (BACKUP_STATUS)
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*/
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typedef struct stc_BACKUP_STATUS_field {
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uint32_t u1RTC_BUSY:1;
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uint32_t :1;
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uint32_t u1WCO_OK:1;
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uint32_t :29;
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} stc_BACKUP_STATUS_field_t;
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typedef union un_BACKUP_STATUS {
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uint32_t u32Register;
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stc_BACKUP_STATUS_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_STATUS_t;
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/**
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* \brief Calendar Seconds, Minutes, Hours, Day of Week (BACKUP_RTC_TIME)
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*/
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typedef struct stc_BACKUP_RTC_TIME_field {
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uint32_t u6RTC_SEC:6;
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uint32_t :2;
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uint32_t u6RTC_MIN:6;
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uint32_t :2;
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uint32_t u5RTC_HOUR:5;
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uint32_t :1;
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uint32_t u1CTRL_12HR:1;
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uint32_t :1;
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uint32_t u3RTC_DAY:3;
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uint32_t :5;
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} stc_BACKUP_RTC_TIME_field_t;
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typedef union un_BACKUP_RTC_TIME {
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uint32_t u32Register;
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stc_BACKUP_RTC_TIME_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_RTC_TIME_t;
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/**
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* \brief Calendar Day of Month, Month, Year (BACKUP_RTC_DATE)
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*/
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typedef struct stc_BACKUP_RTC_DATE_field {
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uint32_t u5RTC_DATE:5;
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uint32_t :3;
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uint32_t u4RTC_MON:4;
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uint32_t :4;
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uint32_t u7RTC_YEAR:7;
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uint32_t :9;
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} stc_BACKUP_RTC_DATE_field_t;
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typedef union un_BACKUP_RTC_DATE {
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uint32_t u32Register;
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stc_BACKUP_RTC_DATE_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_RTC_DATE_t;
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/**
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* \brief Alarm 1 Seconds, Minute, Hours, Day of Week (BACKUP_ALM1_TIME)
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*/
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typedef struct stc_BACKUP_ALM1_TIME_field {
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uint32_t u6ALM_SEC:6;
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uint32_t :1;
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uint32_t u1ALM_SEC_EN:1;
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uint32_t u6ALM_MIN:6;
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uint32_t :1;
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uint32_t u1ALM_MIN_EN:1;
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uint32_t u5ALM_HOUR:5;
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uint32_t :2;
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uint32_t u1ALM_HOUR_EN:1;
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uint32_t u3ALM_DAY:3;
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uint32_t :4;
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uint32_t u1ALM_DAY_EN:1;
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} stc_BACKUP_ALM1_TIME_field_t;
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typedef union un_BACKUP_ALM1_TIME {
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uint32_t u32Register;
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stc_BACKUP_ALM1_TIME_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_ALM1_TIME_t;
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/**
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* \brief Alarm 1 Day of Month, Month (BACKUP_ALM1_DATE)
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*/
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typedef struct stc_BACKUP_ALM1_DATE_field {
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uint32_t u5ALM_DATE:5;
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uint32_t :2;
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uint32_t u1ALM_DATE_EN:1;
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uint32_t u4ALM_MON:4;
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uint32_t :3;
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uint32_t u1ALM_MON_EN:1;
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uint32_t :15;
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uint32_t u1ALM_EN:1;
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} stc_BACKUP_ALM1_DATE_field_t;
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typedef union un_BACKUP_ALM1_DATE {
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uint32_t u32Register;
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stc_BACKUP_ALM1_DATE_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_ALM1_DATE_t;
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/**
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* \brief Alarm 2 Seconds, Minute, Hours, Day of Week (BACKUP_ALM2_TIME)
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*/
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typedef struct stc_BACKUP_ALM2_TIME_field {
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uint32_t u6ALM_SEC:6;
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uint32_t :1;
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uint32_t u1ALM_SEC_EN:1;
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uint32_t u6ALM_MIN:6;
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uint32_t :1;
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uint32_t u1ALM_MIN_EN:1;
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uint32_t u5ALM_HOUR:5;
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uint32_t :2;
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uint32_t u1ALM_HOUR_EN:1;
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uint32_t u3ALM_DAY:3;
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uint32_t :4;
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uint32_t u1ALM_DAY_EN:1;
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} stc_BACKUP_ALM2_TIME_field_t;
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typedef union un_BACKUP_ALM2_TIME {
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uint32_t u32Register;
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stc_BACKUP_ALM2_TIME_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_ALM2_TIME_t;
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/**
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* \brief Alarm 2 Day of Month, Month (BACKUP_ALM2_DATE)
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*/
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typedef struct stc_BACKUP_ALM2_DATE_field {
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uint32_t u5ALM_DATE:5;
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uint32_t :2;
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uint32_t u1ALM_DATE_EN:1;
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uint32_t u4ALM_MON:4;
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uint32_t :3;
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uint32_t u1ALM_MON_EN:1;
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uint32_t :15;
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uint32_t u1ALM_EN:1;
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} stc_BACKUP_ALM2_DATE_field_t;
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typedef union un_BACKUP_ALM2_DATE {
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uint32_t u32Register;
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stc_BACKUP_ALM2_DATE_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_ALM2_DATE_t;
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/**
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* \brief Interrupt request register (BACKUP_INTR)
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*/
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typedef struct stc_BACKUP_INTR_field {
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uint32_t u1ALARM1:1;
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uint32_t u1ALARM2:1;
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uint32_t u1CENTURY:1;
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uint32_t :29;
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} stc_BACKUP_INTR_field_t;
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typedef union un_BACKUP_INTR {
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uint32_t u32Register;
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stc_BACKUP_INTR_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_INTR_t;
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/**
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* \brief Interrupt set request register (BACKUP_INTR_SET)
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*/
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typedef struct stc_BACKUP_INTR_SET_field {
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uint32_t u1ALARM1:1;
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uint32_t u1ALARM2:1;
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uint32_t u1CENTURY:1;
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uint32_t :29;
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} stc_BACKUP_INTR_SET_field_t;
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typedef union un_BACKUP_INTR_SET {
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uint32_t u32Register;
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stc_BACKUP_INTR_SET_field_t stcField;
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uint8_t au8Byte[4];
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uint16_t au16Halfword[2];
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} un_BACKUP_INTR_SET_t;
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/**
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* \brief Interrupt mask register (BACKUP_INTR_MASK)
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*/
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typedef struct stc_BACKUP_INTR_MASK_field {
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uint32_t u1ALARM1:1;
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uint32_t u1ALARM2:1;
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uint32_t u1CENTURY:1;
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uint32_t :29;
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} stc_BACKUP_INTR_MASK_field_t;
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||||
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typedef union un_BACKUP_INTR_MASK {
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uint32_t u32Register;
|
||||
stc_BACKUP_INTR_MASK_field_t stcField;
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uint8_t au8Byte[4];
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||||
uint16_t au16Halfword[2];
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} un_BACKUP_INTR_MASK_t;
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||||
|
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/**
|
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* \brief Interrupt masked request register (BACKUP_INTR_MASKED)
|
||||
*/
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typedef struct stc_BACKUP_INTR_MASKED_field {
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||||
uint32_t u1ALARM1:1;
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||||
uint32_t u1ALARM2:1;
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||||
uint32_t u1CENTURY:1;
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||||
uint32_t :29;
|
||||
} stc_BACKUP_INTR_MASKED_field_t;
|
||||
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||||
typedef union un_BACKUP_INTR_MASKED {
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||||
uint32_t u32Register;
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||||
stc_BACKUP_INTR_MASKED_field_t stcField;
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||||
uint8_t au8Byte[4];
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||||
uint16_t au16Halfword[2];
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||||
} un_BACKUP_INTR_MASKED_t;
|
||||
|
||||
/**
|
||||
* \brief PMIC control register (BACKUP_PMIC_CTL)
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||||
*/
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||||
typedef struct stc_BACKUP_PMIC_CTL_field {
|
||||
uint32_t :8;
|
||||
uint32_t u8UNLOCK:8;
|
||||
uint32_t u1POLARITY:1;
|
||||
uint32_t :12;
|
||||
uint32_t u1PMIC_EN_OUTEN:1;
|
||||
uint32_t u1PMIC_ALWAYSEN:1;
|
||||
uint32_t u1PMIC_EN:1;
|
||||
} stc_BACKUP_PMIC_CTL_field_t;
|
||||
|
||||
typedef union un_BACKUP_PMIC_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_BACKUP_PMIC_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_BACKUP_PMIC_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Backup reset register (BACKUP_RESET)
|
||||
*/
|
||||
typedef struct stc_BACKUP_RESET_field {
|
||||
uint32_t :31;
|
||||
uint32_t u1RESET:1;
|
||||
} stc_BACKUP_RESET_field_t;
|
||||
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||||
typedef union un_BACKUP_RESET {
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||||
uint32_t u32Register;
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||||
stc_BACKUP_RESET_field_t stcField;
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||||
uint8_t au8Byte[4];
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||||
uint16_t au16Halfword[2];
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||||
} un_BACKUP_RESET_t;
|
||||
|
||||
/**
|
||||
* \brief Low-power external crystal oscillator control (BACKUP_LPECO_CTL)
|
||||
*/
|
||||
typedef struct stc_BACKUP_LPECO_CTL_field {
|
||||
uint32_t :4;
|
||||
uint32_t u2LPECO_CRANGE:2;
|
||||
uint32_t :2;
|
||||
uint32_t u1LPECO_FRANGE:1;
|
||||
uint32_t :3;
|
||||
uint32_t u1LPECO_AMP_SEL:1;
|
||||
uint32_t :15;
|
||||
uint32_t u1LPECO_DIV_ENABLE:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1LPECO_AMPDET_EN:1;
|
||||
uint32_t u1LPECO_EN:1;
|
||||
} stc_BACKUP_LPECO_CTL_field_t;
|
||||
|
||||
typedef union un_BACKUP_LPECO_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_BACKUP_LPECO_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_BACKUP_LPECO_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Low-power external crystal oscillator prescaler (BACKUP_LPECO_PRESCALE)
|
||||
*/
|
||||
typedef struct stc_BACKUP_LPECO_PRESCALE_field {
|
||||
uint32_t u1LPECO_DIV_ENABLED:1;
|
||||
uint32_t :7;
|
||||
uint32_t u8LPECO_FRAC_DIV:8;
|
||||
uint32_t u10LPECO_INT_DIV:10;
|
||||
uint32_t :6;
|
||||
} stc_BACKUP_LPECO_PRESCALE_field_t;
|
||||
|
||||
typedef union un_BACKUP_LPECO_PRESCALE {
|
||||
uint32_t u32Register;
|
||||
stc_BACKUP_LPECO_PRESCALE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_BACKUP_LPECO_PRESCALE_t;
|
||||
|
||||
/**
|
||||
* \brief Low-power external crystal oscillator status (BACKUP_LPECO_STATUS)
|
||||
*/
|
||||
typedef struct stc_BACKUP_LPECO_STATUS_field {
|
||||
uint32_t u1LPECO_AMPDET_OK:1;
|
||||
uint32_t u1LPECO_READY:1;
|
||||
uint32_t :30;
|
||||
} stc_BACKUP_LPECO_STATUS_field_t;
|
||||
|
||||
typedef union un_BACKUP_LPECO_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_BACKUP_LPECO_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_BACKUP_LPECO_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Backup register region (BACKUP_BREG)
|
||||
*/
|
||||
typedef struct stc_BACKUP_BREG_field {
|
||||
uint32_t u32BREG:32;
|
||||
} stc_BACKUP_BREG_field_t;
|
||||
|
||||
typedef union un_BACKUP_BREG {
|
||||
uint32_t u32Register;
|
||||
stc_BACKUP_BREG_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_BACKUP_BREG_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief SRSS Backup Domain (ver3) (BACKUP)
|
||||
*/
|
||||
typedef struct stc_BACKUP {
|
||||
un_BACKUP_CTL_t unCTL; /*!< 0x00000000 Control */
|
||||
uint32_t u32Reserved;
|
||||
un_BACKUP_RTC_RW_t unRTC_RW; /*!< 0x00000008 RTC Read Write register */
|
||||
un_BACKUP_CAL_CTL_t unCAL_CTL; /*!< 0x0000000C Oscillator calibration for absolute frequency */
|
||||
un_BACKUP_STATUS_t unSTATUS; /*!< 0x00000010 Status */
|
||||
un_BACKUP_RTC_TIME_t unRTC_TIME; /*!< 0x00000014 Calendar Seconds, Minutes, Hours, Day of Week */
|
||||
un_BACKUP_RTC_DATE_t unRTC_DATE; /*!< 0x00000018 Calendar Day of Month, Month, Year */
|
||||
un_BACKUP_ALM1_TIME_t unALM1_TIME; /*!< 0x0000001C Alarm 1 Seconds, Minute, Hours, Day of Week */
|
||||
un_BACKUP_ALM1_DATE_t unALM1_DATE; /*!< 0x00000020 Alarm 1 Day of Month, Month */
|
||||
un_BACKUP_ALM2_TIME_t unALM2_TIME; /*!< 0x00000024 Alarm 2 Seconds, Minute, Hours, Day of Week */
|
||||
un_BACKUP_ALM2_DATE_t unALM2_DATE; /*!< 0x00000028 Alarm 2 Day of Month, Month */
|
||||
un_BACKUP_INTR_t unINTR; /*!< 0x0000002C Interrupt request register */
|
||||
un_BACKUP_INTR_SET_t unINTR_SET; /*!< 0x00000030 Interrupt set request register */
|
||||
un_BACKUP_INTR_MASK_t unINTR_MASK; /*!< 0x00000034 Interrupt mask register */
|
||||
un_BACKUP_INTR_MASKED_t unINTR_MASKED; /*!< 0x00000038 Interrupt masked request register */
|
||||
uint32_t au32Reserved1[2];
|
||||
un_BACKUP_PMIC_CTL_t unPMIC_CTL; /*!< 0x00000044 PMIC control register */
|
||||
un_BACKUP_RESET_t unRESET; /*!< 0x00000048 Backup reset register */
|
||||
uint32_t au32Reserved2[13];
|
||||
un_BACKUP_LPECO_CTL_t unLPECO_CTL; /*!< 0x00000080 Low-power external crystal oscillator control */
|
||||
un_BACKUP_LPECO_PRESCALE_t unLPECO_PRESCALE; /*!< 0x00000084 Low-power external crystal oscillator prescaler */
|
||||
un_BACKUP_LPECO_STATUS_t unLPECO_STATUS; /*!< 0x00000088 Low-power external crystal oscillator status */
|
||||
uint32_t au32Reserved3[989];
|
||||
un_BACKUP_BREG_t unBREG[64]; /*!< 0x00001000 Backup register region */
|
||||
} stc_BACKUP_t; /*!< Size = 4352 (0x1100) */
|
||||
|
||||
|
||||
/* BACKUP.CTL */
|
||||
#define BACKUP_CTL_WCO_EN_Pos 3UL
|
||||
#define BACKUP_CTL_WCO_EN_Msk 0x8UL
|
||||
#define BACKUP_CTL_CLK_SEL_Pos 8UL
|
||||
#define BACKUP_CTL_CLK_SEL_Msk 0x300UL
|
||||
#define BACKUP_CTL_PRESCALER_Pos 12UL
|
||||
#define BACKUP_CTL_PRESCALER_Msk 0x3000UL
|
||||
#define BACKUP_CTL_WCO_BYPASS_Pos 16UL
|
||||
#define BACKUP_CTL_WCO_BYPASS_Msk 0x10000UL
|
||||
#define BACKUP_CTL_VDDBAK_CTL_Pos 17UL
|
||||
#define BACKUP_CTL_VDDBAK_CTL_Msk 0x60000UL
|
||||
#define BACKUP_CTL_VBACKUP_MEAS_Pos 19UL
|
||||
#define BACKUP_CTL_VBACKUP_MEAS_Msk 0x80000UL
|
||||
#define BACKUP_CTL_EN_CHARGE_KEY_Pos 24UL
|
||||
#define BACKUP_CTL_EN_CHARGE_KEY_Msk 0xFF000000UL
|
||||
/* BACKUP.RTC_RW */
|
||||
#define BACKUP_RTC_RW_READ_Pos 0UL
|
||||
#define BACKUP_RTC_RW_READ_Msk 0x1UL
|
||||
#define BACKUP_RTC_RW_WRITE_Pos 1UL
|
||||
#define BACKUP_RTC_RW_WRITE_Msk 0x2UL
|
||||
/* BACKUP.CAL_CTL */
|
||||
#define BACKUP_CAL_CTL_CALIB_VAL_Pos 0UL
|
||||
#define BACKUP_CAL_CTL_CALIB_VAL_Msk 0x3FUL
|
||||
#define BACKUP_CAL_CTL_CALIB_SIGN_Pos 6UL
|
||||
#define BACKUP_CAL_CTL_CALIB_SIGN_Msk 0x40UL
|
||||
#define BACKUP_CAL_CTL_CAL_SEL_Pos 28UL
|
||||
#define BACKUP_CAL_CTL_CAL_SEL_Msk 0x30000000UL
|
||||
#define BACKUP_CAL_CTL_CAL_OUT_Pos 31UL
|
||||
#define BACKUP_CAL_CTL_CAL_OUT_Msk 0x80000000UL
|
||||
/* BACKUP.STATUS */
|
||||
#define BACKUP_STATUS_RTC_BUSY_Pos 0UL
|
||||
#define BACKUP_STATUS_RTC_BUSY_Msk 0x1UL
|
||||
#define BACKUP_STATUS_WCO_OK_Pos 2UL
|
||||
#define BACKUP_STATUS_WCO_OK_Msk 0x4UL
|
||||
/* BACKUP.RTC_TIME */
|
||||
#define BACKUP_RTC_TIME_RTC_SEC_Pos 0UL
|
||||
#define BACKUP_RTC_TIME_RTC_SEC_Msk 0x3FUL
|
||||
#define BACKUP_RTC_TIME_RTC_MIN_Pos 8UL
|
||||
#define BACKUP_RTC_TIME_RTC_MIN_Msk 0x3F00UL
|
||||
#define BACKUP_RTC_TIME_RTC_HOUR_Pos 16UL
|
||||
#define BACKUP_RTC_TIME_RTC_HOUR_Msk 0x1F0000UL
|
||||
#define BACKUP_RTC_TIME_CTRL_12HR_Pos 22UL
|
||||
#define BACKUP_RTC_TIME_CTRL_12HR_Msk 0x400000UL
|
||||
#define BACKUP_RTC_TIME_RTC_DAY_Pos 24UL
|
||||
#define BACKUP_RTC_TIME_RTC_DAY_Msk 0x7000000UL
|
||||
/* BACKUP.RTC_DATE */
|
||||
#define BACKUP_RTC_DATE_RTC_DATE_Pos 0UL
|
||||
#define BACKUP_RTC_DATE_RTC_DATE_Msk 0x1FUL
|
||||
#define BACKUP_RTC_DATE_RTC_MON_Pos 8UL
|
||||
#define BACKUP_RTC_DATE_RTC_MON_Msk 0xF00UL
|
||||
#define BACKUP_RTC_DATE_RTC_YEAR_Pos 16UL
|
||||
#define BACKUP_RTC_DATE_RTC_YEAR_Msk 0x7F0000UL
|
||||
/* BACKUP.ALM1_TIME */
|
||||
#define BACKUP_ALM1_TIME_ALM_SEC_Pos 0UL
|
||||
#define BACKUP_ALM1_TIME_ALM_SEC_Msk 0x3FUL
|
||||
#define BACKUP_ALM1_TIME_ALM_SEC_EN_Pos 7UL
|
||||
#define BACKUP_ALM1_TIME_ALM_SEC_EN_Msk 0x80UL
|
||||
#define BACKUP_ALM1_TIME_ALM_MIN_Pos 8UL
|
||||
#define BACKUP_ALM1_TIME_ALM_MIN_Msk 0x3F00UL
|
||||
#define BACKUP_ALM1_TIME_ALM_MIN_EN_Pos 15UL
|
||||
#define BACKUP_ALM1_TIME_ALM_MIN_EN_Msk 0x8000UL
|
||||
#define BACKUP_ALM1_TIME_ALM_HOUR_Pos 16UL
|
||||
#define BACKUP_ALM1_TIME_ALM_HOUR_Msk 0x1F0000UL
|
||||
#define BACKUP_ALM1_TIME_ALM_HOUR_EN_Pos 23UL
|
||||
#define BACKUP_ALM1_TIME_ALM_HOUR_EN_Msk 0x800000UL
|
||||
#define BACKUP_ALM1_TIME_ALM_DAY_Pos 24UL
|
||||
#define BACKUP_ALM1_TIME_ALM_DAY_Msk 0x7000000UL
|
||||
#define BACKUP_ALM1_TIME_ALM_DAY_EN_Pos 31UL
|
||||
#define BACKUP_ALM1_TIME_ALM_DAY_EN_Msk 0x80000000UL
|
||||
/* BACKUP.ALM1_DATE */
|
||||
#define BACKUP_ALM1_DATE_ALM_DATE_Pos 0UL
|
||||
#define BACKUP_ALM1_DATE_ALM_DATE_Msk 0x1FUL
|
||||
#define BACKUP_ALM1_DATE_ALM_DATE_EN_Pos 7UL
|
||||
#define BACKUP_ALM1_DATE_ALM_DATE_EN_Msk 0x80UL
|
||||
#define BACKUP_ALM1_DATE_ALM_MON_Pos 8UL
|
||||
#define BACKUP_ALM1_DATE_ALM_MON_Msk 0xF00UL
|
||||
#define BACKUP_ALM1_DATE_ALM_MON_EN_Pos 15UL
|
||||
#define BACKUP_ALM1_DATE_ALM_MON_EN_Msk 0x8000UL
|
||||
#define BACKUP_ALM1_DATE_ALM_EN_Pos 31UL
|
||||
#define BACKUP_ALM1_DATE_ALM_EN_Msk 0x80000000UL
|
||||
/* BACKUP.ALM2_TIME */
|
||||
#define BACKUP_ALM2_TIME_ALM_SEC_Pos 0UL
|
||||
#define BACKUP_ALM2_TIME_ALM_SEC_Msk 0x3FUL
|
||||
#define BACKUP_ALM2_TIME_ALM_SEC_EN_Pos 7UL
|
||||
#define BACKUP_ALM2_TIME_ALM_SEC_EN_Msk 0x80UL
|
||||
#define BACKUP_ALM2_TIME_ALM_MIN_Pos 8UL
|
||||
#define BACKUP_ALM2_TIME_ALM_MIN_Msk 0x3F00UL
|
||||
#define BACKUP_ALM2_TIME_ALM_MIN_EN_Pos 15UL
|
||||
#define BACKUP_ALM2_TIME_ALM_MIN_EN_Msk 0x8000UL
|
||||
#define BACKUP_ALM2_TIME_ALM_HOUR_Pos 16UL
|
||||
#define BACKUP_ALM2_TIME_ALM_HOUR_Msk 0x1F0000UL
|
||||
#define BACKUP_ALM2_TIME_ALM_HOUR_EN_Pos 23UL
|
||||
#define BACKUP_ALM2_TIME_ALM_HOUR_EN_Msk 0x800000UL
|
||||
#define BACKUP_ALM2_TIME_ALM_DAY_Pos 24UL
|
||||
#define BACKUP_ALM2_TIME_ALM_DAY_Msk 0x7000000UL
|
||||
#define BACKUP_ALM2_TIME_ALM_DAY_EN_Pos 31UL
|
||||
#define BACKUP_ALM2_TIME_ALM_DAY_EN_Msk 0x80000000UL
|
||||
/* BACKUP.ALM2_DATE */
|
||||
#define BACKUP_ALM2_DATE_ALM_DATE_Pos 0UL
|
||||
#define BACKUP_ALM2_DATE_ALM_DATE_Msk 0x1FUL
|
||||
#define BACKUP_ALM2_DATE_ALM_DATE_EN_Pos 7UL
|
||||
#define BACKUP_ALM2_DATE_ALM_DATE_EN_Msk 0x80UL
|
||||
#define BACKUP_ALM2_DATE_ALM_MON_Pos 8UL
|
||||
#define BACKUP_ALM2_DATE_ALM_MON_Msk 0xF00UL
|
||||
#define BACKUP_ALM2_DATE_ALM_MON_EN_Pos 15UL
|
||||
#define BACKUP_ALM2_DATE_ALM_MON_EN_Msk 0x8000UL
|
||||
#define BACKUP_ALM2_DATE_ALM_EN_Pos 31UL
|
||||
#define BACKUP_ALM2_DATE_ALM_EN_Msk 0x80000000UL
|
||||
/* BACKUP.INTR */
|
||||
#define BACKUP_INTR_ALARM1_Pos 0UL
|
||||
#define BACKUP_INTR_ALARM1_Msk 0x1UL
|
||||
#define BACKUP_INTR_ALARM2_Pos 1UL
|
||||
#define BACKUP_INTR_ALARM2_Msk 0x2UL
|
||||
#define BACKUP_INTR_CENTURY_Pos 2UL
|
||||
#define BACKUP_INTR_CENTURY_Msk 0x4UL
|
||||
/* BACKUP.INTR_SET */
|
||||
#define BACKUP_INTR_SET_ALARM1_Pos 0UL
|
||||
#define BACKUP_INTR_SET_ALARM1_Msk 0x1UL
|
||||
#define BACKUP_INTR_SET_ALARM2_Pos 1UL
|
||||
#define BACKUP_INTR_SET_ALARM2_Msk 0x2UL
|
||||
#define BACKUP_INTR_SET_CENTURY_Pos 2UL
|
||||
#define BACKUP_INTR_SET_CENTURY_Msk 0x4UL
|
||||
/* BACKUP.INTR_MASK */
|
||||
#define BACKUP_INTR_MASK_ALARM1_Pos 0UL
|
||||
#define BACKUP_INTR_MASK_ALARM1_Msk 0x1UL
|
||||
#define BACKUP_INTR_MASK_ALARM2_Pos 1UL
|
||||
#define BACKUP_INTR_MASK_ALARM2_Msk 0x2UL
|
||||
#define BACKUP_INTR_MASK_CENTURY_Pos 2UL
|
||||
#define BACKUP_INTR_MASK_CENTURY_Msk 0x4UL
|
||||
/* BACKUP.INTR_MASKED */
|
||||
#define BACKUP_INTR_MASKED_ALARM1_Pos 0UL
|
||||
#define BACKUP_INTR_MASKED_ALARM1_Msk 0x1UL
|
||||
#define BACKUP_INTR_MASKED_ALARM2_Pos 1UL
|
||||
#define BACKUP_INTR_MASKED_ALARM2_Msk 0x2UL
|
||||
#define BACKUP_INTR_MASKED_CENTURY_Pos 2UL
|
||||
#define BACKUP_INTR_MASKED_CENTURY_Msk 0x4UL
|
||||
/* BACKUP.PMIC_CTL */
|
||||
#define BACKUP_PMIC_CTL_UNLOCK_Pos 8UL
|
||||
#define BACKUP_PMIC_CTL_UNLOCK_Msk 0xFF00UL
|
||||
#define BACKUP_PMIC_CTL_POLARITY_Pos 16UL
|
||||
#define BACKUP_PMIC_CTL_POLARITY_Msk 0x10000UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Pos 29UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Msk 0x20000000UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Pos 30UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Msk 0x40000000UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_EN_Pos 31UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_EN_Msk 0x80000000UL
|
||||
/* BACKUP.RESET */
|
||||
#define BACKUP_RESET_RESET_Pos 31UL
|
||||
#define BACKUP_RESET_RESET_Msk 0x80000000UL
|
||||
/* BACKUP.LPECO_CTL */
|
||||
#define BACKUP_LPECO_CTL_LPECO_CRANGE_Pos 4UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_CRANGE_Msk 0x30UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_FRANGE_Pos 8UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_FRANGE_Msk 0x100UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_AMP_SEL_Pos 12UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_AMP_SEL_Msk 0x1000UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_DIV_ENABLE_Pos 28UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_DIV_ENABLE_Msk 0x10000000UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_AMPDET_EN_Pos 30UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_AMPDET_EN_Msk 0x40000000UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_EN_Pos 31UL
|
||||
#define BACKUP_LPECO_CTL_LPECO_EN_Msk 0x80000000UL
|
||||
/* BACKUP.LPECO_PRESCALE */
|
||||
#define BACKUP_LPECO_PRESCALE_LPECO_DIV_ENABLED_Pos 0UL
|
||||
#define BACKUP_LPECO_PRESCALE_LPECO_DIV_ENABLED_Msk 0x1UL
|
||||
#define BACKUP_LPECO_PRESCALE_LPECO_FRAC_DIV_Pos 8UL
|
||||
#define BACKUP_LPECO_PRESCALE_LPECO_FRAC_DIV_Msk 0xFF00UL
|
||||
#define BACKUP_LPECO_PRESCALE_LPECO_INT_DIV_Pos 16UL
|
||||
#define BACKUP_LPECO_PRESCALE_LPECO_INT_DIV_Msk 0x3FF0000UL
|
||||
/* BACKUP.LPECO_STATUS */
|
||||
#define BACKUP_LPECO_STATUS_LPECO_AMPDET_OK_Pos 0UL
|
||||
#define BACKUP_LPECO_STATUS_LPECO_AMPDET_OK_Msk 0x1UL
|
||||
#define BACKUP_LPECO_STATUS_LPECO_READY_Pos 1UL
|
||||
#define BACKUP_LPECO_STATUS_LPECO_READY_Msk 0x2UL
|
||||
/* BACKUP.BREG */
|
||||
#define BACKUP_BREG_BREG_Pos 0UL
|
||||
#define BACKUP_BREG_BREG_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_BACKUP_V3_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,594 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_dmac.h
|
||||
*
|
||||
* \brief
|
||||
* DMAC IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_DMAC_H_
|
||||
#define _CYIP_DMAC_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* DMAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define DMAC_CH_SECTION_SIZE 0x00000100UL
|
||||
#define DMAC_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Channel control (DMAC_CH_CTL)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t u1B:1;
|
||||
uint32_t :1;
|
||||
uint32_t u4PC:4;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :21;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_DMAC_CH_CTL_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Channel current indices (DMAC_CH_IDX)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_IDX_field {
|
||||
uint32_t u16X:16;
|
||||
uint32_t u16Y:16;
|
||||
} stc_DMAC_CH_IDX_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_IDX {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_IDX_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_IDX_t;
|
||||
|
||||
/**
|
||||
* \brief Channel current source address (DMAC_CH_SRC)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_SRC_field {
|
||||
uint32_t u32ADDR:32;
|
||||
} stc_DMAC_CH_SRC_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_SRC {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_SRC_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_SRC_t;
|
||||
|
||||
/**
|
||||
* \brief Channel current destination address (DMAC_CH_DST)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_DST_field {
|
||||
uint32_t u32ADDR:32;
|
||||
} stc_DMAC_CH_DST_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_DST {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_DST_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_DST_t;
|
||||
|
||||
/**
|
||||
* \brief Channel current descriptor pointer (DMAC_CH_CURR)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_CURR_field {
|
||||
uint32_t :2;
|
||||
uint32_t u30PTR:30;
|
||||
} stc_DMAC_CH_CURR_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_CURR {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_CURR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_CURR_t;
|
||||
|
||||
/**
|
||||
* \brief Channle software trigger (DMAC_CH_TR_CMD)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_TR_CMD_field {
|
||||
uint32_t u1ACTIVATE:1;
|
||||
uint32_t :31;
|
||||
} stc_DMAC_CH_TR_CMD_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_TR_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_TR_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_TR_CMD_t;
|
||||
|
||||
/**
|
||||
* \brief Channel descriptor status (DMAC_CH_DESCR_STATUS)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_DESCR_STATUS_field {
|
||||
uint32_t :31;
|
||||
uint32_t u1VALID:1;
|
||||
} stc_DMAC_CH_DESCR_STATUS_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_DESCR_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_DESCR_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_DESCR_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Channel descriptor control (DMAC_CH_DESCR_CTL)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_DESCR_CTL_field {
|
||||
uint32_t u2WAIT_FOR_DEACT:2;
|
||||
uint32_t u2INTR_TYPE:2;
|
||||
uint32_t u2TR_OUT_TYPE:2;
|
||||
uint32_t u2TR_IN_TYPE:2;
|
||||
uint32_t u1DATA_PREFETCH:1;
|
||||
uint32_t :7;
|
||||
uint32_t u2DATA_SIZE:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1CH_DISABLE:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1SRC_TRANSFER_SIZE:1;
|
||||
uint32_t u1DST_TRANSFER_SIZE:1;
|
||||
uint32_t u3DESCR_TYPE:3;
|
||||
} stc_DMAC_CH_DESCR_CTL_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_DESCR_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_DESCR_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_DESCR_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Channel descriptor source (DMAC_CH_DESCR_SRC)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_DESCR_SRC_field {
|
||||
uint32_t u32ADDR:32;
|
||||
} stc_DMAC_CH_DESCR_SRC_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_DESCR_SRC {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_DESCR_SRC_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_DESCR_SRC_t;
|
||||
|
||||
/**
|
||||
* \brief Channel descriptor destination (DMAC_CH_DESCR_DST)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_DESCR_DST_field {
|
||||
uint32_t u32ADDR:32;
|
||||
} stc_DMAC_CH_DESCR_DST_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_DESCR_DST {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_DESCR_DST_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_DESCR_DST_t;
|
||||
|
||||
/**
|
||||
* \brief Channel descriptor X size (DMAC_CH_DESCR_X_SIZE)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_DESCR_X_SIZE_field {
|
||||
uint32_t u16X_COUNT:16;
|
||||
uint32_t :16;
|
||||
} stc_DMAC_CH_DESCR_X_SIZE_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_DESCR_X_SIZE {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_DESCR_X_SIZE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_DESCR_X_SIZE_t;
|
||||
|
||||
/**
|
||||
* \brief Channel descriptor X increment (DMAC_CH_DESCR_X_INCR)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_DESCR_X_INCR_field {
|
||||
uint32_t u16SRC_X:16;
|
||||
uint32_t u16DST_X:16;
|
||||
} stc_DMAC_CH_DESCR_X_INCR_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_DESCR_X_INCR {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_DESCR_X_INCR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_DESCR_X_INCR_t;
|
||||
|
||||
/**
|
||||
* \brief Channel descriptor Y size (DMAC_CH_DESCR_Y_SIZE)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_DESCR_Y_SIZE_field {
|
||||
uint32_t u16Y_COUNT:16;
|
||||
uint32_t :16;
|
||||
} stc_DMAC_CH_DESCR_Y_SIZE_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_DESCR_Y_SIZE {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_DESCR_Y_SIZE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_DESCR_Y_SIZE_t;
|
||||
|
||||
/**
|
||||
* \brief Channel descriptor Y increment (DMAC_CH_DESCR_Y_INCR)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_DESCR_Y_INCR_field {
|
||||
uint32_t u16SRC_Y:16;
|
||||
uint32_t u16DST_Y:16;
|
||||
} stc_DMAC_CH_DESCR_Y_INCR_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_DESCR_Y_INCR {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_DESCR_Y_INCR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_DESCR_Y_INCR_t;
|
||||
|
||||
/**
|
||||
* \brief Channel descriptor next pointer (DMAC_CH_DESCR_NEXT)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_DESCR_NEXT_field {
|
||||
uint32_t :2;
|
||||
uint32_t u30PTR:30;
|
||||
} stc_DMAC_CH_DESCR_NEXT_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_DESCR_NEXT {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_DESCR_NEXT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_DESCR_NEXT_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt (DMAC_CH_INTR)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_INTR_field {
|
||||
uint32_t u1COMPLETION:1;
|
||||
uint32_t u1SRC_BUS_ERROR:1;
|
||||
uint32_t u1DST_BUS_ERROR:1;
|
||||
uint32_t u1SRC_MISAL:1;
|
||||
uint32_t u1DST_MISAL:1;
|
||||
uint32_t u1CURR_PTR_NULL:1;
|
||||
uint32_t u1ACTIVE_CH_DISABLED:1;
|
||||
uint32_t u1DESCR_BUS_ERROR:1;
|
||||
uint32_t :24;
|
||||
} stc_DMAC_CH_INTR_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt set (DMAC_CH_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_INTR_SET_field {
|
||||
uint32_t u1COMPLETION:1;
|
||||
uint32_t u1SRC_BUS_ERROR:1;
|
||||
uint32_t u1DST_BUS_ERROR:1;
|
||||
uint32_t u1SRC_MISAL:1;
|
||||
uint32_t u1DST_MISAL:1;
|
||||
uint32_t u1CURR_PTR_NULL:1;
|
||||
uint32_t u1ACTIVE_CH_DISABLED:1;
|
||||
uint32_t u1DESCR_BUS_ERROR:1;
|
||||
uint32_t :24;
|
||||
} stc_DMAC_CH_INTR_SET_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt mask (DMAC_CH_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_INTR_MASK_field {
|
||||
uint32_t u1COMPLETION:1;
|
||||
uint32_t u1SRC_BUS_ERROR:1;
|
||||
uint32_t u1DST_BUS_ERROR:1;
|
||||
uint32_t u1SRC_MISAL:1;
|
||||
uint32_t u1DST_MISAL:1;
|
||||
uint32_t u1CURR_PTR_NULL:1;
|
||||
uint32_t u1ACTIVE_CH_DISABLED:1;
|
||||
uint32_t u1DESCR_BUS_ERROR:1;
|
||||
uint32_t :24;
|
||||
} stc_DMAC_CH_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt masked (DMAC_CH_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH_INTR_MASKED_field {
|
||||
uint32_t u1COMPLETION:1;
|
||||
uint32_t u1SRC_BUS_ERROR:1;
|
||||
uint32_t u1DST_BUS_ERROR:1;
|
||||
uint32_t u1SRC_MISAL:1;
|
||||
uint32_t u1DST_MISAL:1;
|
||||
uint32_t u1CURR_PTR_NULL:1;
|
||||
uint32_t u1ACTIVE_CH_DISABLED:1;
|
||||
uint32_t u1DESCR_BUS_ERROR:1;
|
||||
uint32_t :24;
|
||||
} stc_DMAC_CH_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_DMAC_CH_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CH_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CH_INTR_MASKED_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Control (DMAC_CTL)
|
||||
*/
|
||||
typedef struct stc_DMAC_CTL_field {
|
||||
uint32_t :31;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_DMAC_CTL_field_t;
|
||||
|
||||
typedef union un_DMAC_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Active channels (DMAC_ACTIVE)
|
||||
*/
|
||||
typedef struct stc_DMAC_ACTIVE_field {
|
||||
uint32_t u8ACTIVE:8;
|
||||
uint32_t :24;
|
||||
} stc_DMAC_ACTIVE_field_t;
|
||||
|
||||
typedef union un_DMAC_ACTIVE {
|
||||
uint32_t u32Register;
|
||||
stc_DMAC_ACTIVE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DMAC_ACTIVE_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief DMA controller channel (DMAC_CH)
|
||||
*/
|
||||
typedef struct stc_DMAC_CH {
|
||||
un_DMAC_CH_CTL_t unCTL; /*!< 0x00000000 Channel control */
|
||||
uint32_t au32Reserved[3];
|
||||
un_DMAC_CH_IDX_t unIDX; /*!< 0x00000010 Channel current indices */
|
||||
un_DMAC_CH_SRC_t unSRC; /*!< 0x00000014 Channel current source address */
|
||||
un_DMAC_CH_DST_t unDST; /*!< 0x00000018 Channel current destination address */
|
||||
uint32_t u32Reserved1;
|
||||
un_DMAC_CH_CURR_t unCURR; /*!< 0x00000020 Channel current descriptor pointer */
|
||||
uint32_t u32Reserved2;
|
||||
un_DMAC_CH_TR_CMD_t unTR_CMD; /*!< 0x00000028 Channle software trigger */
|
||||
uint32_t au32Reserved3[5];
|
||||
un_DMAC_CH_DESCR_STATUS_t unDESCR_STATUS; /*!< 0x00000040 Channel descriptor status */
|
||||
uint32_t au32Reserved4[7];
|
||||
un_DMAC_CH_DESCR_CTL_t unDESCR_CTL; /*!< 0x00000060 Channel descriptor control */
|
||||
un_DMAC_CH_DESCR_SRC_t unDESCR_SRC; /*!< 0x00000064 Channel descriptor source */
|
||||
un_DMAC_CH_DESCR_DST_t unDESCR_DST; /*!< 0x00000068 Channel descriptor destination */
|
||||
un_DMAC_CH_DESCR_X_SIZE_t unDESCR_X_SIZE; /*!< 0x0000006C Channel descriptor X size */
|
||||
un_DMAC_CH_DESCR_X_INCR_t unDESCR_X_INCR; /*!< 0x00000070 Channel descriptor X increment */
|
||||
un_DMAC_CH_DESCR_Y_SIZE_t unDESCR_Y_SIZE; /*!< 0x00000074 Channel descriptor Y size */
|
||||
un_DMAC_CH_DESCR_Y_INCR_t unDESCR_Y_INCR; /*!< 0x00000078 Channel descriptor Y increment */
|
||||
un_DMAC_CH_DESCR_NEXT_t unDESCR_NEXT; /*!< 0x0000007C Channel descriptor next pointer */
|
||||
un_DMAC_CH_INTR_t unINTR; /*!< 0x00000080 Interrupt */
|
||||
un_DMAC_CH_INTR_SET_t unINTR_SET; /*!< 0x00000084 Interrupt set */
|
||||
un_DMAC_CH_INTR_MASK_t unINTR_MASK; /*!< 0x00000088 Interrupt mask */
|
||||
un_DMAC_CH_INTR_MASKED_t unINTR_MASKED; /*!< 0x0000008C Interrupt masked */
|
||||
uint32_t au32Reserved5[28];
|
||||
} stc_DMAC_CH_t; /*!< Size = 256 (0x100) */
|
||||
|
||||
/**
|
||||
* \brief DMAC (DMAC)
|
||||
*/
|
||||
typedef struct stc_DMAC {
|
||||
un_DMAC_CTL_t unCTL; /*!< 0x00000000 Control */
|
||||
uint32_t u32Reserved;
|
||||
un_DMAC_ACTIVE_t unACTIVE; /*!< 0x00000008 Active channels */
|
||||
uint32_t au32Reserved1[1021];
|
||||
stc_DMAC_CH_t CH[8]; /*!< 0x00001000 DMA controller channel */
|
||||
} stc_DMAC_t; /*!< Size = 6144 (0x1800) */
|
||||
|
||||
|
||||
/* DMAC_CH.CTL */
|
||||
#define DMAC_CH_CTL_P_Pos 0UL
|
||||
#define DMAC_CH_CTL_P_Msk 0x1UL
|
||||
#define DMAC_CH_CTL_NS_Pos 1UL
|
||||
#define DMAC_CH_CTL_NS_Msk 0x2UL
|
||||
#define DMAC_CH_CTL_B_Pos 2UL
|
||||
#define DMAC_CH_CTL_B_Msk 0x4UL
|
||||
#define DMAC_CH_CTL_PC_Pos 4UL
|
||||
#define DMAC_CH_CTL_PC_Msk 0xF0UL
|
||||
#define DMAC_CH_CTL_PRIO_Pos 8UL
|
||||
#define DMAC_CH_CTL_PRIO_Msk 0x300UL
|
||||
#define DMAC_CH_CTL_ENABLED_Pos 31UL
|
||||
#define DMAC_CH_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* DMAC_CH.IDX */
|
||||
#define DMAC_CH_IDX_X_Pos 0UL
|
||||
#define DMAC_CH_IDX_X_Msk 0xFFFFUL
|
||||
#define DMAC_CH_IDX_Y_Pos 16UL
|
||||
#define DMAC_CH_IDX_Y_Msk 0xFFFF0000UL
|
||||
/* DMAC_CH.SRC */
|
||||
#define DMAC_CH_SRC_ADDR_Pos 0UL
|
||||
#define DMAC_CH_SRC_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DMAC_CH.DST */
|
||||
#define DMAC_CH_DST_ADDR_Pos 0UL
|
||||
#define DMAC_CH_DST_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DMAC_CH.CURR */
|
||||
#define DMAC_CH_CURR_PTR_Pos 2UL
|
||||
#define DMAC_CH_CURR_PTR_Msk 0xFFFFFFFCUL
|
||||
/* DMAC_CH.TR_CMD */
|
||||
#define DMAC_CH_TR_CMD_ACTIVATE_Pos 0UL
|
||||
#define DMAC_CH_TR_CMD_ACTIVATE_Msk 0x1UL
|
||||
/* DMAC_CH.DESCR_STATUS */
|
||||
#define DMAC_CH_DESCR_STATUS_VALID_Pos 31UL
|
||||
#define DMAC_CH_DESCR_STATUS_VALID_Msk 0x80000000UL
|
||||
/* DMAC_CH.DESCR_CTL */
|
||||
#define DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL
|
||||
#define DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL
|
||||
#define DMAC_CH_DESCR_CTL_INTR_TYPE_Pos 2UL
|
||||
#define DMAC_CH_DESCR_CTL_INTR_TYPE_Msk 0xCUL
|
||||
#define DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Pos 4UL
|
||||
#define DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL
|
||||
#define DMAC_CH_DESCR_CTL_TR_IN_TYPE_Pos 6UL
|
||||
#define DMAC_CH_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL
|
||||
#define DMAC_CH_DESCR_CTL_DATA_PREFETCH_Pos 8UL
|
||||
#define DMAC_CH_DESCR_CTL_DATA_PREFETCH_Msk 0x100UL
|
||||
#define DMAC_CH_DESCR_CTL_DATA_SIZE_Pos 16UL
|
||||
#define DMAC_CH_DESCR_CTL_DATA_SIZE_Msk 0x30000UL
|
||||
#define DMAC_CH_DESCR_CTL_CH_DISABLE_Pos 24UL
|
||||
#define DMAC_CH_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL
|
||||
#define DMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL
|
||||
#define DMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL
|
||||
#define DMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL
|
||||
#define DMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL
|
||||
#define DMAC_CH_DESCR_CTL_DESCR_TYPE_Pos 28UL
|
||||
#define DMAC_CH_DESCR_CTL_DESCR_TYPE_Msk 0x70000000UL
|
||||
/* DMAC_CH.DESCR_SRC */
|
||||
#define DMAC_CH_DESCR_SRC_ADDR_Pos 0UL
|
||||
#define DMAC_CH_DESCR_SRC_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DMAC_CH.DESCR_DST */
|
||||
#define DMAC_CH_DESCR_DST_ADDR_Pos 0UL
|
||||
#define DMAC_CH_DESCR_DST_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DMAC_CH.DESCR_X_SIZE */
|
||||
#define DMAC_CH_DESCR_X_SIZE_X_COUNT_Pos 0UL
|
||||
#define DMAC_CH_DESCR_X_SIZE_X_COUNT_Msk 0xFFFFUL
|
||||
/* DMAC_CH.DESCR_X_INCR */
|
||||
#define DMAC_CH_DESCR_X_INCR_SRC_X_Pos 0UL
|
||||
#define DMAC_CH_DESCR_X_INCR_SRC_X_Msk 0xFFFFUL
|
||||
#define DMAC_CH_DESCR_X_INCR_DST_X_Pos 16UL
|
||||
#define DMAC_CH_DESCR_X_INCR_DST_X_Msk 0xFFFF0000UL
|
||||
/* DMAC_CH.DESCR_Y_SIZE */
|
||||
#define DMAC_CH_DESCR_Y_SIZE_Y_COUNT_Pos 0UL
|
||||
#define DMAC_CH_DESCR_Y_SIZE_Y_COUNT_Msk 0xFFFFUL
|
||||
/* DMAC_CH.DESCR_Y_INCR */
|
||||
#define DMAC_CH_DESCR_Y_INCR_SRC_Y_Pos 0UL
|
||||
#define DMAC_CH_DESCR_Y_INCR_SRC_Y_Msk 0xFFFFUL
|
||||
#define DMAC_CH_DESCR_Y_INCR_DST_Y_Pos 16UL
|
||||
#define DMAC_CH_DESCR_Y_INCR_DST_Y_Msk 0xFFFF0000UL
|
||||
/* DMAC_CH.DESCR_NEXT */
|
||||
#define DMAC_CH_DESCR_NEXT_PTR_Pos 2UL
|
||||
#define DMAC_CH_DESCR_NEXT_PTR_Msk 0xFFFFFFFCUL
|
||||
/* DMAC_CH.INTR */
|
||||
#define DMAC_CH_INTR_COMPLETION_Pos 0UL
|
||||
#define DMAC_CH_INTR_COMPLETION_Msk 0x1UL
|
||||
#define DMAC_CH_INTR_SRC_BUS_ERROR_Pos 1UL
|
||||
#define DMAC_CH_INTR_SRC_BUS_ERROR_Msk 0x2UL
|
||||
#define DMAC_CH_INTR_DST_BUS_ERROR_Pos 2UL
|
||||
#define DMAC_CH_INTR_DST_BUS_ERROR_Msk 0x4UL
|
||||
#define DMAC_CH_INTR_SRC_MISAL_Pos 3UL
|
||||
#define DMAC_CH_INTR_SRC_MISAL_Msk 0x8UL
|
||||
#define DMAC_CH_INTR_DST_MISAL_Pos 4UL
|
||||
#define DMAC_CH_INTR_DST_MISAL_Msk 0x10UL
|
||||
#define DMAC_CH_INTR_CURR_PTR_NULL_Pos 5UL
|
||||
#define DMAC_CH_INTR_CURR_PTR_NULL_Msk 0x20UL
|
||||
#define DMAC_CH_INTR_ACTIVE_CH_DISABLED_Pos 6UL
|
||||
#define DMAC_CH_INTR_ACTIVE_CH_DISABLED_Msk 0x40UL
|
||||
#define DMAC_CH_INTR_DESCR_BUS_ERROR_Pos 7UL
|
||||
#define DMAC_CH_INTR_DESCR_BUS_ERROR_Msk 0x80UL
|
||||
/* DMAC_CH.INTR_SET */
|
||||
#define DMAC_CH_INTR_SET_COMPLETION_Pos 0UL
|
||||
#define DMAC_CH_INTR_SET_COMPLETION_Msk 0x1UL
|
||||
#define DMAC_CH_INTR_SET_SRC_BUS_ERROR_Pos 1UL
|
||||
#define DMAC_CH_INTR_SET_SRC_BUS_ERROR_Msk 0x2UL
|
||||
#define DMAC_CH_INTR_SET_DST_BUS_ERROR_Pos 2UL
|
||||
#define DMAC_CH_INTR_SET_DST_BUS_ERROR_Msk 0x4UL
|
||||
#define DMAC_CH_INTR_SET_SRC_MISAL_Pos 3UL
|
||||
#define DMAC_CH_INTR_SET_SRC_MISAL_Msk 0x8UL
|
||||
#define DMAC_CH_INTR_SET_DST_MISAL_Pos 4UL
|
||||
#define DMAC_CH_INTR_SET_DST_MISAL_Msk 0x10UL
|
||||
#define DMAC_CH_INTR_SET_CURR_PTR_NULL_Pos 5UL
|
||||
#define DMAC_CH_INTR_SET_CURR_PTR_NULL_Msk 0x20UL
|
||||
#define DMAC_CH_INTR_SET_ACTIVE_CH_DISABLED_Pos 6UL
|
||||
#define DMAC_CH_INTR_SET_ACTIVE_CH_DISABLED_Msk 0x40UL
|
||||
#define DMAC_CH_INTR_SET_DESCR_BUS_ERROR_Pos 7UL
|
||||
#define DMAC_CH_INTR_SET_DESCR_BUS_ERROR_Msk 0x80UL
|
||||
/* DMAC_CH.INTR_MASK */
|
||||
#define DMAC_CH_INTR_MASK_COMPLETION_Pos 0UL
|
||||
#define DMAC_CH_INTR_MASK_COMPLETION_Msk 0x1UL
|
||||
#define DMAC_CH_INTR_MASK_SRC_BUS_ERROR_Pos 1UL
|
||||
#define DMAC_CH_INTR_MASK_SRC_BUS_ERROR_Msk 0x2UL
|
||||
#define DMAC_CH_INTR_MASK_DST_BUS_ERROR_Pos 2UL
|
||||
#define DMAC_CH_INTR_MASK_DST_BUS_ERROR_Msk 0x4UL
|
||||
#define DMAC_CH_INTR_MASK_SRC_MISAL_Pos 3UL
|
||||
#define DMAC_CH_INTR_MASK_SRC_MISAL_Msk 0x8UL
|
||||
#define DMAC_CH_INTR_MASK_DST_MISAL_Pos 4UL
|
||||
#define DMAC_CH_INTR_MASK_DST_MISAL_Msk 0x10UL
|
||||
#define DMAC_CH_INTR_MASK_CURR_PTR_NULL_Pos 5UL
|
||||
#define DMAC_CH_INTR_MASK_CURR_PTR_NULL_Msk 0x20UL
|
||||
#define DMAC_CH_INTR_MASK_ACTIVE_CH_DISABLED_Pos 6UL
|
||||
#define DMAC_CH_INTR_MASK_ACTIVE_CH_DISABLED_Msk 0x40UL
|
||||
#define DMAC_CH_INTR_MASK_DESCR_BUS_ERROR_Pos 7UL
|
||||
#define DMAC_CH_INTR_MASK_DESCR_BUS_ERROR_Msk 0x80UL
|
||||
/* DMAC_CH.INTR_MASKED */
|
||||
#define DMAC_CH_INTR_MASKED_COMPLETION_Pos 0UL
|
||||
#define DMAC_CH_INTR_MASKED_COMPLETION_Msk 0x1UL
|
||||
#define DMAC_CH_INTR_MASKED_SRC_BUS_ERROR_Pos 1UL
|
||||
#define DMAC_CH_INTR_MASKED_SRC_BUS_ERROR_Msk 0x2UL
|
||||
#define DMAC_CH_INTR_MASKED_DST_BUS_ERROR_Pos 2UL
|
||||
#define DMAC_CH_INTR_MASKED_DST_BUS_ERROR_Msk 0x4UL
|
||||
#define DMAC_CH_INTR_MASKED_SRC_MISAL_Pos 3UL
|
||||
#define DMAC_CH_INTR_MASKED_SRC_MISAL_Msk 0x8UL
|
||||
#define DMAC_CH_INTR_MASKED_DST_MISAL_Pos 4UL
|
||||
#define DMAC_CH_INTR_MASKED_DST_MISAL_Msk 0x10UL
|
||||
#define DMAC_CH_INTR_MASKED_CURR_PTR_NULL_Pos 5UL
|
||||
#define DMAC_CH_INTR_MASKED_CURR_PTR_NULL_Msk 0x20UL
|
||||
#define DMAC_CH_INTR_MASKED_ACTIVE_CH_DISABLED_Pos 6UL
|
||||
#define DMAC_CH_INTR_MASKED_ACTIVE_CH_DISABLED_Msk 0x40UL
|
||||
#define DMAC_CH_INTR_MASKED_DESCR_BUS_ERROR_Pos 7UL
|
||||
#define DMAC_CH_INTR_MASKED_DESCR_BUS_ERROR_Msk 0x80UL
|
||||
|
||||
|
||||
/* DMAC.CTL */
|
||||
#define DMAC_CTL_ENABLED_Pos 31UL
|
||||
#define DMAC_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* DMAC.ACTIVE */
|
||||
#define DMAC_ACTIVE_ACTIVE_Pos 0UL
|
||||
#define DMAC_ACTIVE_ACTIVE_Msk 0xFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_DMAC_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,653 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_dw.h
|
||||
*
|
||||
* \brief
|
||||
* DW IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_DW_H_
|
||||
#define _CYIP_DW_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW_CH_STRUCT_SECTION_SIZE 0x00000040UL
|
||||
#define DW_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Channel control (DW_CH_STRUCT_CH_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_CH_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t u1B:1;
|
||||
uint32_t :1;
|
||||
uint32_t u4PC:4;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :1;
|
||||
uint32_t u1PREEMPTABLE:1;
|
||||
uint32_t :19;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_DW_CH_STRUCT_CH_CTL_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_CH_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_CH_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_CH_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Channel status (DW_CH_STRUCT_CH_STATUS)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_CH_STATUS_field {
|
||||
uint32_t u4INTR_CAUSE:4;
|
||||
uint32_t :27;
|
||||
uint32_t u1PENDING:1;
|
||||
} stc_DW_CH_STRUCT_CH_STATUS_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_CH_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_CH_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_CH_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Channel current indices (DW_CH_STRUCT_CH_IDX)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_CH_IDX_field {
|
||||
uint32_t u8X_IDX:8;
|
||||
uint32_t u8Y_IDX:8;
|
||||
uint32_t :16;
|
||||
} stc_DW_CH_STRUCT_CH_IDX_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_CH_IDX {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_CH_IDX_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_CH_IDX_t;
|
||||
|
||||
/**
|
||||
* \brief Channel current descriptor pointer (DW_CH_STRUCT_CH_CURR_PTR)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_CH_CURR_PTR_field {
|
||||
uint32_t :2;
|
||||
uint32_t u30ADDR:30;
|
||||
} stc_DW_CH_STRUCT_CH_CURR_PTR_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_CH_CURR_PTR {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_CH_CURR_PTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_CH_CURR_PTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt (DW_CH_STRUCT_INTR)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_INTR_field {
|
||||
uint32_t u1CH:1;
|
||||
uint32_t :31;
|
||||
} stc_DW_CH_STRUCT_INTR_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt set (DW_CH_STRUCT_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_INTR_SET_field {
|
||||
uint32_t u1CH:1;
|
||||
uint32_t :31;
|
||||
} stc_DW_CH_STRUCT_INTR_SET_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt mask (DW_CH_STRUCT_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_INTR_MASK_field {
|
||||
uint32_t u1CH:1;
|
||||
uint32_t :31;
|
||||
} stc_DW_CH_STRUCT_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt masked (DW_CH_STRUCT_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_INTR_MASKED_field {
|
||||
uint32_t u1CH:1;
|
||||
uint32_t :31;
|
||||
} stc_DW_CH_STRUCT_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_INTR_MASKED_t;
|
||||
|
||||
/**
|
||||
* \brief SRAM data 0 (DW_CH_STRUCT_SRAM_DATA0)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_SRAM_DATA0_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_DW_CH_STRUCT_SRAM_DATA0_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_SRAM_DATA0 {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_SRAM_DATA0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_SRAM_DATA0_t;
|
||||
|
||||
/**
|
||||
* \brief SRAM data 1 (DW_CH_STRUCT_SRAM_DATA1)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_SRAM_DATA1_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_DW_CH_STRUCT_SRAM_DATA1_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_SRAM_DATA1 {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_SRAM_DATA1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_SRAM_DATA1_t;
|
||||
|
||||
/**
|
||||
* \brief Channel software trigger (DW_CH_STRUCT_TR_CMD)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT_TR_CMD_field {
|
||||
uint32_t u1ACTIVATE:1;
|
||||
uint32_t :31;
|
||||
} stc_DW_CH_STRUCT_TR_CMD_field_t;
|
||||
|
||||
typedef union un_DW_CH_STRUCT_TR_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CH_STRUCT_TR_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CH_STRUCT_TR_CMD_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Control (DW_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_CTL_field {
|
||||
uint32_t u1ECC_EN:1;
|
||||
uint32_t u1ECC_INJ_EN:1;
|
||||
uint32_t :29;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_DW_CTL_field_t;
|
||||
|
||||
typedef union un_DW_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Status (DW_STATUS)
|
||||
*/
|
||||
typedef struct stc_DW_STATUS_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t u1B:1;
|
||||
uint32_t :1;
|
||||
uint32_t u4PC:4;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :1;
|
||||
uint32_t u1PREEMPTABLE:1;
|
||||
uint32_t :4;
|
||||
uint32_t u9CH_IDX:9;
|
||||
uint32_t :3;
|
||||
uint32_t u3STATE:3;
|
||||
uint32_t u1ACTIVE:1;
|
||||
} stc_DW_STATUS_field_t;
|
||||
|
||||
typedef union un_DW_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_DW_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Active descriptor control (DW_ACT_DESCR_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_ACT_DESCR_CTL_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_DW_ACT_DESCR_CTL_field_t;
|
||||
|
||||
typedef union un_DW_ACT_DESCR_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_ACT_DESCR_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_ACT_DESCR_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Active descriptor source (DW_ACT_DESCR_SRC)
|
||||
*/
|
||||
typedef struct stc_DW_ACT_DESCR_SRC_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_DW_ACT_DESCR_SRC_field_t;
|
||||
|
||||
typedef union un_DW_ACT_DESCR_SRC {
|
||||
uint32_t u32Register;
|
||||
stc_DW_ACT_DESCR_SRC_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_ACT_DESCR_SRC_t;
|
||||
|
||||
/**
|
||||
* \brief Active descriptor destination (DW_ACT_DESCR_DST)
|
||||
*/
|
||||
typedef struct stc_DW_ACT_DESCR_DST_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_DW_ACT_DESCR_DST_field_t;
|
||||
|
||||
typedef union un_DW_ACT_DESCR_DST {
|
||||
uint32_t u32Register;
|
||||
stc_DW_ACT_DESCR_DST_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_ACT_DESCR_DST_t;
|
||||
|
||||
/**
|
||||
* \brief Active descriptor X loop control (DW_ACT_DESCR_X_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_ACT_DESCR_X_CTL_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_DW_ACT_DESCR_X_CTL_field_t;
|
||||
|
||||
typedef union un_DW_ACT_DESCR_X_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_ACT_DESCR_X_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_ACT_DESCR_X_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Active descriptor Y loop control (DW_ACT_DESCR_Y_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_ACT_DESCR_Y_CTL_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_DW_ACT_DESCR_Y_CTL_field_t;
|
||||
|
||||
typedef union un_DW_ACT_DESCR_Y_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_ACT_DESCR_Y_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_ACT_DESCR_Y_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Active descriptor next pointer (DW_ACT_DESCR_NEXT_PTR)
|
||||
*/
|
||||
typedef struct stc_DW_ACT_DESCR_NEXT_PTR_field {
|
||||
uint32_t :2;
|
||||
uint32_t u30ADDR:30;
|
||||
} stc_DW_ACT_DESCR_NEXT_PTR_field_t;
|
||||
|
||||
typedef union un_DW_ACT_DESCR_NEXT_PTR {
|
||||
uint32_t u32Register;
|
||||
stc_DW_ACT_DESCR_NEXT_PTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_ACT_DESCR_NEXT_PTR_t;
|
||||
|
||||
/**
|
||||
* \brief Active source (DW_ACT_SRC)
|
||||
*/
|
||||
typedef struct stc_DW_ACT_SRC_field {
|
||||
uint32_t u32SRC_ADDR:32;
|
||||
} stc_DW_ACT_SRC_field_t;
|
||||
|
||||
typedef union un_DW_ACT_SRC {
|
||||
uint32_t u32Register;
|
||||
stc_DW_ACT_SRC_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_ACT_SRC_t;
|
||||
|
||||
/**
|
||||
* \brief Active destination (DW_ACT_DST)
|
||||
*/
|
||||
typedef struct stc_DW_ACT_DST_field {
|
||||
uint32_t u32DST_ADDR:32;
|
||||
} stc_DW_ACT_DST_field_t;
|
||||
|
||||
typedef union un_DW_ACT_DST {
|
||||
uint32_t u32Register;
|
||||
stc_DW_ACT_DST_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_ACT_DST_t;
|
||||
|
||||
/**
|
||||
* \brief ECC control (DW_ECC_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_ECC_CTL_field {
|
||||
uint32_t u10WORD_ADDR:10;
|
||||
uint32_t :15;
|
||||
uint32_t u7PARITY:7;
|
||||
} stc_DW_ECC_CTL_field_t;
|
||||
|
||||
typedef union un_DW_ECC_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_ECC_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_ECC_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief CRC control (DW_CRC_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_CRC_CTL_field {
|
||||
uint32_t u1DATA_REVERSE:1;
|
||||
uint32_t :7;
|
||||
uint32_t u1REM_REVERSE:1;
|
||||
uint32_t :23;
|
||||
} stc_DW_CRC_CTL_field_t;
|
||||
|
||||
typedef union un_DW_CRC_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CRC_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CRC_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief CRC data control (DW_CRC_DATA_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_CRC_DATA_CTL_field {
|
||||
uint32_t u8DATA_XOR:8;
|
||||
uint32_t :24;
|
||||
} stc_DW_CRC_DATA_CTL_field_t;
|
||||
|
||||
typedef union un_DW_CRC_DATA_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CRC_DATA_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CRC_DATA_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief CRC polynomial control (DW_CRC_POL_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_CRC_POL_CTL_field {
|
||||
uint32_t u32POLYNOMIAL:32;
|
||||
} stc_DW_CRC_POL_CTL_field_t;
|
||||
|
||||
typedef union un_DW_CRC_POL_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CRC_POL_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CRC_POL_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief CRC LFSR control (DW_CRC_LFSR_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_CRC_LFSR_CTL_field {
|
||||
uint32_t u32LFSR32:32;
|
||||
} stc_DW_CRC_LFSR_CTL_field_t;
|
||||
|
||||
typedef union un_DW_CRC_LFSR_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CRC_LFSR_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CRC_LFSR_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief CRC remainder control (DW_CRC_REM_CTL)
|
||||
*/
|
||||
typedef struct stc_DW_CRC_REM_CTL_field {
|
||||
uint32_t u32REM_XOR:32;
|
||||
} stc_DW_CRC_REM_CTL_field_t;
|
||||
|
||||
typedef union un_DW_CRC_REM_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CRC_REM_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CRC_REM_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief CRC remainder result (DW_CRC_REM_RESULT)
|
||||
*/
|
||||
typedef struct stc_DW_CRC_REM_RESULT_field {
|
||||
uint32_t u32REM:32;
|
||||
} stc_DW_CRC_REM_RESULT_field_t;
|
||||
|
||||
typedef union un_DW_CRC_REM_RESULT {
|
||||
uint32_t u32Register;
|
||||
stc_DW_CRC_REM_RESULT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_DW_CRC_REM_RESULT_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief DW channel structure (DW_CH_STRUCT)
|
||||
*/
|
||||
typedef struct stc_DW_CH_STRUCT {
|
||||
un_DW_CH_STRUCT_CH_CTL_t unCH_CTL; /*!< 0x00000000 Channel control */
|
||||
un_DW_CH_STRUCT_CH_STATUS_t unCH_STATUS; /*!< 0x00000004 Channel status */
|
||||
un_DW_CH_STRUCT_CH_IDX_t unCH_IDX; /*!< 0x00000008 Channel current indices */
|
||||
un_DW_CH_STRUCT_CH_CURR_PTR_t unCH_CURR_PTR; /*!< 0x0000000C Channel current descriptor pointer */
|
||||
un_DW_CH_STRUCT_INTR_t unINTR; /*!< 0x00000010 Interrupt */
|
||||
un_DW_CH_STRUCT_INTR_SET_t unINTR_SET; /*!< 0x00000014 Interrupt set */
|
||||
un_DW_CH_STRUCT_INTR_MASK_t unINTR_MASK; /*!< 0x00000018 Interrupt mask */
|
||||
un_DW_CH_STRUCT_INTR_MASKED_t unINTR_MASKED; /*!< 0x0000001C Interrupt masked */
|
||||
un_DW_CH_STRUCT_SRAM_DATA0_t unSRAM_DATA0; /*!< 0x00000020 SRAM data 0 */
|
||||
un_DW_CH_STRUCT_SRAM_DATA1_t unSRAM_DATA1; /*!< 0x00000024 SRAM data 1 */
|
||||
un_DW_CH_STRUCT_TR_CMD_t unTR_CMD; /*!< 0x00000028 Channel software trigger */
|
||||
uint32_t au32Reserved[5];
|
||||
} stc_DW_CH_STRUCT_t; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief Datawire Controller (DW)
|
||||
*/
|
||||
typedef struct stc_DW {
|
||||
un_DW_CTL_t unCTL; /*!< 0x00000000 Control */
|
||||
un_DW_STATUS_t unSTATUS; /*!< 0x00000004 Status */
|
||||
uint32_t au32Reserved[6];
|
||||
un_DW_ACT_DESCR_CTL_t unACT_DESCR_CTL; /*!< 0x00000020 Active descriptor control */
|
||||
un_DW_ACT_DESCR_SRC_t unACT_DESCR_SRC; /*!< 0x00000024 Active descriptor source */
|
||||
un_DW_ACT_DESCR_DST_t unACT_DESCR_DST; /*!< 0x00000028 Active descriptor destination */
|
||||
uint32_t u32Reserved1;
|
||||
un_DW_ACT_DESCR_X_CTL_t unACT_DESCR_X_CTL; /*!< 0x00000030 Active descriptor X loop control */
|
||||
un_DW_ACT_DESCR_Y_CTL_t unACT_DESCR_Y_CTL; /*!< 0x00000034 Active descriptor Y loop control */
|
||||
un_DW_ACT_DESCR_NEXT_PTR_t unACT_DESCR_NEXT_PTR; /*!< 0x00000038 Active descriptor next pointer */
|
||||
uint32_t u32Reserved2;
|
||||
un_DW_ACT_SRC_t unACT_SRC; /*!< 0x00000040 Active source */
|
||||
un_DW_ACT_DST_t unACT_DST; /*!< 0x00000044 Active destination */
|
||||
uint32_t au32Reserved3[14];
|
||||
un_DW_ECC_CTL_t unECC_CTL; /*!< 0x00000080 ECC control */
|
||||
uint32_t au32Reserved4[31];
|
||||
un_DW_CRC_CTL_t unCRC_CTL; /*!< 0x00000100 CRC control */
|
||||
uint32_t au32Reserved5[3];
|
||||
un_DW_CRC_DATA_CTL_t unCRC_DATA_CTL; /*!< 0x00000110 CRC data control */
|
||||
uint32_t au32Reserved6[3];
|
||||
un_DW_CRC_POL_CTL_t unCRC_POL_CTL; /*!< 0x00000120 CRC polynomial control */
|
||||
uint32_t au32Reserved7[3];
|
||||
un_DW_CRC_LFSR_CTL_t unCRC_LFSR_CTL; /*!< 0x00000130 CRC LFSR control */
|
||||
uint32_t au32Reserved8[3];
|
||||
un_DW_CRC_REM_CTL_t unCRC_REM_CTL; /*!< 0x00000140 CRC remainder control */
|
||||
uint32_t u32Reserved9;
|
||||
un_DW_CRC_REM_RESULT_t unCRC_REM_RESULT; /*!< 0x00000148 CRC remainder result */
|
||||
uint32_t au32Reserved10[8109];
|
||||
stc_DW_CH_STRUCT_t CH_STRUCT[512]; /*!< 0x00008000 DW channel structure */
|
||||
} stc_DW_t; /*!< Size = 65536 (0x10000) */
|
||||
|
||||
|
||||
/* DW_CH_STRUCT.CH_CTL */
|
||||
#define DW_CH_STRUCT_CH_CTL_P_Pos 0UL
|
||||
#define DW_CH_STRUCT_CH_CTL_P_Msk 0x1UL
|
||||
#define DW_CH_STRUCT_CH_CTL_NS_Pos 1UL
|
||||
#define DW_CH_STRUCT_CH_CTL_NS_Msk 0x2UL
|
||||
#define DW_CH_STRUCT_CH_CTL_B_Pos 2UL
|
||||
#define DW_CH_STRUCT_CH_CTL_B_Msk 0x4UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PC_Pos 4UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PC_Msk 0xF0UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PRIO_Pos 8UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PRIO_Msk 0x300UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos 11UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk 0x800UL
|
||||
#define DW_CH_STRUCT_CH_CTL_ENABLED_Pos 31UL
|
||||
#define DW_CH_STRUCT_CH_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* DW_CH_STRUCT.CH_STATUS */
|
||||
#define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Pos 0UL
|
||||
#define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Msk 0xFUL
|
||||
#define DW_CH_STRUCT_CH_STATUS_PENDING_Pos 31UL
|
||||
#define DW_CH_STRUCT_CH_STATUS_PENDING_Msk 0x80000000UL
|
||||
/* DW_CH_STRUCT.CH_IDX */
|
||||
#define DW_CH_STRUCT_CH_IDX_X_IDX_Pos 0UL
|
||||
#define DW_CH_STRUCT_CH_IDX_X_IDX_Msk 0xFFUL
|
||||
#define DW_CH_STRUCT_CH_IDX_Y_IDX_Pos 8UL
|
||||
#define DW_CH_STRUCT_CH_IDX_Y_IDX_Msk 0xFF00UL
|
||||
/* DW_CH_STRUCT.CH_CURR_PTR */
|
||||
#define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Pos 2UL
|
||||
#define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Msk 0xFFFFFFFCUL
|
||||
/* DW_CH_STRUCT.INTR */
|
||||
#define DW_CH_STRUCT_INTR_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_INTR_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.INTR_SET */
|
||||
#define DW_CH_STRUCT_INTR_SET_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_INTR_SET_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.INTR_MASK */
|
||||
#define DW_CH_STRUCT_INTR_MASK_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_INTR_MASK_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.INTR_MASKED */
|
||||
#define DW_CH_STRUCT_INTR_MASKED_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_INTR_MASKED_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.SRAM_DATA0 */
|
||||
#define DW_CH_STRUCT_SRAM_DATA0_DATA_Pos 0UL
|
||||
#define DW_CH_STRUCT_SRAM_DATA0_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW_CH_STRUCT.SRAM_DATA1 */
|
||||
#define DW_CH_STRUCT_SRAM_DATA1_DATA_Pos 0UL
|
||||
#define DW_CH_STRUCT_SRAM_DATA1_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW_CH_STRUCT.TR_CMD */
|
||||
#define DW_CH_STRUCT_TR_CMD_ACTIVATE_Pos 0UL
|
||||
#define DW_CH_STRUCT_TR_CMD_ACTIVATE_Msk 0x1UL
|
||||
|
||||
|
||||
/* DW.CTL */
|
||||
#define DW_CTL_ECC_EN_Pos 0UL
|
||||
#define DW_CTL_ECC_EN_Msk 0x1UL
|
||||
#define DW_CTL_ECC_INJ_EN_Pos 1UL
|
||||
#define DW_CTL_ECC_INJ_EN_Msk 0x2UL
|
||||
#define DW_CTL_ENABLED_Pos 31UL
|
||||
#define DW_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* DW.STATUS */
|
||||
#define DW_STATUS_P_Pos 0UL
|
||||
#define DW_STATUS_P_Msk 0x1UL
|
||||
#define DW_STATUS_NS_Pos 1UL
|
||||
#define DW_STATUS_NS_Msk 0x2UL
|
||||
#define DW_STATUS_B_Pos 2UL
|
||||
#define DW_STATUS_B_Msk 0x4UL
|
||||
#define DW_STATUS_PC_Pos 4UL
|
||||
#define DW_STATUS_PC_Msk 0xF0UL
|
||||
#define DW_STATUS_PRIO_Pos 8UL
|
||||
#define DW_STATUS_PRIO_Msk 0x300UL
|
||||
#define DW_STATUS_PREEMPTABLE_Pos 11UL
|
||||
#define DW_STATUS_PREEMPTABLE_Msk 0x800UL
|
||||
#define DW_STATUS_CH_IDX_Pos 16UL
|
||||
#define DW_STATUS_CH_IDX_Msk 0x1FF0000UL
|
||||
#define DW_STATUS_STATE_Pos 28UL
|
||||
#define DW_STATUS_STATE_Msk 0x70000000UL
|
||||
#define DW_STATUS_ACTIVE_Pos 31UL
|
||||
#define DW_STATUS_ACTIVE_Msk 0x80000000UL
|
||||
/* DW.ACT_DESCR_CTL */
|
||||
#define DW_ACT_DESCR_CTL_DATA_Pos 0UL
|
||||
#define DW_ACT_DESCR_CTL_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_SRC */
|
||||
#define DW_ACT_DESCR_SRC_DATA_Pos 0UL
|
||||
#define DW_ACT_DESCR_SRC_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_DST */
|
||||
#define DW_ACT_DESCR_DST_DATA_Pos 0UL
|
||||
#define DW_ACT_DESCR_DST_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_X_CTL */
|
||||
#define DW_ACT_DESCR_X_CTL_DATA_Pos 0UL
|
||||
#define DW_ACT_DESCR_X_CTL_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_Y_CTL */
|
||||
#define DW_ACT_DESCR_Y_CTL_DATA_Pos 0UL
|
||||
#define DW_ACT_DESCR_Y_CTL_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_NEXT_PTR */
|
||||
#define DW_ACT_DESCR_NEXT_PTR_ADDR_Pos 2UL
|
||||
#define DW_ACT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL
|
||||
/* DW.ACT_SRC */
|
||||
#define DW_ACT_SRC_SRC_ADDR_Pos 0UL
|
||||
#define DW_ACT_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DST */
|
||||
#define DW_ACT_DST_DST_ADDR_Pos 0UL
|
||||
#define DW_ACT_DST_DST_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DW.ECC_CTL */
|
||||
#define DW_ECC_CTL_WORD_ADDR_Pos 0UL
|
||||
#define DW_ECC_CTL_WORD_ADDR_Msk 0x3FFUL
|
||||
#define DW_ECC_CTL_PARITY_Pos 25UL
|
||||
#define DW_ECC_CTL_PARITY_Msk 0xFE000000UL
|
||||
/* DW.CRC_CTL */
|
||||
#define DW_CRC_CTL_DATA_REVERSE_Pos 0UL
|
||||
#define DW_CRC_CTL_DATA_REVERSE_Msk 0x1UL
|
||||
#define DW_CRC_CTL_REM_REVERSE_Pos 8UL
|
||||
#define DW_CRC_CTL_REM_REVERSE_Msk 0x100UL
|
||||
/* DW.CRC_DATA_CTL */
|
||||
#define DW_CRC_DATA_CTL_DATA_XOR_Pos 0UL
|
||||
#define DW_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL
|
||||
/* DW.CRC_POL_CTL */
|
||||
#define DW_CRC_POL_CTL_POLYNOMIAL_Pos 0UL
|
||||
#define DW_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL
|
||||
/* DW.CRC_LFSR_CTL */
|
||||
#define DW_CRC_LFSR_CTL_LFSR32_Pos 0UL
|
||||
#define DW_CRC_LFSR_CTL_LFSR32_Msk 0xFFFFFFFFUL
|
||||
/* DW.CRC_REM_CTL */
|
||||
#define DW_CRC_REM_CTL_REM_XOR_Pos 0UL
|
||||
#define DW_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL
|
||||
/* DW.CRC_REM_RESULT */
|
||||
#define DW_CRC_REM_RESULT_REM_Pos 0UL
|
||||
#define DW_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_DW_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,116 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_efuse_data_v2.h
|
||||
*
|
||||
* \brief
|
||||
* EFUSE_DATA IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_EFUSE_DATA_V2_H_
|
||||
#define _CYIP_EFUSE_DATA_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/**
|
||||
* \brief Secure HASH word 0 (SECURE_HASH_WORD0)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t HASH_WORD0[32];
|
||||
} cy_stc_secure_hash_word0_t;
|
||||
|
||||
/**
|
||||
* \brief Secure HASH word 1 (SECURE_HASH_WORD1)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t HASH_WORD1[32];
|
||||
} cy_stc_secure_hash_word1_t;
|
||||
|
||||
/**
|
||||
* \brief Secure HASH word 2 (SECURE_HASH_WORD2)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t HASH_WORD2[32];
|
||||
} cy_stc_secure_hash_word2_t;
|
||||
|
||||
/**
|
||||
* \brief Secure HASH word 3 (SECURE_HASH_WORD3)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t HASH_WORD3[32];
|
||||
} cy_stc_secure_hash_word3_t;
|
||||
|
||||
/**
|
||||
* \brief Secure access restrictions (SECURE_ACCESS_RESTRICT)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t AP_CTL_CM0_DISABLE[2];
|
||||
uint8_t AP_CTL_CMX_DISABLE[2];
|
||||
uint8_t AP_CTL_SYS_DISABLE[2];
|
||||
uint8_t SYS_AP_MPU_ENABLE;
|
||||
uint8_t DIRECT_EXECUTE_DISABLE;
|
||||
uint8_t FLASH_ALLOWED[3];
|
||||
uint8_t SRAM_ALLOWED[3];
|
||||
uint8_t WORK_FLASH_ALLOWED[2];
|
||||
uint8_t SFLASH_ALLOWED[2];
|
||||
uint8_t MMIO_ALLOWED[2];
|
||||
uint8_t SMIF_XIP_ENABLE;
|
||||
uint8_t RESEREVED[11];
|
||||
} cy_stc_secure_access_restrict_t;
|
||||
|
||||
/**
|
||||
* \brief Dead access restriction in SECURE lifecycle and number of zeros for Secure fuse group (SECURE_DEAD_ACCESS_RESTRICT_ZEROS)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t AP_CTL_CM0_DISABLE[2];
|
||||
uint8_t AP_CTL_CMX_DISABLE[2];
|
||||
uint8_t AP_CTL_SYS_DISABLE[2];
|
||||
uint8_t SYS_AP_MPU_ENABLE;
|
||||
uint8_t DIRECT_EXECUTE_DISABLE;
|
||||
uint8_t FLASH_ALLOWED[3];
|
||||
uint8_t SRAM_ALLOWED[3];
|
||||
uint8_t WORK_FLASH_ALLOWED[2];
|
||||
uint8_t SFLASH_ALLOWED[2];
|
||||
uint8_t MMIO_ALLOWED[2];
|
||||
uint8_t SMIF_XIP_ENABLE;
|
||||
uint8_t RESERVED[3];
|
||||
uint8_t SECURE_GROUP_ZEROS[8];
|
||||
} cy_stc_secure_dead_access_restrict_zeros_t;
|
||||
|
||||
/**
|
||||
* \brief Customer Data (CUSTOMER_DATA)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t DATA_BYTE[32];
|
||||
} cy_stc_customer_data_t;
|
||||
|
||||
|
||||
/**
|
||||
* \brief eFUSE memory (EFUSE_DATA)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t RESERVED[352];
|
||||
cy_stc_secure_hash_word0_t SECURE_HASH_WORD0;
|
||||
cy_stc_secure_hash_word1_t SECURE_HASH_WORD1;
|
||||
cy_stc_secure_hash_word2_t SECURE_HASH_WORD2;
|
||||
cy_stc_secure_hash_word3_t SECURE_HASH_WORD3;
|
||||
cy_stc_secure_access_restrict_t SECURE_ACCESS_RESTRICT;
|
||||
cy_stc_secure_dead_access_restrict_zeros_t SECURE_DEAD_ACCESS_RESTRICT_ZEROS;
|
||||
uint8_t RESERVED1[288];
|
||||
cy_stc_customer_data_t CUSTOMER_DATA[6];
|
||||
} cy_stc_efuse_data_t;
|
||||
|
||||
|
||||
#endif /* _CYIP_EFUSE_DATA_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,686 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_efuse_v2.h
|
||||
*
|
||||
* \brief
|
||||
* EFUSE IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_EFUSE_V2_H_
|
||||
#define _CYIP_EFUSE_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_SECTION_SIZE 0x00000200UL
|
||||
|
||||
/**
|
||||
* \brief Control (EFUSE_CTL)
|
||||
*/
|
||||
typedef struct stc_EFUSE_CTL_field {
|
||||
uint32_t :31;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_EFUSE_CTL_field_t;
|
||||
|
||||
typedef union un_EFUSE_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Test (EFUSE_TEST)
|
||||
*/
|
||||
typedef struct stc_EFUSE_TEST_field {
|
||||
uint32_t u2MARG_READ:2;
|
||||
uint32_t :30;
|
||||
} stc_EFUSE_TEST_field_t;
|
||||
|
||||
typedef union un_EFUSE_TEST {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_TEST_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_TEST_t;
|
||||
|
||||
/**
|
||||
* \brief Command (EFUSE_CMD)
|
||||
*/
|
||||
typedef struct stc_EFUSE_CMD_field {
|
||||
uint32_t u1BIT_DATA:1;
|
||||
uint32_t :3;
|
||||
uint32_t u3BIT_ADDR:3;
|
||||
uint32_t :1;
|
||||
uint32_t u5BYTE_ADDR:5;
|
||||
uint32_t :3;
|
||||
uint32_t u4MACRO_ADDR:4;
|
||||
uint32_t :11;
|
||||
uint32_t u1START:1;
|
||||
} stc_EFUSE_CMD_field_t;
|
||||
|
||||
typedef union un_EFUSE_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_CMD_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer Default value (EFUSE_SEQ_DEFAULT)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_DEFAULT_field {
|
||||
uint32_t :16;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :9;
|
||||
} stc_EFUSE_SEQ_DEFAULT_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_DEFAULT {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_DEFAULT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_DEFAULT_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer read control 0 (EFUSE_SEQ_READ_CTL_0)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_READ_CTL_0_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_READ_CTL_0_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_READ_CTL_0 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_READ_CTL_0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_READ_CTL_0_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer read control 1 (EFUSE_SEQ_READ_CTL_1)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_READ_CTL_1_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_READ_CTL_1_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_READ_CTL_1 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_READ_CTL_1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_READ_CTL_1_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer read control 2 (EFUSE_SEQ_READ_CTL_2)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_READ_CTL_2_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_READ_CTL_2_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_READ_CTL_2 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_READ_CTL_2_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_READ_CTL_2_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer read control 3 (EFUSE_SEQ_READ_CTL_3)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_READ_CTL_3_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_READ_CTL_3_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_READ_CTL_3 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_READ_CTL_3_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_READ_CTL_3_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer read control 4 (EFUSE_SEQ_READ_CTL_4)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_READ_CTL_4_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_READ_CTL_4_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_READ_CTL_4 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_READ_CTL_4_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_READ_CTL_4_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer read control 5 (EFUSE_SEQ_READ_CTL_5)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_READ_CTL_5_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_READ_CTL_5_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_READ_CTL_5 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_READ_CTL_5_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_READ_CTL_5_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer program control 0 (EFUSE_SEQ_PROGRAM_CTL_0)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_PROGRAM_CTL_0_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_PROGRAM_CTL_0_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_PROGRAM_CTL_0 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_PROGRAM_CTL_0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_PROGRAM_CTL_0_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer program control 1 (EFUSE_SEQ_PROGRAM_CTL_1)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_PROGRAM_CTL_1_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_PROGRAM_CTL_1_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_PROGRAM_CTL_1 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_PROGRAM_CTL_1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_PROGRAM_CTL_1_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer program control 2 (EFUSE_SEQ_PROGRAM_CTL_2)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_PROGRAM_CTL_2_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_PROGRAM_CTL_2_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_PROGRAM_CTL_2 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_PROGRAM_CTL_2_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_PROGRAM_CTL_2_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer program control 3 (EFUSE_SEQ_PROGRAM_CTL_3)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_PROGRAM_CTL_3_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_PROGRAM_CTL_3_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_PROGRAM_CTL_3 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_PROGRAM_CTL_3_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_PROGRAM_CTL_3_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer program control 4 (EFUSE_SEQ_PROGRAM_CTL_4)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_PROGRAM_CTL_4_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_PROGRAM_CTL_4_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_PROGRAM_CTL_4 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_PROGRAM_CTL_4_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_PROGRAM_CTL_4_t;
|
||||
|
||||
/**
|
||||
* \brief Sequencer program control 5 (EFUSE_SEQ_PROGRAM_CTL_5)
|
||||
*/
|
||||
typedef struct stc_EFUSE_SEQ_PROGRAM_CTL_5_field {
|
||||
uint32_t u10CYCLES:10;
|
||||
uint32_t :6;
|
||||
uint32_t u1STROBE_A:1;
|
||||
uint32_t u1STROBE_B:1;
|
||||
uint32_t u1STROBE_C:1;
|
||||
uint32_t u1STROBE_D:1;
|
||||
uint32_t u1STROBE_E:1;
|
||||
uint32_t u1STROBE_F:1;
|
||||
uint32_t u1STROBE_G:1;
|
||||
uint32_t :8;
|
||||
uint32_t u1DONE:1;
|
||||
} stc_EFUSE_SEQ_PROGRAM_CTL_5_field_t;
|
||||
|
||||
typedef union un_EFUSE_SEQ_PROGRAM_CTL_5 {
|
||||
uint32_t u32Register;
|
||||
stc_EFUSE_SEQ_PROGRAM_CTL_5_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EFUSE_SEQ_PROGRAM_CTL_5_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief EFUSE MXS40 registers (EFUSE)
|
||||
*/
|
||||
typedef struct stc_EFUSE {
|
||||
un_EFUSE_CTL_t unCTL; /*!< 0x00000000 Control */
|
||||
un_EFUSE_TEST_t unTEST; /*!< 0x00000004 Test */
|
||||
uint32_t au32Reserved[2];
|
||||
un_EFUSE_CMD_t unCMD; /*!< 0x00000010 Command */
|
||||
uint32_t au32Reserved1[3];
|
||||
un_EFUSE_SEQ_DEFAULT_t unSEQ_DEFAULT; /*!< 0x00000020 Sequencer Default value */
|
||||
uint32_t au32Reserved2[7];
|
||||
un_EFUSE_SEQ_READ_CTL_0_t unSEQ_READ_CTL_0; /*!< 0x00000040 Sequencer read control 0 */
|
||||
un_EFUSE_SEQ_READ_CTL_1_t unSEQ_READ_CTL_1; /*!< 0x00000044 Sequencer read control 1 */
|
||||
un_EFUSE_SEQ_READ_CTL_2_t unSEQ_READ_CTL_2; /*!< 0x00000048 Sequencer read control 2 */
|
||||
un_EFUSE_SEQ_READ_CTL_3_t unSEQ_READ_CTL_3; /*!< 0x0000004C Sequencer read control 3 */
|
||||
un_EFUSE_SEQ_READ_CTL_4_t unSEQ_READ_CTL_4; /*!< 0x00000050 Sequencer read control 4 */
|
||||
un_EFUSE_SEQ_READ_CTL_5_t unSEQ_READ_CTL_5; /*!< 0x00000054 Sequencer read control 5 */
|
||||
uint32_t au32Reserved3[2];
|
||||
un_EFUSE_SEQ_PROGRAM_CTL_0_t unSEQ_PROGRAM_CTL_0; /*!< 0x00000060 Sequencer program control 0 */
|
||||
un_EFUSE_SEQ_PROGRAM_CTL_1_t unSEQ_PROGRAM_CTL_1; /*!< 0x00000064 Sequencer program control 1 */
|
||||
un_EFUSE_SEQ_PROGRAM_CTL_2_t unSEQ_PROGRAM_CTL_2; /*!< 0x00000068 Sequencer program control 2 */
|
||||
un_EFUSE_SEQ_PROGRAM_CTL_3_t unSEQ_PROGRAM_CTL_3; /*!< 0x0000006C Sequencer program control 3 */
|
||||
un_EFUSE_SEQ_PROGRAM_CTL_4_t unSEQ_PROGRAM_CTL_4; /*!< 0x00000070 Sequencer program control 4 */
|
||||
un_EFUSE_SEQ_PROGRAM_CTL_5_t unSEQ_PROGRAM_CTL_5; /*!< 0x00000074 Sequencer program control 5 */
|
||||
} stc_EFUSE_t; /*!< Size = 120 (0x78) */
|
||||
|
||||
|
||||
/* EFUSE.CTL */
|
||||
#define EFUSE_CTL_ENABLED_Pos 31UL
|
||||
#define EFUSE_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* EFUSE.TEST */
|
||||
#define EFUSE_TEST_MARG_READ_Pos 0UL
|
||||
#define EFUSE_TEST_MARG_READ_Msk 0x3UL
|
||||
/* EFUSE.CMD */
|
||||
#define EFUSE_CMD_BIT_DATA_Pos 0UL
|
||||
#define EFUSE_CMD_BIT_DATA_Msk 0x1UL
|
||||
#define EFUSE_CMD_BIT_ADDR_Pos 4UL
|
||||
#define EFUSE_CMD_BIT_ADDR_Msk 0x70UL
|
||||
#define EFUSE_CMD_BYTE_ADDR_Pos 8UL
|
||||
#define EFUSE_CMD_BYTE_ADDR_Msk 0x1F00UL
|
||||
#define EFUSE_CMD_MACRO_ADDR_Pos 16UL
|
||||
#define EFUSE_CMD_MACRO_ADDR_Msk 0xF0000UL
|
||||
#define EFUSE_CMD_START_Pos 31UL
|
||||
#define EFUSE_CMD_START_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_DEFAULT */
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_G_Msk 0x400000UL
|
||||
/* EFUSE.SEQ_READ_CTL_0 */
|
||||
#define EFUSE_SEQ_READ_CTL_0_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_READ_CTL_1 */
|
||||
#define EFUSE_SEQ_READ_CTL_1_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_READ_CTL_2 */
|
||||
#define EFUSE_SEQ_READ_CTL_2_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_READ_CTL_3 */
|
||||
#define EFUSE_SEQ_READ_CTL_3_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_READ_CTL_4 */
|
||||
#define EFUSE_SEQ_READ_CTL_4_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_READ_CTL_5 */
|
||||
#define EFUSE_SEQ_READ_CTL_5_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_0 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_1 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_2 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_3 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_4 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_5 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_DONE_Msk 0x80000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_EFUSE_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,440 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_evtgen.h
|
||||
*
|
||||
* \brief
|
||||
* EVTGEN IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_EVTGEN_H_
|
||||
#define _CYIP_EVTGEN_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* EVTGEN
|
||||
*******************************************************************************/
|
||||
|
||||
#define EVTGEN_COMP_STRUCT_SECTION_SIZE 0x00000020UL
|
||||
#define EVTGEN_SECTION_SIZE 0x00001000UL
|
||||
|
||||
/**
|
||||
* \brief Comparator control (EVTGEN_COMP_STRUCT_COMP_CTL)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_COMP_STRUCT_COMP_CTL_field {
|
||||
uint32_t u1COMP0_EN:1;
|
||||
uint32_t u1COMP1_EN:1;
|
||||
uint32_t :14;
|
||||
uint32_t u1TR_OUT_EDGE:1;
|
||||
uint32_t :14;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_EVTGEN_COMP_STRUCT_COMP_CTL_field_t;
|
||||
|
||||
typedef union un_EVTGEN_COMP_STRUCT_COMP_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_COMP_STRUCT_COMP_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_COMP_STRUCT_COMP_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Comparator 0 (Active functionality) (EVTGEN_COMP_STRUCT_COMP0)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_COMP_STRUCT_COMP0_field {
|
||||
uint32_t u32INT32:32;
|
||||
} stc_EVTGEN_COMP_STRUCT_COMP0_field_t;
|
||||
|
||||
typedef union un_EVTGEN_COMP_STRUCT_COMP0 {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_COMP_STRUCT_COMP0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_COMP_STRUCT_COMP0_t;
|
||||
|
||||
/**
|
||||
* \brief Comparator 1 (DeepSleep functionality) (EVTGEN_COMP_STRUCT_COMP1)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_COMP_STRUCT_COMP1_field {
|
||||
uint32_t u32INT32:32;
|
||||
} stc_EVTGEN_COMP_STRUCT_COMP1_field_t;
|
||||
|
||||
typedef union un_EVTGEN_COMP_STRUCT_COMP1 {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_COMP_STRUCT_COMP1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_COMP_STRUCT_COMP1_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Control (EVTGEN_CTL)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_CTL_field {
|
||||
uint32_t :31;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_EVTGEN_CTL_field_t;
|
||||
|
||||
typedef union un_EVTGEN_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Comparator structures comparator 0 status (EVTGEN_COMP0_STATUS)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_COMP0_STATUS_field {
|
||||
uint32_t u16COMP0_OUT:16;
|
||||
uint32_t :16;
|
||||
} stc_EVTGEN_COMP0_STATUS_field_t;
|
||||
|
||||
typedef union un_EVTGEN_COMP0_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_COMP0_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_COMP0_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Comparator structures comparator 1 status (EVTGEN_COMP1_STATUS)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_COMP1_STATUS_field {
|
||||
uint32_t u16COMP1_OUT:16;
|
||||
uint32_t :16;
|
||||
} stc_EVTGEN_COMP1_STATUS_field_t;
|
||||
|
||||
typedef union un_EVTGEN_COMP1_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_COMP1_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_COMP1_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Counter status (EVTGEN_COUNTER_STATUS)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_COUNTER_STATUS_field {
|
||||
uint32_t :31;
|
||||
uint32_t u1VALID:1;
|
||||
} stc_EVTGEN_COUNTER_STATUS_field_t;
|
||||
|
||||
typedef union un_EVTGEN_COUNTER_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_COUNTER_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_COUNTER_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Counter (EVTGEN_COUNTER)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_COUNTER_field {
|
||||
uint32_t u32INT32:32;
|
||||
} stc_EVTGEN_COUNTER_field_t;
|
||||
|
||||
typedef union un_EVTGEN_COUNTER {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_COUNTER_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_COUNTER_t;
|
||||
|
||||
/**
|
||||
* \brief Ratio control (EVTGEN_RATIO_CTL)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_RATIO_CTL_field {
|
||||
uint32_t :16;
|
||||
uint32_t u3DYNAMIC_MODE:3;
|
||||
uint32_t :11;
|
||||
uint32_t u1DYNAMIC:1;
|
||||
uint32_t u1VALID:1;
|
||||
} stc_EVTGEN_RATIO_CTL_field_t;
|
||||
|
||||
typedef union un_EVTGEN_RATIO_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_RATIO_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_RATIO_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Ratio (EVTGEN_RATIO)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_RATIO_field {
|
||||
uint32_t :8;
|
||||
uint32_t u8FRAC8:8;
|
||||
uint32_t u16INT16:16;
|
||||
} stc_EVTGEN_RATIO_field_t;
|
||||
|
||||
typedef union un_EVTGEN_RATIO {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_RATIO_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_RATIO_t;
|
||||
|
||||
/**
|
||||
* \brief Reference clock control (EVTGEN_REF_CLOCK_CTL)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_REF_CLOCK_CTL_field {
|
||||
uint32_t u8INT_DIV:8;
|
||||
uint32_t :24;
|
||||
} stc_EVTGEN_REF_CLOCK_CTL_field_t;
|
||||
|
||||
typedef union un_EVTGEN_REF_CLOCK_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_REF_CLOCK_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_REF_CLOCK_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt (EVTGEN_INTR)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_INTR_field {
|
||||
uint32_t u16COMP0:16;
|
||||
uint32_t :16;
|
||||
} stc_EVTGEN_INTR_field_t;
|
||||
|
||||
typedef union un_EVTGEN_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt set (EVTGEN_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_INTR_SET_field {
|
||||
uint32_t u16COMP0:16;
|
||||
uint32_t :16;
|
||||
} stc_EVTGEN_INTR_SET_field_t;
|
||||
|
||||
typedef union un_EVTGEN_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt mask (EVTGEN_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_INTR_MASK_field {
|
||||
uint32_t u16COMP0:16;
|
||||
uint32_t :16;
|
||||
} stc_EVTGEN_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_EVTGEN_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt masked (EVTGEN_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_INTR_MASKED_field {
|
||||
uint32_t u16COMP0:16;
|
||||
uint32_t :16;
|
||||
} stc_EVTGEN_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_EVTGEN_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_INTR_MASKED_t;
|
||||
|
||||
/**
|
||||
* \brief DeepSleep interrupt (EVTGEN_INTR_DPSLP)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_INTR_DPSLP_field {
|
||||
uint32_t u16COMP1:16;
|
||||
uint32_t :16;
|
||||
} stc_EVTGEN_INTR_DPSLP_field_t;
|
||||
|
||||
typedef union un_EVTGEN_INTR_DPSLP {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_INTR_DPSLP_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_INTR_DPSLP_t;
|
||||
|
||||
/**
|
||||
* \brief DeepSleep interrupt set (EVTGEN_INTR_DPSLP_SET)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_INTR_DPSLP_SET_field {
|
||||
uint32_t u16COMP1:16;
|
||||
uint32_t :16;
|
||||
} stc_EVTGEN_INTR_DPSLP_SET_field_t;
|
||||
|
||||
typedef union un_EVTGEN_INTR_DPSLP_SET {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_INTR_DPSLP_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_INTR_DPSLP_SET_t;
|
||||
|
||||
/**
|
||||
* \brief DeepSleep interrupt mask (EVTGEN_INTR_DPSLP_MASK)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_INTR_DPSLP_MASK_field {
|
||||
uint32_t u16COMP1:16;
|
||||
uint32_t :16;
|
||||
} stc_EVTGEN_INTR_DPSLP_MASK_field_t;
|
||||
|
||||
typedef union un_EVTGEN_INTR_DPSLP_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_INTR_DPSLP_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_INTR_DPSLP_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief DeepSleep interrupt masked (EVTGEN_INTR_DPSLP_MASKED)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_INTR_DPSLP_MASKED_field {
|
||||
uint32_t u16COMP1:16;
|
||||
uint32_t :16;
|
||||
} stc_EVTGEN_INTR_DPSLP_MASKED_field_t;
|
||||
|
||||
typedef union un_EVTGEN_INTR_DPSLP_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_EVTGEN_INTR_DPSLP_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_EVTGEN_INTR_DPSLP_MASKED_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT)
|
||||
*/
|
||||
typedef struct stc_EVTGEN_COMP_STRUCT {
|
||||
un_EVTGEN_COMP_STRUCT_COMP_CTL_t unCOMP_CTL; /*!< 0x00000000 Comparator control */
|
||||
un_EVTGEN_COMP_STRUCT_COMP0_t unCOMP0; /*!< 0x00000004 Comparator 0 (Active functionality) */
|
||||
un_EVTGEN_COMP_STRUCT_COMP1_t unCOMP1; /*!< 0x00000008 Comparator 1 (DeepSleep functionality) */
|
||||
uint32_t au32Reserved[5];
|
||||
} stc_EVTGEN_COMP_STRUCT_t; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief Event generator (EVTGEN)
|
||||
*/
|
||||
typedef struct stc_EVTGEN {
|
||||
un_EVTGEN_CTL_t unCTL; /*!< 0x00000000 Control */
|
||||
un_EVTGEN_COMP0_STATUS_t unCOMP0_STATUS; /*!< 0x00000004 Comparator structures comparator 0 status */
|
||||
un_EVTGEN_COMP1_STATUS_t unCOMP1_STATUS; /*!< 0x00000008 Comparator structures comparator 1 status */
|
||||
uint32_t u32Reserved;
|
||||
un_EVTGEN_COUNTER_STATUS_t unCOUNTER_STATUS; /*!< 0x00000010 Counter status */
|
||||
un_EVTGEN_COUNTER_t unCOUNTER; /*!< 0x00000014 Counter */
|
||||
uint32_t au32Reserved1[2];
|
||||
un_EVTGEN_RATIO_CTL_t unRATIO_CTL; /*!< 0x00000020 Ratio control */
|
||||
un_EVTGEN_RATIO_t unRATIO; /*!< 0x00000024 Ratio */
|
||||
uint32_t au32Reserved2[2];
|
||||
un_EVTGEN_REF_CLOCK_CTL_t unREF_CLOCK_CTL; /*!< 0x00000030 Reference clock control */
|
||||
uint32_t au32Reserved3[435];
|
||||
un_EVTGEN_INTR_t unINTR; /*!< 0x00000700 Interrupt */
|
||||
un_EVTGEN_INTR_SET_t unINTR_SET; /*!< 0x00000704 Interrupt set */
|
||||
un_EVTGEN_INTR_MASK_t unINTR_MASK; /*!< 0x00000708 Interrupt mask */
|
||||
un_EVTGEN_INTR_MASKED_t unINTR_MASKED; /*!< 0x0000070C Interrupt masked */
|
||||
un_EVTGEN_INTR_DPSLP_t unINTR_DPSLP; /*!< 0x00000710 DeepSleep interrupt */
|
||||
un_EVTGEN_INTR_DPSLP_SET_t unINTR_DPSLP_SET; /*!< 0x00000714 DeepSleep interrupt set */
|
||||
un_EVTGEN_INTR_DPSLP_MASK_t unINTR_DPSLP_MASK; /*!< 0x00000718 DeepSleep interrupt mask */
|
||||
un_EVTGEN_INTR_DPSLP_MASKED_t unINTR_DPSLP_MASKED; /*!< 0x0000071C DeepSleep interrupt masked */
|
||||
uint32_t au32Reserved4[56];
|
||||
stc_EVTGEN_COMP_STRUCT_t COMP_STRUCT[32]; /*!< 0x00000800 Comparator structure */
|
||||
} stc_EVTGEN_t; /*!< Size = 3072 (0xC00) */
|
||||
|
||||
|
||||
/* EVTGEN_COMP_STRUCT.COMP_CTL */
|
||||
#define EVTGEN_COMP_STRUCT_COMP_CTL_COMP0_EN_Pos 0UL
|
||||
#define EVTGEN_COMP_STRUCT_COMP_CTL_COMP0_EN_Msk 0x1UL
|
||||
#define EVTGEN_COMP_STRUCT_COMP_CTL_COMP1_EN_Pos 1UL
|
||||
#define EVTGEN_COMP_STRUCT_COMP_CTL_COMP1_EN_Msk 0x2UL
|
||||
#define EVTGEN_COMP_STRUCT_COMP_CTL_TR_OUT_EDGE_Pos 16UL
|
||||
#define EVTGEN_COMP_STRUCT_COMP_CTL_TR_OUT_EDGE_Msk 0x10000UL
|
||||
#define EVTGEN_COMP_STRUCT_COMP_CTL_ENABLED_Pos 31UL
|
||||
#define EVTGEN_COMP_STRUCT_COMP_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* EVTGEN_COMP_STRUCT.COMP0 */
|
||||
#define EVTGEN_COMP_STRUCT_COMP0_INT32_Pos 0UL
|
||||
#define EVTGEN_COMP_STRUCT_COMP0_INT32_Msk 0xFFFFFFFFUL
|
||||
/* EVTGEN_COMP_STRUCT.COMP1 */
|
||||
#define EVTGEN_COMP_STRUCT_COMP1_INT32_Pos 0UL
|
||||
#define EVTGEN_COMP_STRUCT_COMP1_INT32_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
/* EVTGEN.CTL */
|
||||
#define EVTGEN_CTL_ENABLED_Pos 31UL
|
||||
#define EVTGEN_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* EVTGEN.COMP0_STATUS */
|
||||
#define EVTGEN_COMP0_STATUS_COMP0_OUT_Pos 0UL
|
||||
#define EVTGEN_COMP0_STATUS_COMP0_OUT_Msk 0xFFFFUL
|
||||
/* EVTGEN.COMP1_STATUS */
|
||||
#define EVTGEN_COMP1_STATUS_COMP1_OUT_Pos 0UL
|
||||
#define EVTGEN_COMP1_STATUS_COMP1_OUT_Msk 0xFFFFUL
|
||||
/* EVTGEN.COUNTER_STATUS */
|
||||
#define EVTGEN_COUNTER_STATUS_VALID_Pos 31UL
|
||||
#define EVTGEN_COUNTER_STATUS_VALID_Msk 0x80000000UL
|
||||
/* EVTGEN.COUNTER */
|
||||
#define EVTGEN_COUNTER_INT32_Pos 0UL
|
||||
#define EVTGEN_COUNTER_INT32_Msk 0xFFFFFFFFUL
|
||||
/* EVTGEN.RATIO_CTL */
|
||||
#define EVTGEN_RATIO_CTL_DYNAMIC_MODE_Pos 16UL
|
||||
#define EVTGEN_RATIO_CTL_DYNAMIC_MODE_Msk 0x70000UL
|
||||
#define EVTGEN_RATIO_CTL_DYNAMIC_Pos 30UL
|
||||
#define EVTGEN_RATIO_CTL_DYNAMIC_Msk 0x40000000UL
|
||||
#define EVTGEN_RATIO_CTL_VALID_Pos 31UL
|
||||
#define EVTGEN_RATIO_CTL_VALID_Msk 0x80000000UL
|
||||
/* EVTGEN.RATIO */
|
||||
#define EVTGEN_RATIO_FRAC8_Pos 8UL
|
||||
#define EVTGEN_RATIO_FRAC8_Msk 0xFF00UL
|
||||
#define EVTGEN_RATIO_INT16_Pos 16UL
|
||||
#define EVTGEN_RATIO_INT16_Msk 0xFFFF0000UL
|
||||
/* EVTGEN.REF_CLOCK_CTL */
|
||||
#define EVTGEN_REF_CLOCK_CTL_INT_DIV_Pos 0UL
|
||||
#define EVTGEN_REF_CLOCK_CTL_INT_DIV_Msk 0xFFUL
|
||||
/* EVTGEN.INTR */
|
||||
#define EVTGEN_INTR_COMP0_Pos 0UL
|
||||
#define EVTGEN_INTR_COMP0_Msk 0xFFFFUL
|
||||
/* EVTGEN.INTR_SET */
|
||||
#define EVTGEN_INTR_SET_COMP0_Pos 0UL
|
||||
#define EVTGEN_INTR_SET_COMP0_Msk 0xFFFFUL
|
||||
/* EVTGEN.INTR_MASK */
|
||||
#define EVTGEN_INTR_MASK_COMP0_Pos 0UL
|
||||
#define EVTGEN_INTR_MASK_COMP0_Msk 0xFFFFUL
|
||||
/* EVTGEN.INTR_MASKED */
|
||||
#define EVTGEN_INTR_MASKED_COMP0_Pos 0UL
|
||||
#define EVTGEN_INTR_MASKED_COMP0_Msk 0xFFFFUL
|
||||
/* EVTGEN.INTR_DPSLP */
|
||||
#define EVTGEN_INTR_DPSLP_COMP1_Pos 0UL
|
||||
#define EVTGEN_INTR_DPSLP_COMP1_Msk 0xFFFFUL
|
||||
/* EVTGEN.INTR_DPSLP_SET */
|
||||
#define EVTGEN_INTR_DPSLP_SET_COMP1_Pos 0UL
|
||||
#define EVTGEN_INTR_DPSLP_SET_COMP1_Msk 0xFFFFUL
|
||||
/* EVTGEN.INTR_DPSLP_MASK */
|
||||
#define EVTGEN_INTR_DPSLP_MASK_COMP1_Pos 0UL
|
||||
#define EVTGEN_INTR_DPSLP_MASK_COMP1_Msk 0xFFFFUL
|
||||
/* EVTGEN.INTR_DPSLP_MASKED */
|
||||
#define EVTGEN_INTR_DPSLP_MASKED_COMP1_Pos 0UL
|
||||
#define EVTGEN_INTR_DPSLP_MASKED_COMP1_Msk 0xFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_EVTGEN_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,306 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_fault.h
|
||||
*
|
||||
* \brief
|
||||
* FAULT IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_FAULT_H_
|
||||
#define _CYIP_FAULT_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_STRUCT_SECTION_SIZE 0x00000100UL
|
||||
#define FAULT_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Fault control (FAULT_STRUCT_CTL)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_CTL_field {
|
||||
uint32_t u1TR_EN:1;
|
||||
uint32_t u1OUT_EN:1;
|
||||
uint32_t u1RESET_REQ_EN:1;
|
||||
uint32_t :29;
|
||||
} stc_FAULT_STRUCT_CTL_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Fault status (FAULT_STRUCT_STATUS)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_STATUS_field {
|
||||
uint32_t u7IDX:7;
|
||||
uint32_t :24;
|
||||
uint32_t u1VALID:1;
|
||||
} stc_FAULT_STRUCT_STATUS_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Fault data (FAULT_STRUCT_DATA)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_DATA_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_FAULT_STRUCT_DATA_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_DATA {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_DATA_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_DATA_t;
|
||||
|
||||
/**
|
||||
* \brief Fault pending 0 (FAULT_STRUCT_PENDING0)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_PENDING0_field {
|
||||
uint32_t u32SOURCE:32;
|
||||
} stc_FAULT_STRUCT_PENDING0_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_PENDING0 {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_PENDING0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_PENDING0_t;
|
||||
|
||||
/**
|
||||
* \brief Fault pending 1 (FAULT_STRUCT_PENDING1)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_PENDING1_field {
|
||||
uint32_t u32SOURCE:32;
|
||||
} stc_FAULT_STRUCT_PENDING1_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_PENDING1 {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_PENDING1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_PENDING1_t;
|
||||
|
||||
/**
|
||||
* \brief Fault pending 2 (FAULT_STRUCT_PENDING2)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_PENDING2_field {
|
||||
uint32_t u32SOURCE:32;
|
||||
} stc_FAULT_STRUCT_PENDING2_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_PENDING2 {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_PENDING2_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_PENDING2_t;
|
||||
|
||||
/**
|
||||
* \brief Fault mask 0 (FAULT_STRUCT_MASK0)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_MASK0_field {
|
||||
uint32_t u32SOURCE:32;
|
||||
} stc_FAULT_STRUCT_MASK0_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_MASK0 {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_MASK0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_MASK0_t;
|
||||
|
||||
/**
|
||||
* \brief Fault mask 1 (FAULT_STRUCT_MASK1)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_MASK1_field {
|
||||
uint32_t u32SOURCE:32;
|
||||
} stc_FAULT_STRUCT_MASK1_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_MASK1 {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_MASK1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_MASK1_t;
|
||||
|
||||
/**
|
||||
* \brief Fault mask 2 (FAULT_STRUCT_MASK2)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_MASK2_field {
|
||||
uint32_t u32SOURCE:32;
|
||||
} stc_FAULT_STRUCT_MASK2_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_MASK2 {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_MASK2_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_MASK2_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt (FAULT_STRUCT_INTR)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_INTR_field {
|
||||
uint32_t u1FAULT:1;
|
||||
uint32_t :31;
|
||||
} stc_FAULT_STRUCT_INTR_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt set (FAULT_STRUCT_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_INTR_SET_field {
|
||||
uint32_t u1FAULT:1;
|
||||
uint32_t :31;
|
||||
} stc_FAULT_STRUCT_INTR_SET_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt mask (FAULT_STRUCT_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_INTR_MASK_field {
|
||||
uint32_t u1FAULT:1;
|
||||
uint32_t :31;
|
||||
} stc_FAULT_STRUCT_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt masked (FAULT_STRUCT_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT_INTR_MASKED_field {
|
||||
uint32_t u1FAULT:1;
|
||||
uint32_t :31;
|
||||
} stc_FAULT_STRUCT_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_FAULT_STRUCT_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_FAULT_STRUCT_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FAULT_STRUCT_INTR_MASKED_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Fault structure (FAULT_STRUCT)
|
||||
*/
|
||||
typedef struct stc_FAULT_STRUCT {
|
||||
un_FAULT_STRUCT_CTL_t unCTL; /*!< 0x00000000 Fault control */
|
||||
uint32_t au32Reserved[2];
|
||||
un_FAULT_STRUCT_STATUS_t unSTATUS; /*!< 0x0000000C Fault status */
|
||||
un_FAULT_STRUCT_DATA_t unDATA[4]; /*!< 0x00000010 Fault data */
|
||||
uint32_t au32Reserved1[8];
|
||||
un_FAULT_STRUCT_PENDING0_t unPENDING0; /*!< 0x00000040 Fault pending 0 */
|
||||
un_FAULT_STRUCT_PENDING1_t unPENDING1; /*!< 0x00000044 Fault pending 1 */
|
||||
un_FAULT_STRUCT_PENDING2_t unPENDING2; /*!< 0x00000048 Fault pending 2 */
|
||||
uint32_t u32Reserved2;
|
||||
un_FAULT_STRUCT_MASK0_t unMASK0; /*!< 0x00000050 Fault mask 0 */
|
||||
un_FAULT_STRUCT_MASK1_t unMASK1; /*!< 0x00000054 Fault mask 1 */
|
||||
un_FAULT_STRUCT_MASK2_t unMASK2; /*!< 0x00000058 Fault mask 2 */
|
||||
uint32_t au32Reserved3[25];
|
||||
un_FAULT_STRUCT_INTR_t unINTR; /*!< 0x000000C0 Interrupt */
|
||||
un_FAULT_STRUCT_INTR_SET_t unINTR_SET; /*!< 0x000000C4 Interrupt set */
|
||||
un_FAULT_STRUCT_INTR_MASK_t unINTR_MASK; /*!< 0x000000C8 Interrupt mask */
|
||||
un_FAULT_STRUCT_INTR_MASKED_t unINTR_MASKED; /*!< 0x000000CC Interrupt masked */
|
||||
uint32_t au32Reserved4[12];
|
||||
} stc_FAULT_STRUCT_t; /*!< Size = 256 (0x100) */
|
||||
|
||||
/**
|
||||
* \brief Fault structures (FAULT)
|
||||
*/
|
||||
typedef struct stc_FAULT {
|
||||
stc_FAULT_STRUCT_t STRUCT[4]; /*!< 0x00000000 Fault structure */
|
||||
} stc_FAULT_t; /*!< Size = 1024 (0x400) */
|
||||
|
||||
|
||||
/* FAULT_STRUCT.CTL */
|
||||
#define FAULT_STRUCT_CTL_TR_EN_Pos 0UL
|
||||
#define FAULT_STRUCT_CTL_TR_EN_Msk 0x1UL
|
||||
#define FAULT_STRUCT_CTL_OUT_EN_Pos 1UL
|
||||
#define FAULT_STRUCT_CTL_OUT_EN_Msk 0x2UL
|
||||
#define FAULT_STRUCT_CTL_RESET_REQ_EN_Pos 2UL
|
||||
#define FAULT_STRUCT_CTL_RESET_REQ_EN_Msk 0x4UL
|
||||
/* FAULT_STRUCT.STATUS */
|
||||
#define FAULT_STRUCT_STATUS_IDX_Pos 0UL
|
||||
#define FAULT_STRUCT_STATUS_IDX_Msk 0x7FUL
|
||||
#define FAULT_STRUCT_STATUS_VALID_Pos 31UL
|
||||
#define FAULT_STRUCT_STATUS_VALID_Msk 0x80000000UL
|
||||
/* FAULT_STRUCT.DATA */
|
||||
#define FAULT_STRUCT_DATA_DATA_Pos 0UL
|
||||
#define FAULT_STRUCT_DATA_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.PENDING0 */
|
||||
#define FAULT_STRUCT_PENDING0_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_PENDING0_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.PENDING1 */
|
||||
#define FAULT_STRUCT_PENDING1_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_PENDING1_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.PENDING2 */
|
||||
#define FAULT_STRUCT_PENDING2_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_PENDING2_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.MASK0 */
|
||||
#define FAULT_STRUCT_MASK0_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_MASK0_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.MASK1 */
|
||||
#define FAULT_STRUCT_MASK1_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_MASK1_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.MASK2 */
|
||||
#define FAULT_STRUCT_MASK2_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_MASK2_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.INTR */
|
||||
#define FAULT_STRUCT_INTR_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_INTR_FAULT_Msk 0x1UL
|
||||
/* FAULT_STRUCT.INTR_SET */
|
||||
#define FAULT_STRUCT_INTR_SET_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_INTR_SET_FAULT_Msk 0x1UL
|
||||
/* FAULT_STRUCT.INTR_MASK */
|
||||
#define FAULT_STRUCT_INTR_MASK_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_INTR_MASK_FAULT_Msk 0x1UL
|
||||
/* FAULT_STRUCT.INTR_MASKED */
|
||||
#define FAULT_STRUCT_INTR_MASKED_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_INTR_MASKED_FAULT_Msk 0x1UL
|
||||
|
||||
|
||||
#endif /* _CYIP_FAULT_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,921 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_flashc.h
|
||||
*
|
||||
* \brief
|
||||
* FLASHC IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_FLASHC_H_
|
||||
#define _CYIP_FLASHC_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_FM_CTL_ECT_SECTION_SIZE 0x00001000UL
|
||||
#define FLASHC_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Flash Macro Control (FLASHC_FM_CTL)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FM_CTL_field {
|
||||
uint32_t u5FM_MODE:5;
|
||||
uint32_t :26;
|
||||
uint32_t u1EMB_START:1;
|
||||
} stc_FLASHC_FM_CTL_field_t;
|
||||
|
||||
typedef union un_FLASHC_FM_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FM_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FM_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Flash Macro Margin Mode on Code Flash (FLASHC_FM_CODE_MARGIN)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FM_CODE_MARGIN_field {
|
||||
uint32_t u9MARGIN_DCS_TRIM:9;
|
||||
uint32_t u1MARGIN_DCS_TRIM_EN:1;
|
||||
uint32_t u6MARGIN_RDREG_TRIM:6;
|
||||
uint32_t :13;
|
||||
uint32_t u1MARGIN_PGM_ERS_B:1;
|
||||
uint32_t u1MARGIN_MODE_RDREG_CHNG_EN:1;
|
||||
uint32_t u1MARGIN_MODE_EN:1;
|
||||
} stc_FLASHC_FM_CODE_MARGIN_field_t;
|
||||
|
||||
typedef union un_FLASHC_FM_CODE_MARGIN {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FM_CODE_MARGIN_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FM_CODE_MARGIN_t;
|
||||
|
||||
/**
|
||||
* \brief Flash Macro Address (FLASHC_FM_ADDR)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FM_ADDR_field {
|
||||
uint32_t u32FM_ADDR:32;
|
||||
} stc_FLASHC_FM_ADDR_field_t;
|
||||
|
||||
typedef union un_FLASHC_FM_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FM_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FM_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Flash Density Information (FLASHC_GEOMTRY)
|
||||
*/
|
||||
typedef struct stc_FLASHC_GEOMTRY_field {
|
||||
uint32_t u3CODE_FLASH_DENSITY:3;
|
||||
uint32_t u3WORK_FLASH_DENSITY:3;
|
||||
uint32_t u1CODE_FLASH_SMS_NUMBER:1;
|
||||
uint32_t u1OTP_SIZE_KB:1;
|
||||
uint32_t :24;
|
||||
} stc_FLASHC_GEOMTRY_field_t;
|
||||
|
||||
typedef union un_FLASHC_GEOMTRY {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_GEOMTRY_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_GEOMTRY_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt (FLASHC_INTR)
|
||||
*/
|
||||
typedef struct stc_FLASHC_INTR_field {
|
||||
uint32_t u1INTR:1;
|
||||
uint32_t :31;
|
||||
} stc_FLASHC_INTR_field_t;
|
||||
|
||||
typedef union un_FLASHC_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt Set (FLASHC_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_FLASHC_INTR_SET_field {
|
||||
uint32_t u1INTR_SET:1;
|
||||
uint32_t :31;
|
||||
} stc_FLASHC_INTR_SET_field_t;
|
||||
|
||||
typedef union un_FLASHC_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt Mask (FLASHC_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_FLASHC_INTR_MASK_field {
|
||||
uint32_t u1INTR_MASK:1;
|
||||
uint32_t :31;
|
||||
} stc_FLASHC_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_FLASHC_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt Masked (FLASHC_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_FLASHC_INTR_MASKED_field {
|
||||
uint32_t u1INTR_MASKED:1;
|
||||
uint32_t :31;
|
||||
} stc_FLASHC_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_FLASHC_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_INTR_MASKED_t;
|
||||
|
||||
/**
|
||||
* \brief ECC Data In override information and control bits (FLASHC_ECC_OVERRIDE)
|
||||
*/
|
||||
typedef struct stc_FLASHC_ECC_OVERRIDE_field {
|
||||
uint32_t u8ECC_OVERRIDE_SYNDROME:8;
|
||||
uint32_t :22;
|
||||
uint32_t u1ECC_OVERRIDE_WORK:1;
|
||||
uint32_t u1ECC_OVERRIDE_CODE:1;
|
||||
} stc_FLASHC_ECC_OVERRIDE_field_t;
|
||||
|
||||
typedef union un_FLASHC_ECC_OVERRIDE {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_ECC_OVERRIDE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_ECC_OVERRIDE_t;
|
||||
|
||||
/**
|
||||
* \brief Flash macro data_in[31 to 0] both Code and Work Flash (FLASHC_FM_DATA)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FM_DATA_field {
|
||||
uint32_t u32FM_DATA:32;
|
||||
} stc_FLASHC_FM_DATA_field_t;
|
||||
|
||||
typedef union un_FLASHC_FM_DATA {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FM_DATA_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FM_DATA_t;
|
||||
|
||||
/**
|
||||
* \brief Bookmark register - keeps the current FW HV seq (FLASHC_BOOKMARK)
|
||||
*/
|
||||
typedef struct stc_FLASHC_BOOKMARK_field {
|
||||
uint32_t u32BOOKMARK:32;
|
||||
} stc_FLASHC_BOOKMARK_field_t;
|
||||
|
||||
typedef union un_FLASHC_BOOKMARK {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_BOOKMARK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_BOOKMARK_t;
|
||||
|
||||
/**
|
||||
* \brief Main (Code) Flash Security enable (FLASHC_MAIN_FLASH_SAFETY)
|
||||
*/
|
||||
typedef struct stc_FLASHC_MAIN_FLASH_SAFETY_field {
|
||||
uint32_t u1MAINFLASHWRITEENABLE:1;
|
||||
uint32_t :31;
|
||||
} stc_FLASHC_MAIN_FLASH_SAFETY_field_t;
|
||||
|
||||
typedef union un_FLASHC_MAIN_FLASH_SAFETY {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_MAIN_FLASH_SAFETY_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_MAIN_FLASH_SAFETY_t;
|
||||
|
||||
/**
|
||||
* \brief Status read from Flash Macro (FLASHC_STATUS)
|
||||
*/
|
||||
typedef struct stc_FLASHC_STATUS_field {
|
||||
uint32_t u1PGM_CODE:1;
|
||||
uint32_t u1PGM_WORK:1;
|
||||
uint32_t u1ERASE_CODE:1;
|
||||
uint32_t u1ERASE_WORK:1;
|
||||
uint32_t u1ERS_SUSPEND:1;
|
||||
uint32_t u1BLANK_CHECK_WORK:1;
|
||||
uint32_t u1BLANK_CHCEK_PASS:1;
|
||||
uint32_t :20;
|
||||
uint32_t u1POR_1B_ECC_CORRECTED:1;
|
||||
uint32_t u1POR_2B_ECC_ERROR:1;
|
||||
uint32_t u1NATIVE_POR:1;
|
||||
uint32_t u1HANG:1;
|
||||
uint32_t u1BUSY:1;
|
||||
} stc_FLASHC_STATUS_field_t;
|
||||
|
||||
typedef union un_FLASHC_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Work Flash Security enable (FLASHC_WORK_FLASH_SAFETY)
|
||||
*/
|
||||
typedef struct stc_FLASHC_WORK_FLASH_SAFETY_field {
|
||||
uint32_t u1WORKFLASHWRITEENABLE:1;
|
||||
uint32_t :31;
|
||||
} stc_FLASHC_WORK_FLASH_SAFETY_field_t;
|
||||
|
||||
typedef union un_FLASHC_WORK_FLASH_SAFETY {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_WORK_FLASH_SAFETY_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_WORK_FLASH_SAFETY_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Control (FLASHC_FLASH_CTL)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FLASH_CTL_field {
|
||||
uint32_t u4WS:4;
|
||||
uint32_t :4;
|
||||
uint32_t u1MAIN_MAP:1;
|
||||
uint32_t u1WORK_MAP:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1MAIN_BANK_MODE:1;
|
||||
uint32_t u1WORK_BANK_MODE:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1MAIN_ECC_EN:1;
|
||||
uint32_t u1MAIN_ECC_INJ_EN:1;
|
||||
uint32_t u1MAIN_ERR_SILENT:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1WORK_ECC_EN:1;
|
||||
uint32_t u1WORK_ECC_INJ_EN:1;
|
||||
uint32_t u1WORK_ERR_SILENT:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1WORK_SEQ_RD_EN:1;
|
||||
uint32_t :7;
|
||||
} stc_FLASHC_FLASH_CTL_field_t;
|
||||
|
||||
typedef union un_FLASHC_FLASH_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FLASH_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FLASH_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Flash power control (FLASHC_FLASH_PWR_CTL)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FLASH_PWR_CTL_field {
|
||||
uint32_t u1ENABLE:1;
|
||||
uint32_t u1ENABLE_HV:1;
|
||||
uint32_t :30;
|
||||
} stc_FLASHC_FLASH_PWR_CTL_field_t;
|
||||
|
||||
typedef union un_FLASHC_FLASH_PWR_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FLASH_PWR_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FLASH_PWR_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Command (FLASHC_FLASH_CMD)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FLASH_CMD_field {
|
||||
uint32_t u1INV:1;
|
||||
uint32_t u1BUFF_INV:1;
|
||||
uint32_t :30;
|
||||
} stc_FLASHC_FLASH_CMD_field_t;
|
||||
|
||||
typedef union un_FLASHC_FLASH_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FLASH_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FLASH_CMD_t;
|
||||
|
||||
/**
|
||||
* \brief ECC control (FLASHC_ECC_CTL)
|
||||
*/
|
||||
typedef struct stc_FLASHC_ECC_CTL_field {
|
||||
uint32_t u24WORD_ADDR:24;
|
||||
uint32_t u8PARITY:8;
|
||||
} stc_FLASHC_ECC_CTL_field_t;
|
||||
|
||||
typedef union un_FLASHC_ECC_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_ECC_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_ECC_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief eCT Flash SRAM ECC control 0 (FLASHC_FM_SRAM_ECC_CTL0)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FM_SRAM_ECC_CTL0_field {
|
||||
uint32_t u32ECC_INJ_DATA:32;
|
||||
} stc_FLASHC_FM_SRAM_ECC_CTL0_field_t;
|
||||
|
||||
typedef union un_FLASHC_FM_SRAM_ECC_CTL0 {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FM_SRAM_ECC_CTL0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FM_SRAM_ECC_CTL0_t;
|
||||
|
||||
/**
|
||||
* \brief eCT Flash SRAM ECC control 1 (FLASHC_FM_SRAM_ECC_CTL1)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FM_SRAM_ECC_CTL1_field {
|
||||
uint32_t u7ECC_INJ_PARITY:7;
|
||||
uint32_t :25;
|
||||
} stc_FLASHC_FM_SRAM_ECC_CTL1_field_t;
|
||||
|
||||
typedef union un_FLASHC_FM_SRAM_ECC_CTL1 {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FM_SRAM_ECC_CTL1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FM_SRAM_ECC_CTL1_t;
|
||||
|
||||
/**
|
||||
* \brief eCT Flash SRAM ECC control 2 (FLASHC_FM_SRAM_ECC_CTL2)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FM_SRAM_ECC_CTL2_field {
|
||||
uint32_t u32CORRECTED_DATA:32;
|
||||
} stc_FLASHC_FM_SRAM_ECC_CTL2_field_t;
|
||||
|
||||
typedef union un_FLASHC_FM_SRAM_ECC_CTL2 {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FM_SRAM_ECC_CTL2_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FM_SRAM_ECC_CTL2_t;
|
||||
|
||||
/**
|
||||
* \brief eCT Flash SRAM ECC control 3 (FLASHC_FM_SRAM_ECC_CTL3)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FM_SRAM_ECC_CTL3_field {
|
||||
uint32_t u1ECC_ENABLE:1;
|
||||
uint32_t :3;
|
||||
uint32_t u1ECC_INJ_EN:1;
|
||||
uint32_t :3;
|
||||
uint32_t u1ECC_TEST_FAIL:1;
|
||||
uint32_t :23;
|
||||
} stc_FLASHC_FM_SRAM_ECC_CTL3_field_t;
|
||||
|
||||
typedef union un_FLASHC_FM_SRAM_ECC_CTL3 {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_FM_SRAM_ECC_CTL3_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_FM_SRAM_ECC_CTL3_t;
|
||||
|
||||
/**
|
||||
* \brief CM0+ cache control (FLASHC_CM0_CA_CTL0)
|
||||
*/
|
||||
typedef struct stc_FLASHC_CM0_CA_CTL0_field {
|
||||
uint32_t u1RAM_ECC_EN:1;
|
||||
uint32_t u1RAM_ECC_INJ_EN:1;
|
||||
uint32_t :14;
|
||||
uint32_t u2WAY:2;
|
||||
uint32_t :6;
|
||||
uint32_t u3SET_ADDR:3;
|
||||
uint32_t :3;
|
||||
uint32_t u1PREF_EN:1;
|
||||
uint32_t u1CA_EN:1;
|
||||
} stc_FLASHC_CM0_CA_CTL0_field_t;
|
||||
|
||||
typedef union un_FLASHC_CM0_CA_CTL0 {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_CM0_CA_CTL0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_CM0_CA_CTL0_t;
|
||||
|
||||
/**
|
||||
* \brief CM0+ cache control (FLASHC_CM0_CA_CTL1)
|
||||
*/
|
||||
typedef struct stc_FLASHC_CM0_CA_CTL1_field {
|
||||
uint32_t u2PWR_MODE:2;
|
||||
uint32_t :14;
|
||||
uint32_t u16VECTKEYSTAT:16;
|
||||
} stc_FLASHC_CM0_CA_CTL1_field_t;
|
||||
|
||||
typedef union un_FLASHC_CM0_CA_CTL1 {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_CM0_CA_CTL1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_CM0_CA_CTL1_t;
|
||||
|
||||
/**
|
||||
* \brief CM0+ cache control (FLASHC_CM0_CA_CTL2)
|
||||
*/
|
||||
typedef struct stc_FLASHC_CM0_CA_CTL2_field {
|
||||
uint32_t u10PWRUP_DELAY:10;
|
||||
uint32_t :22;
|
||||
} stc_FLASHC_CM0_CA_CTL2_field_t;
|
||||
|
||||
typedef union un_FLASHC_CM0_CA_CTL2 {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_CM0_CA_CTL2_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_CM0_CA_CTL2_t;
|
||||
|
||||
/**
|
||||
* \brief CM0+ cache status 0 (FLASHC_CM0_CA_STATUS0)
|
||||
*/
|
||||
typedef struct stc_FLASHC_CM0_CA_STATUS0_field {
|
||||
uint32_t u32VALID32:32;
|
||||
} stc_FLASHC_CM0_CA_STATUS0_field_t;
|
||||
|
||||
typedef union un_FLASHC_CM0_CA_STATUS0 {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_CM0_CA_STATUS0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_CM0_CA_STATUS0_t;
|
||||
|
||||
/**
|
||||
* \brief CM0+ cache status 1 (FLASHC_CM0_CA_STATUS1)
|
||||
*/
|
||||
typedef struct stc_FLASHC_CM0_CA_STATUS1_field {
|
||||
uint32_t u32TAG:32;
|
||||
} stc_FLASHC_CM0_CA_STATUS1_field_t;
|
||||
|
||||
typedef union un_FLASHC_CM0_CA_STATUS1 {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_CM0_CA_STATUS1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_CM0_CA_STATUS1_t;
|
||||
|
||||
/**
|
||||
* \brief CM0+ cache status 2 (FLASHC_CM0_CA_STATUS2)
|
||||
*/
|
||||
typedef struct stc_FLASHC_CM0_CA_STATUS2_field {
|
||||
uint32_t u6LRU:6;
|
||||
uint32_t :26;
|
||||
} stc_FLASHC_CM0_CA_STATUS2_field_t;
|
||||
|
||||
typedef union un_FLASHC_CM0_CA_STATUS2 {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_CM0_CA_STATUS2_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_CM0_CA_STATUS2_t;
|
||||
|
||||
/**
|
||||
* \brief CM0+ interface status (FLASHC_CM0_STATUS)
|
||||
*/
|
||||
typedef struct stc_FLASHC_CM0_STATUS_field {
|
||||
uint32_t u1MAIN_INTERNAL_ERR:1;
|
||||
uint32_t u1WORK_INTERNAL_ERR:1;
|
||||
uint32_t :30;
|
||||
} stc_FLASHC_CM0_STATUS_field_t;
|
||||
|
||||
typedef union un_FLASHC_CM0_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_CM0_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_CM0_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief CM7 #0 interface status (FLASHC_CM7_0_STATUS)
|
||||
*/
|
||||
typedef struct stc_FLASHC_CM7_0_STATUS_field {
|
||||
uint32_t u1MAIN_INTERNAL_ERR:1;
|
||||
uint32_t u1WORK_INTERNAL_ERR:1;
|
||||
uint32_t :30;
|
||||
} stc_FLASHC_CM7_0_STATUS_field_t;
|
||||
|
||||
typedef union un_FLASHC_CM7_0_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_CM7_0_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_CM7_0_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief CM7 #1 interface status (FLASHC_CM7_1_STATUS)
|
||||
*/
|
||||
typedef struct stc_FLASHC_CM7_1_STATUS_field {
|
||||
uint32_t u1MAIN_INTERNAL_ERR:1;
|
||||
uint32_t u1WORK_INTERNAL_ERR:1;
|
||||
uint32_t :30;
|
||||
} stc_FLASHC_CM7_1_STATUS_field_t;
|
||||
|
||||
typedef union un_FLASHC_CM7_1_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_CM7_1_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_CM7_1_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Cryptography buffer control (FLASHC_CRYPTO_BUFF_CTL)
|
||||
*/
|
||||
typedef struct stc_FLASHC_CRYPTO_BUFF_CTL_field {
|
||||
uint32_t :30;
|
||||
uint32_t u1PREF_EN:1;
|
||||
} stc_FLASHC_CRYPTO_BUFF_CTL_field_t;
|
||||
|
||||
typedef union un_FLASHC_CRYPTO_BUFF_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_CRYPTO_BUFF_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_CRYPTO_BUFF_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Datawire 0 buffer control (FLASHC_DW0_BUFF_CTL)
|
||||
*/
|
||||
typedef struct stc_FLASHC_DW0_BUFF_CTL_field {
|
||||
uint32_t :30;
|
||||
uint32_t u1PREF_EN:1;
|
||||
} stc_FLASHC_DW0_BUFF_CTL_field_t;
|
||||
|
||||
typedef union un_FLASHC_DW0_BUFF_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_DW0_BUFF_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_DW0_BUFF_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Datawire 1 buffer control (FLASHC_DW1_BUFF_CTL)
|
||||
*/
|
||||
typedef struct stc_FLASHC_DW1_BUFF_CTL_field {
|
||||
uint32_t :30;
|
||||
uint32_t u1PREF_EN:1;
|
||||
} stc_FLASHC_DW1_BUFF_CTL_field_t;
|
||||
|
||||
typedef union un_FLASHC_DW1_BUFF_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_DW1_BUFF_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_DW1_BUFF_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief DMA controller buffer control (FLASHC_DMAC_BUFF_CTL)
|
||||
*/
|
||||
typedef struct stc_FLASHC_DMAC_BUFF_CTL_field {
|
||||
uint32_t :30;
|
||||
uint32_t u1PREF_EN:1;
|
||||
} stc_FLASHC_DMAC_BUFF_CTL_field_t;
|
||||
|
||||
typedef union un_FLASHC_DMAC_BUFF_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_DMAC_BUFF_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_DMAC_BUFF_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Slow external master 0 buffer control (FLASHC_SLOW0_MS_BUFF_CTL)
|
||||
*/
|
||||
typedef struct stc_FLASHC_SLOW0_MS_BUFF_CTL_field {
|
||||
uint32_t :30;
|
||||
uint32_t u1PREF_EN:1;
|
||||
} stc_FLASHC_SLOW0_MS_BUFF_CTL_field_t;
|
||||
|
||||
typedef union un_FLASHC_SLOW0_MS_BUFF_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_SLOW0_MS_BUFF_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_SLOW0_MS_BUFF_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Slow external master 1 buffer control (FLASHC_SLOW1_MS_BUFF_CTL)
|
||||
*/
|
||||
typedef struct stc_FLASHC_SLOW1_MS_BUFF_CTL_field {
|
||||
uint32_t :30;
|
||||
uint32_t u1PREF_EN:1;
|
||||
} stc_FLASHC_SLOW1_MS_BUFF_CTL_field_t;
|
||||
|
||||
typedef union un_FLASHC_SLOW1_MS_BUFF_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_FLASHC_SLOW1_MS_BUFF_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_FLASHC_SLOW1_MS_BUFF_CTL_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Flash Macro Registers (FLASHC_FM_CTL_ECT)
|
||||
*/
|
||||
typedef struct stc_FLASHC_FM_CTL_ECT {
|
||||
un_FLASHC_FM_CTL_t unFM_CTL; /*!< 0x00000000 Flash Macro Control */
|
||||
un_FLASHC_FM_CODE_MARGIN_t unFM_CODE_MARGIN; /*!< 0x00000004 Flash Macro Margin Mode on Code Flash */
|
||||
un_FLASHC_FM_ADDR_t unFM_ADDR; /*!< 0x00000008 Flash Macro Address */
|
||||
un_FLASHC_GEOMTRY_t unGEOMTRY; /*!< 0x0000000C Flash Density Information */
|
||||
uint32_t au32Reserved[4];
|
||||
un_FLASHC_INTR_t unINTR; /*!< 0x00000020 Interrupt */
|
||||
un_FLASHC_INTR_SET_t unINTR_SET; /*!< 0x00000024 Interrupt Set */
|
||||
un_FLASHC_INTR_MASK_t unINTR_MASK; /*!< 0x00000028 Interrupt Mask */
|
||||
un_FLASHC_INTR_MASKED_t unINTR_MASKED; /*!< 0x0000002C Interrupt Masked */
|
||||
un_FLASHC_ECC_OVERRIDE_t unECC_OVERRIDE; /*!< 0x00000030 ECC Data In override information and control bits */
|
||||
uint32_t au32Reserved1[3];
|
||||
un_FLASHC_FM_DATA_t unFM_DATA; /*!< 0x00000040 Flash macro data_in[31 to 0] both Code and Work Flash */
|
||||
uint32_t au32Reserved2[8];
|
||||
un_FLASHC_BOOKMARK_t unBOOKMARK; /*!< 0x00000064 Bookmark register - keeps the current FW HV seq */
|
||||
uint32_t au32Reserved3[230];
|
||||
un_FLASHC_MAIN_FLASH_SAFETY_t unMAIN_FLASH_SAFETY; /*!< 0x00000400 Main (Code) Flash Security enable */
|
||||
un_FLASHC_STATUS_t unSTATUS; /*!< 0x00000404 Status read from Flash Macro */
|
||||
uint32_t au32Reserved4[62];
|
||||
un_FLASHC_WORK_FLASH_SAFETY_t unWORK_FLASH_SAFETY; /*!< 0x00000500 Work Flash Security enable */
|
||||
uint32_t au32Reserved5[703];
|
||||
} stc_FLASHC_FM_CTL_ECT_t; /*!< Size = 4096 (0x1000) */
|
||||
|
||||
/**
|
||||
* \brief Flash controller (FLASHC)
|
||||
*/
|
||||
typedef struct stc_FLASHC {
|
||||
un_FLASHC_FLASH_CTL_t unFLASH_CTL; /*!< 0x00000000 Control */
|
||||
un_FLASHC_FLASH_PWR_CTL_t unFLASH_PWR_CTL; /*!< 0x00000004 Flash power control */
|
||||
un_FLASHC_FLASH_CMD_t unFLASH_CMD; /*!< 0x00000008 Command */
|
||||
uint32_t au32Reserved[165];
|
||||
un_FLASHC_ECC_CTL_t unECC_CTL; /*!< 0x000002A0 ECC control */
|
||||
uint32_t au32Reserved1[3];
|
||||
un_FLASHC_FM_SRAM_ECC_CTL0_t unFM_SRAM_ECC_CTL0; /*!< 0x000002B0 eCT Flash SRAM ECC control 0 */
|
||||
un_FLASHC_FM_SRAM_ECC_CTL1_t unFM_SRAM_ECC_CTL1; /*!< 0x000002B4 eCT Flash SRAM ECC control 1 */
|
||||
un_FLASHC_FM_SRAM_ECC_CTL2_t unFM_SRAM_ECC_CTL2; /*!< 0x000002B8 eCT Flash SRAM ECC control 2 */
|
||||
un_FLASHC_FM_SRAM_ECC_CTL3_t unFM_SRAM_ECC_CTL3; /*!< 0x000002BC eCT Flash SRAM ECC control 3 */
|
||||
uint32_t au32Reserved2[80];
|
||||
un_FLASHC_CM0_CA_CTL0_t unCM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */
|
||||
un_FLASHC_CM0_CA_CTL1_t unCM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */
|
||||
un_FLASHC_CM0_CA_CTL2_t unCM0_CA_CTL2; /*!< 0x00000408 CM0+ cache control */
|
||||
uint32_t au32Reserved3[13];
|
||||
un_FLASHC_CM0_CA_STATUS0_t unCM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */
|
||||
un_FLASHC_CM0_CA_STATUS1_t unCM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */
|
||||
un_FLASHC_CM0_CA_STATUS2_t unCM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */
|
||||
uint32_t au32Reserved4[5];
|
||||
un_FLASHC_CM0_STATUS_t unCM0_STATUS; /*!< 0x00000460 CM0+ interface status */
|
||||
uint32_t au32Reserved5[31];
|
||||
un_FLASHC_CM7_0_STATUS_t unCM7_0_STATUS; /*!< 0x000004E0 CM7 #0 interface status */
|
||||
uint32_t au32Reserved6[31];
|
||||
un_FLASHC_CM7_1_STATUS_t unCM7_1_STATUS; /*!< 0x00000560 CM7 #1 interface status */
|
||||
uint32_t au32Reserved7[7];
|
||||
un_FLASHC_CRYPTO_BUFF_CTL_t unCRYPTO_BUFF_CTL; /*!< 0x00000580 Cryptography buffer control */
|
||||
uint32_t au32Reserved8[31];
|
||||
un_FLASHC_DW0_BUFF_CTL_t unDW0_BUFF_CTL; /*!< 0x00000600 Datawire 0 buffer control */
|
||||
uint32_t au32Reserved9[31];
|
||||
un_FLASHC_DW1_BUFF_CTL_t unDW1_BUFF_CTL; /*!< 0x00000680 Datawire 1 buffer control */
|
||||
uint32_t au32Reserved10[31];
|
||||
un_FLASHC_DMAC_BUFF_CTL_t unDMAC_BUFF_CTL; /*!< 0x00000700 DMA controller buffer control */
|
||||
uint32_t au32Reserved11[31];
|
||||
un_FLASHC_SLOW0_MS_BUFF_CTL_t unSLOW0_MS_BUFF_CTL; /*!< 0x00000780 Slow external master 0 buffer control */
|
||||
uint32_t au32Reserved12[31];
|
||||
un_FLASHC_SLOW1_MS_BUFF_CTL_t unSLOW1_MS_BUFF_CTL; /*!< 0x00000800 Slow external master 1 buffer control */
|
||||
uint32_t au32Reserved13[14847];
|
||||
stc_FLASHC_FM_CTL_ECT_t FM_CTL_ECT; /*!< 0x0000F000 Flash Macro Registers */
|
||||
} stc_FLASHC_t; /*!< Size = 65536 (0x10000) */
|
||||
|
||||
|
||||
/* FLASHC_FM_CTL_ECT.FM_CTL */
|
||||
#define FLASHC_FM_CTL_ECT_FM_CTL_FM_MODE_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CTL_FM_MODE_Msk 0x1FUL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CTL_EMB_START_Pos 31UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CTL_EMB_START_Msk 0x80000000UL
|
||||
/* FLASHC_FM_CTL_ECT.FM_CODE_MARGIN */
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_DCS_TRIM_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_DCS_TRIM_Msk 0x1FFUL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_DCS_TRIM_EN_Pos 9UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_DCS_TRIM_EN_Msk 0x200UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_RDREG_TRIM_Pos 10UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_RDREG_TRIM_Msk 0xFC00UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_PGM_ERS_B_Pos 29UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_PGM_ERS_B_Msk 0x20000000UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_MODE_RDREG_CHNG_EN_Pos 30UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_MODE_RDREG_CHNG_EN_Msk 0x40000000UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_MODE_EN_Pos 31UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_MODE_EN_Msk 0x80000000UL
|
||||
/* FLASHC_FM_CTL_ECT.FM_ADDR */
|
||||
#define FLASHC_FM_CTL_ECT_FM_ADDR_FM_ADDR_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_ADDR_FM_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC_FM_CTL_ECT.GEOMTRY */
|
||||
#define FLASHC_FM_CTL_ECT_GEOMTRY_CODE_FLASH_DENSITY_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_GEOMTRY_CODE_FLASH_DENSITY_Msk 0x7UL
|
||||
#define FLASHC_FM_CTL_ECT_GEOMTRY_WORK_FLASH_DENSITY_Pos 3UL
|
||||
#define FLASHC_FM_CTL_ECT_GEOMTRY_WORK_FLASH_DENSITY_Msk 0x38UL
|
||||
#define FLASHC_FM_CTL_ECT_GEOMTRY_CODE_FLASH_SMS_NUMBER_Pos 6UL
|
||||
#define FLASHC_FM_CTL_ECT_GEOMTRY_CODE_FLASH_SMS_NUMBER_Msk 0x40UL
|
||||
#define FLASHC_FM_CTL_ECT_GEOMTRY_OTP_SIZE_KB_Pos 7UL
|
||||
#define FLASHC_FM_CTL_ECT_GEOMTRY_OTP_SIZE_KB_Msk 0x80UL
|
||||
/* FLASHC_FM_CTL_ECT.INTR */
|
||||
#define FLASHC_FM_CTL_ECT_INTR_INTR_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_INTR_INTR_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL_ECT.INTR_SET */
|
||||
#define FLASHC_FM_CTL_ECT_INTR_SET_INTR_SET_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_INTR_SET_INTR_SET_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL_ECT.INTR_MASK */
|
||||
#define FLASHC_FM_CTL_ECT_INTR_MASK_INTR_MASK_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_INTR_MASK_INTR_MASK_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL_ECT.INTR_MASKED */
|
||||
#define FLASHC_FM_CTL_ECT_INTR_MASKED_INTR_MASKED_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_INTR_MASKED_INTR_MASKED_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL_ECT.ECC_OVERRIDE */
|
||||
#define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_SYNDROME_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_SYNDROME_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_WORK_Pos 30UL
|
||||
#define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_WORK_Msk 0x40000000UL
|
||||
#define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_CODE_Pos 31UL
|
||||
#define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_CODE_Msk 0x80000000UL
|
||||
/* FLASHC_FM_CTL_ECT.FM_DATA */
|
||||
#define FLASHC_FM_CTL_ECT_FM_DATA_FM_DATA_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_FM_DATA_FM_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC_FM_CTL_ECT.BOOKMARK */
|
||||
#define FLASHC_FM_CTL_ECT_BOOKMARK_BOOKMARK_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_BOOKMARK_BOOKMARK_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC_FM_CTL_ECT.MAIN_FLASH_SAFETY */
|
||||
#define FLASHC_FM_CTL_ECT_MAIN_FLASH_SAFETY_MAINFLASHWRITEENABLE_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_MAIN_FLASH_SAFETY_MAINFLASHWRITEENABLE_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL_ECT.STATUS */
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_PGM_CODE_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_PGM_CODE_Msk 0x1UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_PGM_WORK_Pos 1UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_PGM_WORK_Msk 0x2UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_ERASE_CODE_Pos 2UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_ERASE_CODE_Msk 0x4UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_ERASE_WORK_Pos 3UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_ERASE_WORK_Msk 0x8UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_ERS_SUSPEND_Pos 4UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_ERS_SUSPEND_Msk 0x10UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_BLANK_CHECK_WORK_Pos 5UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_BLANK_CHECK_WORK_Msk 0x20UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_BLANK_CHCEK_PASS_Pos 6UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_BLANK_CHCEK_PASS_Msk 0x40UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_POR_1B_ECC_CORRECTED_Pos 27UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_POR_1B_ECC_CORRECTED_Msk 0x8000000UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_POR_2B_ECC_ERROR_Pos 28UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_POR_2B_ECC_ERROR_Msk 0x10000000UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_NATIVE_POR_Pos 29UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_NATIVE_POR_Msk 0x20000000UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_HANG_Pos 30UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_HANG_Msk 0x40000000UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_BUSY_Pos 31UL
|
||||
#define FLASHC_FM_CTL_ECT_STATUS_BUSY_Msk 0x80000000UL
|
||||
/* FLASHC_FM_CTL_ECT.WORK_FLASH_SAFETY */
|
||||
#define FLASHC_FM_CTL_ECT_WORK_FLASH_SAFETY_WORKFLASHWRITEENABLE_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ECT_WORK_FLASH_SAFETY_WORKFLASHWRITEENABLE_Msk 0x1UL
|
||||
|
||||
|
||||
/* FLASHC.FLASH_CTL */
|
||||
#define FLASHC_FLASH_CTL_WS_Pos 0UL
|
||||
#define FLASHC_FLASH_CTL_WS_Msk 0xFUL
|
||||
#define FLASHC_FLASH_CTL_MAIN_MAP_Pos 8UL
|
||||
#define FLASHC_FLASH_CTL_MAIN_MAP_Msk 0x100UL
|
||||
#define FLASHC_FLASH_CTL_WORK_MAP_Pos 9UL
|
||||
#define FLASHC_FLASH_CTL_WORK_MAP_Msk 0x200UL
|
||||
#define FLASHC_FLASH_CTL_MAIN_BANK_MODE_Pos 12UL
|
||||
#define FLASHC_FLASH_CTL_MAIN_BANK_MODE_Msk 0x1000UL
|
||||
#define FLASHC_FLASH_CTL_WORK_BANK_MODE_Pos 13UL
|
||||
#define FLASHC_FLASH_CTL_WORK_BANK_MODE_Msk 0x2000UL
|
||||
#define FLASHC_FLASH_CTL_MAIN_ECC_EN_Pos 16UL
|
||||
#define FLASHC_FLASH_CTL_MAIN_ECC_EN_Msk 0x10000UL
|
||||
#define FLASHC_FLASH_CTL_MAIN_ECC_INJ_EN_Pos 17UL
|
||||
#define FLASHC_FLASH_CTL_MAIN_ECC_INJ_EN_Msk 0x20000UL
|
||||
#define FLASHC_FLASH_CTL_MAIN_ERR_SILENT_Pos 18UL
|
||||
#define FLASHC_FLASH_CTL_MAIN_ERR_SILENT_Msk 0x40000UL
|
||||
#define FLASHC_FLASH_CTL_WORK_ECC_EN_Pos 20UL
|
||||
#define FLASHC_FLASH_CTL_WORK_ECC_EN_Msk 0x100000UL
|
||||
#define FLASHC_FLASH_CTL_WORK_ECC_INJ_EN_Pos 21UL
|
||||
#define FLASHC_FLASH_CTL_WORK_ECC_INJ_EN_Msk 0x200000UL
|
||||
#define FLASHC_FLASH_CTL_WORK_ERR_SILENT_Pos 22UL
|
||||
#define FLASHC_FLASH_CTL_WORK_ERR_SILENT_Msk 0x400000UL
|
||||
#define FLASHC_FLASH_CTL_WORK_SEQ_RD_EN_Pos 24UL
|
||||
#define FLASHC_FLASH_CTL_WORK_SEQ_RD_EN_Msk 0x1000000UL
|
||||
/* FLASHC.FLASH_PWR_CTL */
|
||||
#define FLASHC_FLASH_PWR_CTL_ENABLE_Pos 0UL
|
||||
#define FLASHC_FLASH_PWR_CTL_ENABLE_Msk 0x1UL
|
||||
#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Pos 1UL
|
||||
#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Msk 0x2UL
|
||||
/* FLASHC.FLASH_CMD */
|
||||
#define FLASHC_FLASH_CMD_INV_Pos 0UL
|
||||
#define FLASHC_FLASH_CMD_INV_Msk 0x1UL
|
||||
#define FLASHC_FLASH_CMD_BUFF_INV_Pos 1UL
|
||||
#define FLASHC_FLASH_CMD_BUFF_INV_Msk 0x2UL
|
||||
/* FLASHC.ECC_CTL */
|
||||
#define FLASHC_ECC_CTL_WORD_ADDR_Pos 0UL
|
||||
#define FLASHC_ECC_CTL_WORD_ADDR_Msk 0xFFFFFFUL
|
||||
#define FLASHC_ECC_CTL_PARITY_Pos 24UL
|
||||
#define FLASHC_ECC_CTL_PARITY_Msk 0xFF000000UL
|
||||
/* FLASHC.FM_SRAM_ECC_CTL0 */
|
||||
#define FLASHC_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Pos 0UL
|
||||
#define FLASHC_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.FM_SRAM_ECC_CTL1 */
|
||||
#define FLASHC_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Pos 0UL
|
||||
#define FLASHC_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Msk 0x7FUL
|
||||
/* FLASHC.FM_SRAM_ECC_CTL2 */
|
||||
#define FLASHC_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Pos 0UL
|
||||
#define FLASHC_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.FM_SRAM_ECC_CTL3 */
|
||||
#define FLASHC_FM_SRAM_ECC_CTL3_ECC_ENABLE_Pos 0UL
|
||||
#define FLASHC_FM_SRAM_ECC_CTL3_ECC_ENABLE_Msk 0x1UL
|
||||
#define FLASHC_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Pos 4UL
|
||||
#define FLASHC_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Msk 0x10UL
|
||||
#define FLASHC_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Pos 8UL
|
||||
#define FLASHC_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Msk 0x100UL
|
||||
/* FLASHC.CM0_CA_CTL0 */
|
||||
#define FLASHC_CM0_CA_CTL0_RAM_ECC_EN_Pos 0UL
|
||||
#define FLASHC_CM0_CA_CTL0_RAM_ECC_EN_Msk 0x1UL
|
||||
#define FLASHC_CM0_CA_CTL0_RAM_ECC_INJ_EN_Pos 1UL
|
||||
#define FLASHC_CM0_CA_CTL0_RAM_ECC_INJ_EN_Msk 0x2UL
|
||||
#define FLASHC_CM0_CA_CTL0_WAY_Pos 16UL
|
||||
#define FLASHC_CM0_CA_CTL0_WAY_Msk 0x30000UL
|
||||
#define FLASHC_CM0_CA_CTL0_SET_ADDR_Pos 24UL
|
||||
#define FLASHC_CM0_CA_CTL0_SET_ADDR_Msk 0x7000000UL
|
||||
#define FLASHC_CM0_CA_CTL0_PREF_EN_Pos 30UL
|
||||
#define FLASHC_CM0_CA_CTL0_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_CM0_CA_CTL0_CA_EN_Pos 31UL
|
||||
#define FLASHC_CM0_CA_CTL0_CA_EN_Msk 0x80000000UL
|
||||
/* FLASHC.CM0_CA_CTL1 */
|
||||
#define FLASHC_CM0_CA_CTL1_PWR_MODE_Pos 0UL
|
||||
#define FLASHC_CM0_CA_CTL1_PWR_MODE_Msk 0x3UL
|
||||
#define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Pos 16UL
|
||||
#define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* FLASHC.CM0_CA_CTL2 */
|
||||
#define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Pos 0UL
|
||||
#define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
|
||||
/* FLASHC.CM0_CA_STATUS0 */
|
||||
#define FLASHC_CM0_CA_STATUS0_VALID32_Pos 0UL
|
||||
#define FLASHC_CM0_CA_STATUS0_VALID32_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.CM0_CA_STATUS1 */
|
||||
#define FLASHC_CM0_CA_STATUS1_TAG_Pos 0UL
|
||||
#define FLASHC_CM0_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.CM0_CA_STATUS2 */
|
||||
#define FLASHC_CM0_CA_STATUS2_LRU_Pos 0UL
|
||||
#define FLASHC_CM0_CA_STATUS2_LRU_Msk 0x3FUL
|
||||
/* FLASHC.CM0_STATUS */
|
||||
#define FLASHC_CM0_STATUS_MAIN_INTERNAL_ERR_Pos 0UL
|
||||
#define FLASHC_CM0_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL
|
||||
#define FLASHC_CM0_STATUS_WORK_INTERNAL_ERR_Pos 1UL
|
||||
#define FLASHC_CM0_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL
|
||||
/* FLASHC.CM7_0_STATUS */
|
||||
#define FLASHC_CM7_0_STATUS_MAIN_INTERNAL_ERR_Pos 0UL
|
||||
#define FLASHC_CM7_0_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL
|
||||
#define FLASHC_CM7_0_STATUS_WORK_INTERNAL_ERR_Pos 1UL
|
||||
#define FLASHC_CM7_0_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL
|
||||
/* FLASHC.CM7_1_STATUS */
|
||||
#define FLASHC_CM7_1_STATUS_MAIN_INTERNAL_ERR_Pos 0UL
|
||||
#define FLASHC_CM7_1_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL
|
||||
#define FLASHC_CM7_1_STATUS_WORK_INTERNAL_ERR_Pos 1UL
|
||||
#define FLASHC_CM7_1_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL
|
||||
/* FLASHC.CRYPTO_BUFF_CTL */
|
||||
#define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
/* FLASHC.DW0_BUFF_CTL */
|
||||
#define FLASHC_DW0_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_DW0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
/* FLASHC.DW1_BUFF_CTL */
|
||||
#define FLASHC_DW1_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_DW1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
/* FLASHC.DMAC_BUFF_CTL */
|
||||
#define FLASHC_DMAC_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_DMAC_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
/* FLASHC.SLOW0_MS_BUFF_CTL */
|
||||
#define FLASHC_SLOW0_MS_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_SLOW0_MS_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
/* FLASHC.SLOW1_MS_BUFF_CTL */
|
||||
#define FLASHC_SLOW1_MS_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_SLOW1_MS_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_FLASHC_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,988 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_gpio_v3.h
|
||||
*
|
||||
* \brief
|
||||
* GPIO IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_GPIO_V3_H_
|
||||
#define _CYIP_GPIO_V3_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_PRT_SECTION_SIZE 0x00000080UL
|
||||
#define GPIO_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Port output data register (GPIO_PRT_OUT)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_OUT_field {
|
||||
uint32_t u1OUT0:1;
|
||||
uint32_t u1OUT1:1;
|
||||
uint32_t u1OUT2:1;
|
||||
uint32_t u1OUT3:1;
|
||||
uint32_t u1OUT4:1;
|
||||
uint32_t u1OUT5:1;
|
||||
uint32_t u1OUT6:1;
|
||||
uint32_t u1OUT7:1;
|
||||
uint32_t :24;
|
||||
} stc_GPIO_PRT_OUT_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_OUT {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_OUT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_OUT_t;
|
||||
|
||||
/**
|
||||
* \brief Port output data clear register (GPIO_PRT_OUT_CLR)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_OUT_CLR_field {
|
||||
uint32_t u1OUT0:1;
|
||||
uint32_t u1OUT1:1;
|
||||
uint32_t u1OUT2:1;
|
||||
uint32_t u1OUT3:1;
|
||||
uint32_t u1OUT4:1;
|
||||
uint32_t u1OUT5:1;
|
||||
uint32_t u1OUT6:1;
|
||||
uint32_t u1OUT7:1;
|
||||
uint32_t :24;
|
||||
} stc_GPIO_PRT_OUT_CLR_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_OUT_CLR {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_OUT_CLR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_OUT_CLR_t;
|
||||
|
||||
/**
|
||||
* \brief Port output data set register (GPIO_PRT_OUT_SET)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_OUT_SET_field {
|
||||
uint32_t u1OUT0:1;
|
||||
uint32_t u1OUT1:1;
|
||||
uint32_t u1OUT2:1;
|
||||
uint32_t u1OUT3:1;
|
||||
uint32_t u1OUT4:1;
|
||||
uint32_t u1OUT5:1;
|
||||
uint32_t u1OUT6:1;
|
||||
uint32_t u1OUT7:1;
|
||||
uint32_t :24;
|
||||
} stc_GPIO_PRT_OUT_SET_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_OUT_SET {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_OUT_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_OUT_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Port output data invert register (GPIO_PRT_OUT_INV)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_OUT_INV_field {
|
||||
uint32_t u1OUT0:1;
|
||||
uint32_t u1OUT1:1;
|
||||
uint32_t u1OUT2:1;
|
||||
uint32_t u1OUT3:1;
|
||||
uint32_t u1OUT4:1;
|
||||
uint32_t u1OUT5:1;
|
||||
uint32_t u1OUT6:1;
|
||||
uint32_t u1OUT7:1;
|
||||
uint32_t :24;
|
||||
} stc_GPIO_PRT_OUT_INV_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_OUT_INV {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_OUT_INV_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_OUT_INV_t;
|
||||
|
||||
/**
|
||||
* \brief Port input state register (GPIO_PRT_IN)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_IN_field {
|
||||
uint32_t u1IN0:1;
|
||||
uint32_t u1IN1:1;
|
||||
uint32_t u1IN2:1;
|
||||
uint32_t u1IN3:1;
|
||||
uint32_t u1IN4:1;
|
||||
uint32_t u1IN5:1;
|
||||
uint32_t u1IN6:1;
|
||||
uint32_t u1IN7:1;
|
||||
uint32_t u1FLT_IN:1;
|
||||
uint32_t :23;
|
||||
} stc_GPIO_PRT_IN_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_IN {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_IN_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_IN_t;
|
||||
|
||||
/**
|
||||
* \brief Port interrupt status register (GPIO_PRT_INTR)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_INTR_field {
|
||||
uint32_t u1EDGE0:1;
|
||||
uint32_t u1EDGE1:1;
|
||||
uint32_t u1EDGE2:1;
|
||||
uint32_t u1EDGE3:1;
|
||||
uint32_t u1EDGE4:1;
|
||||
uint32_t u1EDGE5:1;
|
||||
uint32_t u1EDGE6:1;
|
||||
uint32_t u1EDGE7:1;
|
||||
uint32_t u1FLT_EDGE:1;
|
||||
uint32_t :7;
|
||||
uint32_t u1IN_IN0:1;
|
||||
uint32_t u1IN_IN1:1;
|
||||
uint32_t u1IN_IN2:1;
|
||||
uint32_t u1IN_IN3:1;
|
||||
uint32_t u1IN_IN4:1;
|
||||
uint32_t u1IN_IN5:1;
|
||||
uint32_t u1IN_IN6:1;
|
||||
uint32_t u1IN_IN7:1;
|
||||
uint32_t u1FLT_IN_IN:1;
|
||||
uint32_t :7;
|
||||
} stc_GPIO_PRT_INTR_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Port interrupt mask register (GPIO_PRT_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_INTR_MASK_field {
|
||||
uint32_t u1EDGE0:1;
|
||||
uint32_t u1EDGE1:1;
|
||||
uint32_t u1EDGE2:1;
|
||||
uint32_t u1EDGE3:1;
|
||||
uint32_t u1EDGE4:1;
|
||||
uint32_t u1EDGE5:1;
|
||||
uint32_t u1EDGE6:1;
|
||||
uint32_t u1EDGE7:1;
|
||||
uint32_t u1FLT_EDGE:1;
|
||||
uint32_t :23;
|
||||
} stc_GPIO_PRT_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Port interrupt masked status register (GPIO_PRT_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_INTR_MASKED_field {
|
||||
uint32_t u1EDGE0:1;
|
||||
uint32_t u1EDGE1:1;
|
||||
uint32_t u1EDGE2:1;
|
||||
uint32_t u1EDGE3:1;
|
||||
uint32_t u1EDGE4:1;
|
||||
uint32_t u1EDGE5:1;
|
||||
uint32_t u1EDGE6:1;
|
||||
uint32_t u1EDGE7:1;
|
||||
uint32_t u1FLT_EDGE:1;
|
||||
uint32_t :23;
|
||||
} stc_GPIO_PRT_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_INTR_MASKED_t;
|
||||
|
||||
/**
|
||||
* \brief Port interrupt set register (GPIO_PRT_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_INTR_SET_field {
|
||||
uint32_t u1EDGE0:1;
|
||||
uint32_t u1EDGE1:1;
|
||||
uint32_t u1EDGE2:1;
|
||||
uint32_t u1EDGE3:1;
|
||||
uint32_t u1EDGE4:1;
|
||||
uint32_t u1EDGE5:1;
|
||||
uint32_t u1EDGE6:1;
|
||||
uint32_t u1EDGE7:1;
|
||||
uint32_t u1FLT_EDGE:1;
|
||||
uint32_t :23;
|
||||
} stc_GPIO_PRT_INTR_SET_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Port interrupt configuration register (GPIO_PRT_INTR_CFG)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_INTR_CFG_field {
|
||||
uint32_t u2EDGE0_SEL:2;
|
||||
uint32_t u2EDGE1_SEL:2;
|
||||
uint32_t u2EDGE2_SEL:2;
|
||||
uint32_t u2EDGE3_SEL:2;
|
||||
uint32_t u2EDGE4_SEL:2;
|
||||
uint32_t u2EDGE5_SEL:2;
|
||||
uint32_t u2EDGE6_SEL:2;
|
||||
uint32_t u2EDGE7_SEL:2;
|
||||
uint32_t u2FLT_EDGE_SEL:2;
|
||||
uint32_t u3FLT_SEL:3;
|
||||
uint32_t :11;
|
||||
} stc_GPIO_PRT_INTR_CFG_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_INTR_CFG {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_INTR_CFG_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_INTR_CFG_t;
|
||||
|
||||
/**
|
||||
* \brief Port configuration register (GPIO_PRT_CFG)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_CFG_field {
|
||||
uint32_t u3DRIVE_MODE0:3;
|
||||
uint32_t u1IN_EN0:1;
|
||||
uint32_t u3DRIVE_MODE1:3;
|
||||
uint32_t u1IN_EN1:1;
|
||||
uint32_t u3DRIVE_MODE2:3;
|
||||
uint32_t u1IN_EN2:1;
|
||||
uint32_t u3DRIVE_MODE3:3;
|
||||
uint32_t u1IN_EN3:1;
|
||||
uint32_t u3DRIVE_MODE4:3;
|
||||
uint32_t u1IN_EN4:1;
|
||||
uint32_t u3DRIVE_MODE5:3;
|
||||
uint32_t u1IN_EN5:1;
|
||||
uint32_t u3DRIVE_MODE6:3;
|
||||
uint32_t u1IN_EN6:1;
|
||||
uint32_t u3DRIVE_MODE7:3;
|
||||
uint32_t u1IN_EN7:1;
|
||||
} stc_GPIO_PRT_CFG_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_CFG {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_CFG_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_CFG_t;
|
||||
|
||||
/**
|
||||
* \brief Port input buffer configuration register (GPIO_PRT_CFG_IN)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_CFG_IN_field {
|
||||
uint32_t u1VTRIP_SEL0_0:1;
|
||||
uint32_t u1VTRIP_SEL1_0:1;
|
||||
uint32_t u1VTRIP_SEL2_0:1;
|
||||
uint32_t u1VTRIP_SEL3_0:1;
|
||||
uint32_t u1VTRIP_SEL4_0:1;
|
||||
uint32_t u1VTRIP_SEL5_0:1;
|
||||
uint32_t u1VTRIP_SEL6_0:1;
|
||||
uint32_t u1VTRIP_SEL7_0:1;
|
||||
uint32_t :24;
|
||||
} stc_GPIO_PRT_CFG_IN_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_CFG_IN {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_CFG_IN_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_CFG_IN_t;
|
||||
|
||||
/**
|
||||
* \brief Port output buffer configuration register (GPIO_PRT_CFG_OUT)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_CFG_OUT_field {
|
||||
uint32_t u1SLOW0:1;
|
||||
uint32_t u1SLOW1:1;
|
||||
uint32_t u1SLOW2:1;
|
||||
uint32_t u1SLOW3:1;
|
||||
uint32_t u1SLOW4:1;
|
||||
uint32_t u1SLOW5:1;
|
||||
uint32_t u1SLOW6:1;
|
||||
uint32_t u1SLOW7:1;
|
||||
uint32_t :8;
|
||||
uint32_t u2DRIVE_SEL0:2;
|
||||
uint32_t u2DRIVE_SEL1:2;
|
||||
uint32_t u2DRIVE_SEL2:2;
|
||||
uint32_t u2DRIVE_SEL3:2;
|
||||
uint32_t u2DRIVE_SEL4:2;
|
||||
uint32_t u2DRIVE_SEL5:2;
|
||||
uint32_t u2DRIVE_SEL6:2;
|
||||
uint32_t u2DRIVE_SEL7:2;
|
||||
} stc_GPIO_PRT_CFG_OUT_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_CFG_OUT {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_CFG_OUT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_CFG_OUT_t;
|
||||
|
||||
/**
|
||||
* \brief Port SIO configuration register (GPIO_PRT_CFG_SIO)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_CFG_SIO_field {
|
||||
uint32_t u1VREG_EN01:1;
|
||||
uint32_t u1IBUF_SEL01:1;
|
||||
uint32_t u1VTRIP_SEL01:1;
|
||||
uint32_t u2VREF_SEL01:2;
|
||||
uint32_t u3VOH_SEL01:3;
|
||||
uint32_t u1VREG_EN23:1;
|
||||
uint32_t u1IBUF_SEL23:1;
|
||||
uint32_t u1VTRIP_SEL23:1;
|
||||
uint32_t u2VREF_SEL23:2;
|
||||
uint32_t u3VOH_SEL23:3;
|
||||
uint32_t u1VREG_EN45:1;
|
||||
uint32_t u1IBUF_SEL45:1;
|
||||
uint32_t u1VTRIP_SEL45:1;
|
||||
uint32_t u2VREF_SEL45:2;
|
||||
uint32_t u3VOH_SEL45:3;
|
||||
uint32_t u1VREG_EN67:1;
|
||||
uint32_t u1IBUF_SEL67:1;
|
||||
uint32_t u1VTRIP_SEL67:1;
|
||||
uint32_t u2VREF_SEL67:2;
|
||||
uint32_t u3VOH_SEL67:3;
|
||||
} stc_GPIO_PRT_CFG_SIO_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_CFG_SIO {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_CFG_SIO_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_CFG_SIO_t;
|
||||
|
||||
/**
|
||||
* \brief Port input buffer AUTOLVL configuration register for S40E GPIO (GPIO_PRT_CFG_IN_AUTOLVL)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT_CFG_IN_AUTOLVL_field {
|
||||
uint32_t u1VTRIP_SEL0_1:1;
|
||||
uint32_t u1VTRIP_SEL1_1:1;
|
||||
uint32_t u1VTRIP_SEL2_1:1;
|
||||
uint32_t u1VTRIP_SEL3_1:1;
|
||||
uint32_t u1VTRIP_SEL4_1:1;
|
||||
uint32_t u1VTRIP_SEL5_1:1;
|
||||
uint32_t u1VTRIP_SEL6_1:1;
|
||||
uint32_t u1VTRIP_SEL7_1:1;
|
||||
uint32_t :24;
|
||||
} stc_GPIO_PRT_CFG_IN_AUTOLVL_field_t;
|
||||
|
||||
typedef union un_GPIO_PRT_CFG_IN_AUTOLVL {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_PRT_CFG_IN_AUTOLVL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_PRT_CFG_IN_AUTOLVL_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Interrupt port cause register 0 (GPIO_INTR_CAUSE0)
|
||||
*/
|
||||
typedef struct stc_GPIO_INTR_CAUSE0_field {
|
||||
uint32_t u32PORT_INT:32;
|
||||
} stc_GPIO_INTR_CAUSE0_field_t;
|
||||
|
||||
typedef union un_GPIO_INTR_CAUSE0 {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_INTR_CAUSE0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_INTR_CAUSE0_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt port cause register 1 (GPIO_INTR_CAUSE1)
|
||||
*/
|
||||
typedef struct stc_GPIO_INTR_CAUSE1_field {
|
||||
uint32_t u32PORT_INT:32;
|
||||
} stc_GPIO_INTR_CAUSE1_field_t;
|
||||
|
||||
typedef union un_GPIO_INTR_CAUSE1 {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_INTR_CAUSE1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_INTR_CAUSE1_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt port cause register 2 (GPIO_INTR_CAUSE2)
|
||||
*/
|
||||
typedef struct stc_GPIO_INTR_CAUSE2_field {
|
||||
uint32_t u32PORT_INT:32;
|
||||
} stc_GPIO_INTR_CAUSE2_field_t;
|
||||
|
||||
typedef union un_GPIO_INTR_CAUSE2 {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_INTR_CAUSE2_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_INTR_CAUSE2_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt port cause register 3 (GPIO_INTR_CAUSE3)
|
||||
*/
|
||||
typedef struct stc_GPIO_INTR_CAUSE3_field {
|
||||
uint32_t u32PORT_INT:32;
|
||||
} stc_GPIO_INTR_CAUSE3_field_t;
|
||||
|
||||
typedef union un_GPIO_INTR_CAUSE3 {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_INTR_CAUSE3_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_INTR_CAUSE3_t;
|
||||
|
||||
/**
|
||||
* \brief Extern power supply detection register (GPIO_VDD_ACTIVE)
|
||||
*/
|
||||
typedef struct stc_GPIO_VDD_ACTIVE_field {
|
||||
uint32_t u16VDDIO_ACTIVE:16;
|
||||
uint32_t :14;
|
||||
uint32_t u1VDDA_ACTIVE:1;
|
||||
uint32_t u1VDDD_ACTIVE:1;
|
||||
} stc_GPIO_VDD_ACTIVE_field_t;
|
||||
|
||||
typedef union un_GPIO_VDD_ACTIVE {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_VDD_ACTIVE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_VDD_ACTIVE_t;
|
||||
|
||||
/**
|
||||
* \brief Supply detection interrupt register (GPIO_VDD_INTR)
|
||||
*/
|
||||
typedef struct stc_GPIO_VDD_INTR_field {
|
||||
uint32_t u16VDDIO_ACTIVE:16;
|
||||
uint32_t :14;
|
||||
uint32_t u1VDDA_ACTIVE:1;
|
||||
uint32_t u1VDDD_ACTIVE:1;
|
||||
} stc_GPIO_VDD_INTR_field_t;
|
||||
|
||||
typedef union un_GPIO_VDD_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_VDD_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_VDD_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Supply detection interrupt mask register (GPIO_VDD_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_GPIO_VDD_INTR_MASK_field {
|
||||
uint32_t u16VDDIO_ACTIVE:16;
|
||||
uint32_t :14;
|
||||
uint32_t u1VDDA_ACTIVE:1;
|
||||
uint32_t u1VDDD_ACTIVE:1;
|
||||
} stc_GPIO_VDD_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_GPIO_VDD_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_VDD_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_VDD_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Supply detection interrupt masked register (GPIO_VDD_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_GPIO_VDD_INTR_MASKED_field {
|
||||
uint32_t u16VDDIO_ACTIVE:16;
|
||||
uint32_t :14;
|
||||
uint32_t u1VDDA_ACTIVE:1;
|
||||
uint32_t u1VDDD_ACTIVE:1;
|
||||
} stc_GPIO_VDD_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_GPIO_VDD_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_VDD_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_VDD_INTR_MASKED_t;
|
||||
|
||||
/**
|
||||
* \brief Supply detection interrupt set register (GPIO_VDD_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_GPIO_VDD_INTR_SET_field {
|
||||
uint32_t u16VDDIO_ACTIVE:16;
|
||||
uint32_t :14;
|
||||
uint32_t u1VDDA_ACTIVE:1;
|
||||
uint32_t u1VDDD_ACTIVE:1;
|
||||
} stc_GPIO_VDD_INTR_SET_field_t;
|
||||
|
||||
typedef union un_GPIO_VDD_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_GPIO_VDD_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_GPIO_VDD_INTR_SET_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT)
|
||||
*/
|
||||
typedef struct stc_GPIO_PRT {
|
||||
un_GPIO_PRT_OUT_t unOUT; /*!< 0x00000000 Port output data register */
|
||||
un_GPIO_PRT_OUT_CLR_t unOUT_CLR; /*!< 0x00000004 Port output data clear register */
|
||||
un_GPIO_PRT_OUT_SET_t unOUT_SET; /*!< 0x00000008 Port output data set register */
|
||||
un_GPIO_PRT_OUT_INV_t unOUT_INV; /*!< 0x0000000C Port output data invert register */
|
||||
un_GPIO_PRT_IN_t unIN; /*!< 0x00000010 Port input state register */
|
||||
un_GPIO_PRT_INTR_t unINTR; /*!< 0x00000014 Port interrupt status register */
|
||||
un_GPIO_PRT_INTR_MASK_t unINTR_MASK; /*!< 0x00000018 Port interrupt mask register */
|
||||
un_GPIO_PRT_INTR_MASKED_t unINTR_MASKED; /*!< 0x0000001C Port interrupt masked status register */
|
||||
un_GPIO_PRT_INTR_SET_t unINTR_SET; /*!< 0x00000020 Port interrupt set register */
|
||||
uint32_t au32Reserved[7];
|
||||
un_GPIO_PRT_INTR_CFG_t unINTR_CFG; /*!< 0x00000040 Port interrupt configuration register */
|
||||
un_GPIO_PRT_CFG_t unCFG; /*!< 0x00000044 Port configuration register */
|
||||
un_GPIO_PRT_CFG_IN_t unCFG_IN; /*!< 0x00000048 Port input buffer configuration register */
|
||||
un_GPIO_PRT_CFG_OUT_t unCFG_OUT; /*!< 0x0000004C Port output buffer configuration register */
|
||||
un_GPIO_PRT_CFG_SIO_t unCFG_SIO; /*!< 0x00000050 Port SIO configuration register */
|
||||
uint32_t u32Reserved1;
|
||||
un_GPIO_PRT_CFG_IN_AUTOLVL_t unCFG_IN_AUTOLVL; /*!< 0x00000058 Port input buffer AUTOLVL configuration register for
|
||||
S40E GPIO */
|
||||
uint32_t au32Reserved2[9];
|
||||
} stc_GPIO_PRT_t; /*!< Size = 128 (0x80) */
|
||||
|
||||
/**
|
||||
* \brief GPIO port control/configuration (GPIO)
|
||||
*/
|
||||
typedef struct stc_GPIO {
|
||||
stc_GPIO_PRT_t PRT[128]; /*!< 0x00000000 GPIO port registers */
|
||||
un_GPIO_INTR_CAUSE0_t unINTR_CAUSE0; /*!< 0x00004000 Interrupt port cause register 0 */
|
||||
un_GPIO_INTR_CAUSE1_t unINTR_CAUSE1; /*!< 0x00004004 Interrupt port cause register 1 */
|
||||
un_GPIO_INTR_CAUSE2_t unINTR_CAUSE2; /*!< 0x00004008 Interrupt port cause register 2 */
|
||||
un_GPIO_INTR_CAUSE3_t unINTR_CAUSE3; /*!< 0x0000400C Interrupt port cause register 3 */
|
||||
un_GPIO_VDD_ACTIVE_t unVDD_ACTIVE; /*!< 0x00004010 Extern power supply detection register */
|
||||
un_GPIO_VDD_INTR_t unVDD_INTR; /*!< 0x00004014 Supply detection interrupt register */
|
||||
un_GPIO_VDD_INTR_MASK_t unVDD_INTR_MASK; /*!< 0x00004018 Supply detection interrupt mask register */
|
||||
un_GPIO_VDD_INTR_MASKED_t unVDD_INTR_MASKED; /*!< 0x0000401C Supply detection interrupt masked register */
|
||||
un_GPIO_VDD_INTR_SET_t unVDD_INTR_SET; /*!< 0x00004020 Supply detection interrupt set register */
|
||||
} stc_GPIO_t; /*!< Size = 16420 (0x4024) */
|
||||
|
||||
|
||||
/* GPIO_PRT.OUT */
|
||||
#define GPIO_PRT_OUT_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_OUT_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_OUT_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_OUT_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_OUT_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_OUT_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_OUT_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_OUT_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_OUT_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_OUT_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_OUT_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_OUT_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_OUT_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_OUT_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_OUT_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_OUT_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.OUT_CLR */
|
||||
#define GPIO_PRT_OUT_CLR_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.OUT_SET */
|
||||
#define GPIO_PRT_OUT_SET_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_OUT_SET_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_OUT_SET_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_OUT_SET_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_OUT_SET_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_OUT_SET_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_OUT_SET_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_OUT_SET_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_OUT_SET_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_OUT_SET_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_OUT_SET_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_OUT_SET_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_OUT_SET_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_OUT_SET_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_OUT_SET_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_OUT_SET_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.OUT_INV */
|
||||
#define GPIO_PRT_OUT_INV_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_OUT_INV_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_OUT_INV_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_OUT_INV_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_OUT_INV_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_OUT_INV_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_OUT_INV_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_OUT_INV_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_OUT_INV_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_OUT_INV_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_OUT_INV_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_OUT_INV_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_OUT_INV_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_OUT_INV_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_OUT_INV_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_OUT_INV_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.IN */
|
||||
#define GPIO_PRT_IN_IN0_Pos 0UL
|
||||
#define GPIO_PRT_IN_IN0_Msk 0x1UL
|
||||
#define GPIO_PRT_IN_IN1_Pos 1UL
|
||||
#define GPIO_PRT_IN_IN1_Msk 0x2UL
|
||||
#define GPIO_PRT_IN_IN2_Pos 2UL
|
||||
#define GPIO_PRT_IN_IN2_Msk 0x4UL
|
||||
#define GPIO_PRT_IN_IN3_Pos 3UL
|
||||
#define GPIO_PRT_IN_IN3_Msk 0x8UL
|
||||
#define GPIO_PRT_IN_IN4_Pos 4UL
|
||||
#define GPIO_PRT_IN_IN4_Msk 0x10UL
|
||||
#define GPIO_PRT_IN_IN5_Pos 5UL
|
||||
#define GPIO_PRT_IN_IN5_Msk 0x20UL
|
||||
#define GPIO_PRT_IN_IN6_Pos 6UL
|
||||
#define GPIO_PRT_IN_IN6_Msk 0x40UL
|
||||
#define GPIO_PRT_IN_IN7_Pos 7UL
|
||||
#define GPIO_PRT_IN_IN7_Msk 0x80UL
|
||||
#define GPIO_PRT_IN_FLT_IN_Pos 8UL
|
||||
#define GPIO_PRT_IN_FLT_IN_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR */
|
||||
#define GPIO_PRT_INTR_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_INTR_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_INTR_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_INTR_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_INTR_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_INTR_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_INTR_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_INTR_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_INTR_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_INTR_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_INTR_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_INTR_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_INTR_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_INTR_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_INTR_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_INTR_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_INTR_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_INTR_FLT_EDGE_Msk 0x100UL
|
||||
#define GPIO_PRT_INTR_IN_IN0_Pos 16UL
|
||||
#define GPIO_PRT_INTR_IN_IN0_Msk 0x10000UL
|
||||
#define GPIO_PRT_INTR_IN_IN1_Pos 17UL
|
||||
#define GPIO_PRT_INTR_IN_IN1_Msk 0x20000UL
|
||||
#define GPIO_PRT_INTR_IN_IN2_Pos 18UL
|
||||
#define GPIO_PRT_INTR_IN_IN2_Msk 0x40000UL
|
||||
#define GPIO_PRT_INTR_IN_IN3_Pos 19UL
|
||||
#define GPIO_PRT_INTR_IN_IN3_Msk 0x80000UL
|
||||
#define GPIO_PRT_INTR_IN_IN4_Pos 20UL
|
||||
#define GPIO_PRT_INTR_IN_IN4_Msk 0x100000UL
|
||||
#define GPIO_PRT_INTR_IN_IN5_Pos 21UL
|
||||
#define GPIO_PRT_INTR_IN_IN5_Msk 0x200000UL
|
||||
#define GPIO_PRT_INTR_IN_IN6_Pos 22UL
|
||||
#define GPIO_PRT_INTR_IN_IN6_Msk 0x400000UL
|
||||
#define GPIO_PRT_INTR_IN_IN7_Pos 23UL
|
||||
#define GPIO_PRT_INTR_IN_IN7_Msk 0x800000UL
|
||||
#define GPIO_PRT_INTR_FLT_IN_IN_Pos 24UL
|
||||
#define GPIO_PRT_INTR_FLT_IN_IN_Msk 0x1000000UL
|
||||
/* GPIO_PRT.INTR_MASK */
|
||||
#define GPIO_PRT_INTR_MASK_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_INTR_MASK_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_INTR_MASK_FLT_EDGE_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR_MASKED */
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_INTR_MASKED_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_INTR_MASKED_FLT_EDGE_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR_SET */
|
||||
#define GPIO_PRT_INTR_SET_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_INTR_SET_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_INTR_SET_FLT_EDGE_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR_CFG */
|
||||
#define GPIO_PRT_INTR_CFG_EDGE0_SEL_Pos 0UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk 0x3UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE1_SEL_Pos 2UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk 0xCUL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE2_SEL_Pos 4UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk 0x30UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE3_SEL_Pos 6UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk 0xC0UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE4_SEL_Pos 8UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk 0x300UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE5_SEL_Pos 10UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk 0xC00UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE6_SEL_Pos 12UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk 0x3000UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE7_SEL_Pos 14UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk 0xC000UL
|
||||
#define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Pos 16UL
|
||||
#define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk 0x30000UL
|
||||
#define GPIO_PRT_INTR_CFG_FLT_SEL_Pos 18UL
|
||||
#define GPIO_PRT_INTR_CFG_FLT_SEL_Msk 0x1C0000UL
|
||||
/* GPIO_PRT.CFG */
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE0_Pos 0UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE0_Msk 0x7UL
|
||||
#define GPIO_PRT_CFG_IN_EN0_Pos 3UL
|
||||
#define GPIO_PRT_CFG_IN_EN0_Msk 0x8UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE1_Pos 4UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE1_Msk 0x70UL
|
||||
#define GPIO_PRT_CFG_IN_EN1_Pos 7UL
|
||||
#define GPIO_PRT_CFG_IN_EN1_Msk 0x80UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE2_Pos 8UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE2_Msk 0x700UL
|
||||
#define GPIO_PRT_CFG_IN_EN2_Pos 11UL
|
||||
#define GPIO_PRT_CFG_IN_EN2_Msk 0x800UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE3_Pos 12UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE3_Msk 0x7000UL
|
||||
#define GPIO_PRT_CFG_IN_EN3_Pos 15UL
|
||||
#define GPIO_PRT_CFG_IN_EN3_Msk 0x8000UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE4_Pos 16UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE4_Msk 0x70000UL
|
||||
#define GPIO_PRT_CFG_IN_EN4_Pos 19UL
|
||||
#define GPIO_PRT_CFG_IN_EN4_Msk 0x80000UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE5_Pos 20UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE5_Msk 0x700000UL
|
||||
#define GPIO_PRT_CFG_IN_EN5_Pos 23UL
|
||||
#define GPIO_PRT_CFG_IN_EN5_Msk 0x800000UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE6_Pos 24UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE6_Msk 0x7000000UL
|
||||
#define GPIO_PRT_CFG_IN_EN6_Pos 27UL
|
||||
#define GPIO_PRT_CFG_IN_EN6_Msk 0x8000000UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE7_Pos 28UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE7_Msk 0x70000000UL
|
||||
#define GPIO_PRT_CFG_IN_EN7_Pos 31UL
|
||||
#define GPIO_PRT_CFG_IN_EN7_Msk 0x80000000UL
|
||||
/* GPIO_PRT.CFG_IN */
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Pos 0UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Msk 0x1UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Pos 1UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Msk 0x2UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Pos 2UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Msk 0x4UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Pos 3UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Msk 0x8UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Pos 4UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Msk 0x10UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Pos 5UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Msk 0x20UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Pos 6UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Msk 0x40UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Pos 7UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Msk 0x80UL
|
||||
/* GPIO_PRT.CFG_OUT */
|
||||
#define GPIO_PRT_CFG_OUT_SLOW0_Pos 0UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW0_Msk 0x1UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW1_Pos 1UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW1_Msk 0x2UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW2_Pos 2UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW2_Msk 0x4UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW3_Pos 3UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW3_Msk 0x8UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW4_Pos 4UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW4_Msk 0x10UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW5_Pos 5UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW5_Msk 0x20UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW6_Pos 6UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW6_Msk 0x40UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW7_Pos 7UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW7_Msk 0x80UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Pos 16UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Msk 0x30000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Pos 18UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Msk 0xC0000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Pos 20UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Msk 0x300000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Pos 22UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Msk 0xC00000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Pos 24UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Msk 0x3000000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Pos 26UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Msk 0xC000000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Pos 28UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Msk 0x30000000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Pos 30UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Msk 0xC0000000UL
|
||||
/* GPIO_PRT.CFG_SIO */
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN01_Pos 0UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN01_Msk 0x1UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL01_Pos 1UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL01_Msk 0x2UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Pos 2UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Msk 0x4UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL01_Pos 3UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL01_Msk 0x18UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL01_Pos 5UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL01_Msk 0xE0UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN23_Pos 8UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN23_Msk 0x100UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL23_Pos 9UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL23_Msk 0x200UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Pos 10UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Msk 0x400UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL23_Pos 11UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL23_Msk 0x1800UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL23_Pos 13UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL23_Msk 0xE000UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN45_Pos 16UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN45_Msk 0x10000UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL45_Pos 17UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL45_Msk 0x20000UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Pos 18UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Msk 0x40000UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL45_Pos 19UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL45_Msk 0x180000UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL45_Pos 21UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL45_Msk 0xE00000UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN67_Pos 24UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN67_Msk 0x1000000UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL67_Pos 25UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL67_Msk 0x2000000UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Pos 26UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Msk 0x4000000UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL67_Pos 27UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL67_Msk 0x18000000UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL67_Pos 29UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL67_Msk 0xE0000000UL
|
||||
/* GPIO_PRT.CFG_IN_AUTOLVL */
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Pos 0UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Msk 0x1UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Pos 1UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Msk 0x2UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Pos 2UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Msk 0x4UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Pos 3UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Msk 0x8UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Pos 4UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Msk 0x10UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Pos 5UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Msk 0x20UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Pos 6UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Msk 0x40UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Pos 7UL
|
||||
#define GPIO_PRT_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Msk 0x80UL
|
||||
|
||||
|
||||
/* GPIO.INTR_CAUSE0 */
|
||||
#define GPIO_INTR_CAUSE0_PORT_INT_Pos 0UL
|
||||
#define GPIO_INTR_CAUSE0_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.INTR_CAUSE1 */
|
||||
#define GPIO_INTR_CAUSE1_PORT_INT_Pos 0UL
|
||||
#define GPIO_INTR_CAUSE1_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.INTR_CAUSE2 */
|
||||
#define GPIO_INTR_CAUSE2_PORT_INT_Pos 0UL
|
||||
#define GPIO_INTR_CAUSE2_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.INTR_CAUSE3 */
|
||||
#define GPIO_INTR_CAUSE3_PORT_INT_Pos 0UL
|
||||
#define GPIO_INTR_CAUSE3_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.VDD_ACTIVE */
|
||||
#define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR */
|
||||
#define GPIO_VDD_INTR_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_VDD_INTR_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_VDD_INTR_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_VDD_INTR_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_VDD_INTR_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_VDD_INTR_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR_MASK */
|
||||
#define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR_MASKED */
|
||||
#define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR_SET */
|
||||
#define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_GPIO_V3_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,32 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_headers.h
|
||||
*
|
||||
* \brief
|
||||
* Common header file to be included by all IP definition headers
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_HEADERS_H_
|
||||
#define _CYIP_HEADERS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
|
||||
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
|
||||
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
|
||||
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
|
||||
#include "core_cm0plus.h"
|
||||
#else
|
||||
#include "core_cm7.h"
|
||||
#endif
|
||||
|
||||
#endif /* _CYIP_HEADERS_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,248 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_hsiom_v3.h
|
||||
*
|
||||
* \brief
|
||||
* HSIOM IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_HSIOM_V3_H_
|
||||
#define _CYIP_HSIOM_V3_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_PRT_SECTION_SIZE 0x00000010UL
|
||||
#define HSIOM_SECTION_SIZE 0x00004000UL
|
||||
|
||||
/**
|
||||
* \brief Port selection 0 (HSIOM_PRT_PORT_SEL0)
|
||||
*/
|
||||
typedef struct stc_HSIOM_PRT_PORT_SEL0_field {
|
||||
uint32_t u5IO0_SEL:5;
|
||||
uint32_t :3;
|
||||
uint32_t u5IO1_SEL:5;
|
||||
uint32_t :3;
|
||||
uint32_t u5IO2_SEL:5;
|
||||
uint32_t :3;
|
||||
uint32_t u5IO3_SEL:5;
|
||||
uint32_t :3;
|
||||
} stc_HSIOM_PRT_PORT_SEL0_field_t;
|
||||
|
||||
typedef union un_HSIOM_PRT_PORT_SEL0 {
|
||||
uint32_t u32Register;
|
||||
stc_HSIOM_PRT_PORT_SEL0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_HSIOM_PRT_PORT_SEL0_t;
|
||||
|
||||
/**
|
||||
* \brief Port selection 1 (HSIOM_PRT_PORT_SEL1)
|
||||
*/
|
||||
typedef struct stc_HSIOM_PRT_PORT_SEL1_field {
|
||||
uint32_t u5IO4_SEL:5;
|
||||
uint32_t :3;
|
||||
uint32_t u5IO5_SEL:5;
|
||||
uint32_t :3;
|
||||
uint32_t u5IO6_SEL:5;
|
||||
uint32_t :3;
|
||||
uint32_t u5IO7_SEL:5;
|
||||
uint32_t :3;
|
||||
} stc_HSIOM_PRT_PORT_SEL1_field_t;
|
||||
|
||||
typedef union un_HSIOM_PRT_PORT_SEL1 {
|
||||
uint32_t u32Register;
|
||||
stc_HSIOM_PRT_PORT_SEL1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_HSIOM_PRT_PORT_SEL1_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief AMUX splitter cell control (HSIOM_AMUX_SPLIT_CTL)
|
||||
*/
|
||||
typedef struct stc_HSIOM_AMUX_SPLIT_CTL_field {
|
||||
uint32_t u1SWITCH_AA_SL:1;
|
||||
uint32_t u1SWITCH_AA_SR:1;
|
||||
uint32_t u1SWITCH_AA_S0:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1SWITCH_BB_SL:1;
|
||||
uint32_t u1SWITCH_BB_SR:1;
|
||||
uint32_t u1SWITCH_BB_S0:1;
|
||||
uint32_t :25;
|
||||
} stc_HSIOM_AMUX_SPLIT_CTL_field_t;
|
||||
|
||||
typedef union un_HSIOM_AMUX_SPLIT_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_HSIOM_AMUX_SPLIT_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_HSIOM_AMUX_SPLIT_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Power/Ground Monitor cell control 0 (HSIOM_MONITOR_CTL_0)
|
||||
*/
|
||||
typedef struct stc_HSIOM_MONITOR_CTL_0_field {
|
||||
uint32_t u32MONITOR_EN:32;
|
||||
} stc_HSIOM_MONITOR_CTL_0_field_t;
|
||||
|
||||
typedef union un_HSIOM_MONITOR_CTL_0 {
|
||||
uint32_t u32Register;
|
||||
stc_HSIOM_MONITOR_CTL_0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_HSIOM_MONITOR_CTL_0_t;
|
||||
|
||||
/**
|
||||
* \brief Power/Ground Monitor cell control 1 (HSIOM_MONITOR_CTL_1)
|
||||
*/
|
||||
typedef struct stc_HSIOM_MONITOR_CTL_1_field {
|
||||
uint32_t u32MONITOR_EN:32;
|
||||
} stc_HSIOM_MONITOR_CTL_1_field_t;
|
||||
|
||||
typedef union un_HSIOM_MONITOR_CTL_1 {
|
||||
uint32_t u32Register;
|
||||
stc_HSIOM_MONITOR_CTL_1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_HSIOM_MONITOR_CTL_1_t;
|
||||
|
||||
/**
|
||||
* \brief Power/Ground Monitor cell control 2 (HSIOM_MONITOR_CTL_2)
|
||||
*/
|
||||
typedef struct stc_HSIOM_MONITOR_CTL_2_field {
|
||||
uint32_t u32MONITOR_EN:32;
|
||||
} stc_HSIOM_MONITOR_CTL_2_field_t;
|
||||
|
||||
typedef union un_HSIOM_MONITOR_CTL_2 {
|
||||
uint32_t u32Register;
|
||||
stc_HSIOM_MONITOR_CTL_2_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_HSIOM_MONITOR_CTL_2_t;
|
||||
|
||||
/**
|
||||
* \brief Power/Ground Monitor cell control 3 (HSIOM_MONITOR_CTL_3)
|
||||
*/
|
||||
typedef struct stc_HSIOM_MONITOR_CTL_3_field {
|
||||
uint32_t u32MONITOR_EN:32;
|
||||
} stc_HSIOM_MONITOR_CTL_3_field_t;
|
||||
|
||||
typedef union un_HSIOM_MONITOR_CTL_3 {
|
||||
uint32_t u32Register;
|
||||
stc_HSIOM_MONITOR_CTL_3_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_HSIOM_MONITOR_CTL_3_t;
|
||||
|
||||
/**
|
||||
* \brief Alternate JTAG IF selection register (HSIOM_ALT_JTAG_EN)
|
||||
*/
|
||||
typedef struct stc_HSIOM_ALT_JTAG_EN_field {
|
||||
uint32_t :31;
|
||||
uint32_t u1ENABLE:1;
|
||||
} stc_HSIOM_ALT_JTAG_EN_field_t;
|
||||
|
||||
typedef union un_HSIOM_ALT_JTAG_EN {
|
||||
uint32_t u32Register;
|
||||
stc_HSIOM_ALT_JTAG_EN_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_HSIOM_ALT_JTAG_EN_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT)
|
||||
*/
|
||||
typedef struct stc_HSIOM_PRT {
|
||||
un_HSIOM_PRT_PORT_SEL0_t unPORT_SEL0; /*!< 0x00000000 Port selection 0 */
|
||||
un_HSIOM_PRT_PORT_SEL1_t unPORT_SEL1; /*!< 0x00000004 Port selection 1 */
|
||||
uint32_t au32Reserved[2];
|
||||
} stc_HSIOM_PRT_t; /*!< Size = 16 (0x10) */
|
||||
|
||||
/**
|
||||
* \brief High Speed IO Matrix (HSIOM) (HSIOM)
|
||||
*/
|
||||
typedef struct stc_HSIOM {
|
||||
stc_HSIOM_PRT_t PRT[128]; /*!< 0x00000000 HSIOM port registers */
|
||||
uint32_t au32Reserved[1536];
|
||||
un_HSIOM_AMUX_SPLIT_CTL_t unAMUX_SPLIT_CTL[64]; /*!< 0x00002000 AMUX splitter cell control */
|
||||
uint32_t au32Reserved1[64];
|
||||
un_HSIOM_MONITOR_CTL_0_t unMONITOR_CTL_0; /*!< 0x00002200 Power/Ground Monitor cell control 0 */
|
||||
un_HSIOM_MONITOR_CTL_1_t unMONITOR_CTL_1; /*!< 0x00002204 Power/Ground Monitor cell control 1 */
|
||||
un_HSIOM_MONITOR_CTL_2_t unMONITOR_CTL_2; /*!< 0x00002208 Power/Ground Monitor cell control 2 */
|
||||
un_HSIOM_MONITOR_CTL_3_t unMONITOR_CTL_3; /*!< 0x0000220C Power/Ground Monitor cell control 3 */
|
||||
uint32_t au32Reserved2[12];
|
||||
un_HSIOM_ALT_JTAG_EN_t unALT_JTAG_EN; /*!< 0x00002240 Alternate JTAG IF selection register */
|
||||
} stc_HSIOM_t; /*!< Size = 8772 (0x2244) */
|
||||
|
||||
|
||||
/* HSIOM_PRT.PORT_SEL0 */
|
||||
#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Pos 0UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Msk 0x1FUL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Pos 8UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Msk 0x1F00UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Pos 16UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Msk 0x1F0000UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Pos 24UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Msk 0x1F000000UL
|
||||
/* HSIOM_PRT.PORT_SEL1 */
|
||||
#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Pos 0UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Msk 0x1FUL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Pos 8UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Msk 0x1F00UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Pos 16UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Msk 0x1F0000UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Pos 24UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Msk 0x1F000000UL
|
||||
|
||||
|
||||
/* HSIOM.AMUX_SPLIT_CTL */
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos 0UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk 0x1UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos 1UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk 0x2UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos 2UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk 0x4UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos 4UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk 0x10UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos 5UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk 0x20UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos 6UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk 0x40UL
|
||||
/* HSIOM.MONITOR_CTL_0 */
|
||||
#define HSIOM_MONITOR_CTL_0_MONITOR_EN_Pos 0UL
|
||||
#define HSIOM_MONITOR_CTL_0_MONITOR_EN_Msk 0xFFFFFFFFUL
|
||||
/* HSIOM.MONITOR_CTL_1 */
|
||||
#define HSIOM_MONITOR_CTL_1_MONITOR_EN_Pos 0UL
|
||||
#define HSIOM_MONITOR_CTL_1_MONITOR_EN_Msk 0xFFFFFFFFUL
|
||||
/* HSIOM.MONITOR_CTL_2 */
|
||||
#define HSIOM_MONITOR_CTL_2_MONITOR_EN_Pos 0UL
|
||||
#define HSIOM_MONITOR_CTL_2_MONITOR_EN_Msk 0xFFFFFFFFUL
|
||||
/* HSIOM.MONITOR_CTL_3 */
|
||||
#define HSIOM_MONITOR_CTL_3_MONITOR_EN_Pos 0UL
|
||||
#define HSIOM_MONITOR_CTL_3_MONITOR_EN_Msk 0xFFFFFFFFUL
|
||||
/* HSIOM.ALT_JTAG_EN */
|
||||
#define HSIOM_ALT_JTAG_EN_ENABLE_Pos 31UL
|
||||
#define HSIOM_ALT_JTAG_EN_ENABLE_Msk 0x80000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_HSIOM_V3_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,705 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_i2s_v2.h
|
||||
*
|
||||
* \brief
|
||||
* I2S IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_I2S_V2_H_
|
||||
#define _CYIP_I2S_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S_SECTION_SIZE 0x00001000UL
|
||||
|
||||
/**
|
||||
* \brief Control (I2S_CTL)
|
||||
*/
|
||||
typedef struct stc_I2S_CTL_field {
|
||||
uint32_t :30;
|
||||
uint32_t u1TX_ENABLED:1;
|
||||
uint32_t u1RX_ENABLED:1;
|
||||
} stc_I2S_CTL_field_t;
|
||||
|
||||
typedef union un_I2S_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Clock control (I2S_CLOCK_CTL)
|
||||
*/
|
||||
typedef struct stc_I2S_CLOCK_CTL_field {
|
||||
uint32_t u6CLOCK_DIV:6;
|
||||
uint32_t :2;
|
||||
uint32_t u1CLOCK_SEL:1;
|
||||
uint32_t :3;
|
||||
uint32_t u2MCLK_DIV:2;
|
||||
uint32_t :2;
|
||||
uint32_t u1MCLK_EN:1;
|
||||
uint32_t :15;
|
||||
} stc_I2S_CLOCK_CTL_field_t;
|
||||
|
||||
typedef union un_I2S_CLOCK_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_CLOCK_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_CLOCK_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Clock Status (I2S_CLOCK_STAT)
|
||||
*/
|
||||
typedef struct stc_I2S_CLOCK_STAT_field {
|
||||
uint32_t u1MCLK_DIV_OFF:1;
|
||||
uint32_t :31;
|
||||
} stc_I2S_CLOCK_STAT_field_t;
|
||||
|
||||
typedef union un_I2S_CLOCK_STAT {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_CLOCK_STAT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_CLOCK_STAT_t;
|
||||
|
||||
/**
|
||||
* \brief Command (I2S_CMD)
|
||||
*/
|
||||
typedef struct stc_I2S_CMD_field {
|
||||
uint32_t u1TX_START:1;
|
||||
uint32_t :7;
|
||||
uint32_t u1TX_PAUSE:1;
|
||||
uint32_t :7;
|
||||
uint32_t u1RX_START:1;
|
||||
uint32_t :15;
|
||||
} stc_I2S_CMD_field_t;
|
||||
|
||||
typedef union un_I2S_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_CMD_t;
|
||||
|
||||
/**
|
||||
* \brief Trigger control (I2S_TR_CTL)
|
||||
*/
|
||||
typedef struct stc_I2S_TR_CTL_field {
|
||||
uint32_t u1TX_REQ_EN:1;
|
||||
uint32_t :15;
|
||||
uint32_t u1RX_REQ_EN:1;
|
||||
uint32_t :15;
|
||||
} stc_I2S_TR_CTL_field_t;
|
||||
|
||||
typedef union un_I2S_TR_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_TR_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_TR_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Transmitter control (I2S_TX_CTL)
|
||||
*/
|
||||
typedef struct stc_I2S_TX_CTL_field {
|
||||
uint32_t :3;
|
||||
uint32_t u1B_CLOCK_INV:1;
|
||||
uint32_t u3CH_NR:3;
|
||||
uint32_t u1MS:1;
|
||||
uint32_t u2I2S_MODE:2;
|
||||
uint32_t u1WS_PULSE:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1OVHDATA:1;
|
||||
uint32_t u1WD_EN:1;
|
||||
uint32_t :2;
|
||||
uint32_t u3CH_LEN:3;
|
||||
uint32_t :1;
|
||||
uint32_t u3WORD_LEN:3;
|
||||
uint32_t :1;
|
||||
uint32_t u1SCKO_POL:1;
|
||||
uint32_t u1SCKI_POL:1;
|
||||
uint32_t :6;
|
||||
} stc_I2S_TX_CTL_field_t;
|
||||
|
||||
typedef union un_I2S_TX_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_TX_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_TX_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Transmitter watchdog (I2S_TX_WATCHDOG)
|
||||
*/
|
||||
typedef struct stc_I2S_TX_WATCHDOG_field {
|
||||
uint32_t u32WD_COUNTER:32;
|
||||
} stc_I2S_TX_WATCHDOG_field_t;
|
||||
|
||||
typedef union un_I2S_TX_WATCHDOG {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_TX_WATCHDOG_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_TX_WATCHDOG_t;
|
||||
|
||||
/**
|
||||
* \brief Receiver control (I2S_RX_CTL)
|
||||
*/
|
||||
typedef struct stc_I2S_RX_CTL_field {
|
||||
uint32_t :3;
|
||||
uint32_t u1B_CLOCK_INV:1;
|
||||
uint32_t u3CH_NR:3;
|
||||
uint32_t u1MS:1;
|
||||
uint32_t u2I2S_MODE:2;
|
||||
uint32_t u1WS_PULSE:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1WD_EN:1;
|
||||
uint32_t :2;
|
||||
uint32_t u3CH_LEN:3;
|
||||
uint32_t :1;
|
||||
uint32_t u3WORD_LEN:3;
|
||||
uint32_t u1BIT_EXTENSION:1;
|
||||
uint32_t u1SCKO_POL:1;
|
||||
uint32_t u1SCKI_POL:1;
|
||||
uint32_t :6;
|
||||
} stc_I2S_RX_CTL_field_t;
|
||||
|
||||
typedef union un_I2S_RX_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_RX_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_RX_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Receiver watchdog (I2S_RX_WATCHDOG)
|
||||
*/
|
||||
typedef struct stc_I2S_RX_WATCHDOG_field {
|
||||
uint32_t u32WD_COUNTER:32;
|
||||
} stc_I2S_RX_WATCHDOG_field_t;
|
||||
|
||||
typedef union un_I2S_RX_WATCHDOG {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_RX_WATCHDOG_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_RX_WATCHDOG_t;
|
||||
|
||||
/**
|
||||
* \brief TX FIFO control (I2S_TX_FIFO_CTL)
|
||||
*/
|
||||
typedef struct stc_I2S_TX_FIFO_CTL_field {
|
||||
uint32_t u8TRIGGER_LEVEL:8;
|
||||
uint32_t :8;
|
||||
uint32_t u1CLEAR:1;
|
||||
uint32_t u1FREEZE:1;
|
||||
uint32_t :14;
|
||||
} stc_I2S_TX_FIFO_CTL_field_t;
|
||||
|
||||
typedef union un_I2S_TX_FIFO_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_TX_FIFO_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_TX_FIFO_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief TX FIFO status (I2S_TX_FIFO_STATUS)
|
||||
*/
|
||||
typedef struct stc_I2S_TX_FIFO_STATUS_field {
|
||||
uint32_t u9USED:9;
|
||||
uint32_t :7;
|
||||
uint32_t u8RD_PTR:8;
|
||||
uint32_t u8WR_PTR:8;
|
||||
} stc_I2S_TX_FIFO_STATUS_field_t;
|
||||
|
||||
typedef union un_I2S_TX_FIFO_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_TX_FIFO_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_TX_FIFO_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief TX FIFO write (I2S_TX_FIFO_WR)
|
||||
*/
|
||||
typedef struct stc_I2S_TX_FIFO_WR_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_I2S_TX_FIFO_WR_field_t;
|
||||
|
||||
typedef union un_I2S_TX_FIFO_WR {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_TX_FIFO_WR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_TX_FIFO_WR_t;
|
||||
|
||||
/**
|
||||
* \brief RX FIFO control (I2S_RX_FIFO_CTL)
|
||||
*/
|
||||
typedef struct stc_I2S_RX_FIFO_CTL_field {
|
||||
uint32_t u8TRIGGER_LEVEL:8;
|
||||
uint32_t :8;
|
||||
uint32_t u1CLEAR:1;
|
||||
uint32_t u1FREEZE:1;
|
||||
uint32_t :14;
|
||||
} stc_I2S_RX_FIFO_CTL_field_t;
|
||||
|
||||
typedef union un_I2S_RX_FIFO_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_RX_FIFO_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_RX_FIFO_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief RX FIFO status (I2S_RX_FIFO_STATUS)
|
||||
*/
|
||||
typedef struct stc_I2S_RX_FIFO_STATUS_field {
|
||||
uint32_t u9USED:9;
|
||||
uint32_t :7;
|
||||
uint32_t u8RD_PTR:8;
|
||||
uint32_t u8WR_PTR:8;
|
||||
} stc_I2S_RX_FIFO_STATUS_field_t;
|
||||
|
||||
typedef union un_I2S_RX_FIFO_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_RX_FIFO_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_RX_FIFO_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief RX FIFO read (I2S_RX_FIFO_RD)
|
||||
*/
|
||||
typedef struct stc_I2S_RX_FIFO_RD_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_I2S_RX_FIFO_RD_field_t;
|
||||
|
||||
typedef union un_I2S_RX_FIFO_RD {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_RX_FIFO_RD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_RX_FIFO_RD_t;
|
||||
|
||||
/**
|
||||
* \brief RX FIFO silent read (I2S_RX_FIFO_RD_SILENT)
|
||||
*/
|
||||
typedef struct stc_I2S_RX_FIFO_RD_SILENT_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_I2S_RX_FIFO_RD_SILENT_field_t;
|
||||
|
||||
typedef union un_I2S_RX_FIFO_RD_SILENT {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_RX_FIFO_RD_SILENT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_RX_FIFO_RD_SILENT_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt register (I2S_INTR)
|
||||
*/
|
||||
typedef struct stc_I2S_INTR_field {
|
||||
uint32_t u1TX_TRIGGER:1;
|
||||
uint32_t u1TX_NOT_FULL:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1TX_EMPTY:1;
|
||||
uint32_t u1TX_OVERFLOW:1;
|
||||
uint32_t u1TX_UNDERFLOW:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1TX_WD:1;
|
||||
uint32_t :7;
|
||||
uint32_t u1RX_TRIGGER:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_NOT_EMPTY:1;
|
||||
uint32_t u1RX_FULL:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_OVERFLOW:1;
|
||||
uint32_t u1RX_UNDERFLOW:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_WD:1;
|
||||
uint32_t :7;
|
||||
} stc_I2S_INTR_field_t;
|
||||
|
||||
typedef union un_I2S_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt set register (I2S_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_I2S_INTR_SET_field {
|
||||
uint32_t u1TX_TRIGGER:1;
|
||||
uint32_t u1TX_NOT_FULL:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1TX_EMPTY:1;
|
||||
uint32_t u1TX_OVERFLOW:1;
|
||||
uint32_t u1TX_UNDERFLOW:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1TX_WD:1;
|
||||
uint32_t :7;
|
||||
uint32_t u1RX_TRIGGER:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_NOT_EMPTY:1;
|
||||
uint32_t u1RX_FULL:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_OVERFLOW:1;
|
||||
uint32_t u1RX_UNDERFLOW:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_WD:1;
|
||||
uint32_t :7;
|
||||
} stc_I2S_INTR_SET_field_t;
|
||||
|
||||
typedef union un_I2S_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt mask register (I2S_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_I2S_INTR_MASK_field {
|
||||
uint32_t u1TX_TRIGGER:1;
|
||||
uint32_t u1TX_NOT_FULL:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1TX_EMPTY:1;
|
||||
uint32_t u1TX_OVERFLOW:1;
|
||||
uint32_t u1TX_UNDERFLOW:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1TX_WD:1;
|
||||
uint32_t :7;
|
||||
uint32_t u1RX_TRIGGER:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_NOT_EMPTY:1;
|
||||
uint32_t u1RX_FULL:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_OVERFLOW:1;
|
||||
uint32_t u1RX_UNDERFLOW:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_WD:1;
|
||||
uint32_t :7;
|
||||
} stc_I2S_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_I2S_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt masked register (I2S_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_I2S_INTR_MASKED_field {
|
||||
uint32_t u1TX_TRIGGER:1;
|
||||
uint32_t u1TX_NOT_FULL:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1TX_EMPTY:1;
|
||||
uint32_t u1TX_OVERFLOW:1;
|
||||
uint32_t u1TX_UNDERFLOW:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1TX_WD:1;
|
||||
uint32_t :7;
|
||||
uint32_t u1RX_TRIGGER:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_NOT_EMPTY:1;
|
||||
uint32_t u1RX_FULL:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_OVERFLOW:1;
|
||||
uint32_t u1RX_UNDERFLOW:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_WD:1;
|
||||
uint32_t :7;
|
||||
} stc_I2S_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_I2S_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_I2S_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_I2S_INTR_MASKED_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief I2S registers (I2S)
|
||||
*/
|
||||
typedef struct stc_I2S {
|
||||
un_I2S_CTL_t unCTL; /*!< 0x00000000 Control */
|
||||
uint32_t au32Reserved[3];
|
||||
un_I2S_CLOCK_CTL_t unCLOCK_CTL; /*!< 0x00000010 Clock control */
|
||||
un_I2S_CLOCK_STAT_t unCLOCK_STAT; /*!< 0x00000014 Clock Status */
|
||||
uint32_t au32Reserved1[2];
|
||||
un_I2S_CMD_t unCMD; /*!< 0x00000020 Command */
|
||||
uint32_t au32Reserved2[7];
|
||||
un_I2S_TR_CTL_t unTR_CTL; /*!< 0x00000040 Trigger control */
|
||||
uint32_t au32Reserved3[15];
|
||||
un_I2S_TX_CTL_t unTX_CTL; /*!< 0x00000080 Transmitter control */
|
||||
un_I2S_TX_WATCHDOG_t unTX_WATCHDOG; /*!< 0x00000084 Transmitter watchdog */
|
||||
uint32_t au32Reserved4[6];
|
||||
un_I2S_RX_CTL_t unRX_CTL; /*!< 0x000000A0 Receiver control */
|
||||
un_I2S_RX_WATCHDOG_t unRX_WATCHDOG; /*!< 0x000000A4 Receiver watchdog */
|
||||
uint32_t au32Reserved5[86];
|
||||
un_I2S_TX_FIFO_CTL_t unTX_FIFO_CTL; /*!< 0x00000200 TX FIFO control */
|
||||
un_I2S_TX_FIFO_STATUS_t unTX_FIFO_STATUS; /*!< 0x00000204 TX FIFO status */
|
||||
un_I2S_TX_FIFO_WR_t unTX_FIFO_WR; /*!< 0x00000208 TX FIFO write */
|
||||
uint32_t au32Reserved6[61];
|
||||
un_I2S_RX_FIFO_CTL_t unRX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */
|
||||
un_I2S_RX_FIFO_STATUS_t unRX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */
|
||||
un_I2S_RX_FIFO_RD_t unRX_FIFO_RD; /*!< 0x00000308 RX FIFO read */
|
||||
un_I2S_RX_FIFO_RD_SILENT_t unRX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */
|
||||
uint32_t au32Reserved7[764];
|
||||
un_I2S_INTR_t unINTR; /*!< 0x00000F00 Interrupt register */
|
||||
un_I2S_INTR_SET_t unINTR_SET; /*!< 0x00000F04 Interrupt set register */
|
||||
un_I2S_INTR_MASK_t unINTR_MASK; /*!< 0x00000F08 Interrupt mask register */
|
||||
un_I2S_INTR_MASKED_t unINTR_MASKED; /*!< 0x00000F0C Interrupt masked register */
|
||||
} stc_I2S_t; /*!< Size = 3856 (0xF10) */
|
||||
|
||||
|
||||
/* I2S.CTL */
|
||||
#define I2S_CTL_TX_ENABLED_Pos 30UL
|
||||
#define I2S_CTL_TX_ENABLED_Msk 0x40000000UL
|
||||
#define I2S_CTL_RX_ENABLED_Pos 31UL
|
||||
#define I2S_CTL_RX_ENABLED_Msk 0x80000000UL
|
||||
/* I2S.CLOCK_CTL */
|
||||
#define I2S_CLOCK_CTL_CLOCK_DIV_Pos 0UL
|
||||
#define I2S_CLOCK_CTL_CLOCK_DIV_Msk 0x3FUL
|
||||
#define I2S_CLOCK_CTL_CLOCK_SEL_Pos 8UL
|
||||
#define I2S_CLOCK_CTL_CLOCK_SEL_Msk 0x100UL
|
||||
#define I2S_CLOCK_CTL_MCLK_DIV_Pos 12UL
|
||||
#define I2S_CLOCK_CTL_MCLK_DIV_Msk 0x3000UL
|
||||
#define I2S_CLOCK_CTL_MCLK_EN_Pos 16UL
|
||||
#define I2S_CLOCK_CTL_MCLK_EN_Msk 0x10000UL
|
||||
/* I2S.CLOCK_STAT */
|
||||
#define I2S_CLOCK_STAT_MCLK_DIV_OFF_Pos 0UL
|
||||
#define I2S_CLOCK_STAT_MCLK_DIV_OFF_Msk 0x1UL
|
||||
/* I2S.CMD */
|
||||
#define I2S_CMD_TX_START_Pos 0UL
|
||||
#define I2S_CMD_TX_START_Msk 0x1UL
|
||||
#define I2S_CMD_TX_PAUSE_Pos 8UL
|
||||
#define I2S_CMD_TX_PAUSE_Msk 0x100UL
|
||||
#define I2S_CMD_RX_START_Pos 16UL
|
||||
#define I2S_CMD_RX_START_Msk 0x10000UL
|
||||
/* I2S.TR_CTL */
|
||||
#define I2S_TR_CTL_TX_REQ_EN_Pos 0UL
|
||||
#define I2S_TR_CTL_TX_REQ_EN_Msk 0x1UL
|
||||
#define I2S_TR_CTL_RX_REQ_EN_Pos 16UL
|
||||
#define I2S_TR_CTL_RX_REQ_EN_Msk 0x10000UL
|
||||
/* I2S.TX_CTL */
|
||||
#define I2S_TX_CTL_B_CLOCK_INV_Pos 3UL
|
||||
#define I2S_TX_CTL_B_CLOCK_INV_Msk 0x8UL
|
||||
#define I2S_TX_CTL_CH_NR_Pos 4UL
|
||||
#define I2S_TX_CTL_CH_NR_Msk 0x70UL
|
||||
#define I2S_TX_CTL_MS_Pos 7UL
|
||||
#define I2S_TX_CTL_MS_Msk 0x80UL
|
||||
#define I2S_TX_CTL_I2S_MODE_Pos 8UL
|
||||
#define I2S_TX_CTL_I2S_MODE_Msk 0x300UL
|
||||
#define I2S_TX_CTL_WS_PULSE_Pos 10UL
|
||||
#define I2S_TX_CTL_WS_PULSE_Msk 0x400UL
|
||||
#define I2S_TX_CTL_OVHDATA_Pos 12UL
|
||||
#define I2S_TX_CTL_OVHDATA_Msk 0x1000UL
|
||||
#define I2S_TX_CTL_WD_EN_Pos 13UL
|
||||
#define I2S_TX_CTL_WD_EN_Msk 0x2000UL
|
||||
#define I2S_TX_CTL_CH_LEN_Pos 16UL
|
||||
#define I2S_TX_CTL_CH_LEN_Msk 0x70000UL
|
||||
#define I2S_TX_CTL_WORD_LEN_Pos 20UL
|
||||
#define I2S_TX_CTL_WORD_LEN_Msk 0x700000UL
|
||||
#define I2S_TX_CTL_SCKO_POL_Pos 24UL
|
||||
#define I2S_TX_CTL_SCKO_POL_Msk 0x1000000UL
|
||||
#define I2S_TX_CTL_SCKI_POL_Pos 25UL
|
||||
#define I2S_TX_CTL_SCKI_POL_Msk 0x2000000UL
|
||||
/* I2S.TX_WATCHDOG */
|
||||
#define I2S_TX_WATCHDOG_WD_COUNTER_Pos 0UL
|
||||
#define I2S_TX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL
|
||||
/* I2S.RX_CTL */
|
||||
#define I2S_RX_CTL_B_CLOCK_INV_Pos 3UL
|
||||
#define I2S_RX_CTL_B_CLOCK_INV_Msk 0x8UL
|
||||
#define I2S_RX_CTL_CH_NR_Pos 4UL
|
||||
#define I2S_RX_CTL_CH_NR_Msk 0x70UL
|
||||
#define I2S_RX_CTL_MS_Pos 7UL
|
||||
#define I2S_RX_CTL_MS_Msk 0x80UL
|
||||
#define I2S_RX_CTL_I2S_MODE_Pos 8UL
|
||||
#define I2S_RX_CTL_I2S_MODE_Msk 0x300UL
|
||||
#define I2S_RX_CTL_WS_PULSE_Pos 10UL
|
||||
#define I2S_RX_CTL_WS_PULSE_Msk 0x400UL
|
||||
#define I2S_RX_CTL_WD_EN_Pos 13UL
|
||||
#define I2S_RX_CTL_WD_EN_Msk 0x2000UL
|
||||
#define I2S_RX_CTL_CH_LEN_Pos 16UL
|
||||
#define I2S_RX_CTL_CH_LEN_Msk 0x70000UL
|
||||
#define I2S_RX_CTL_WORD_LEN_Pos 20UL
|
||||
#define I2S_RX_CTL_WORD_LEN_Msk 0x700000UL
|
||||
#define I2S_RX_CTL_BIT_EXTENSION_Pos 23UL
|
||||
#define I2S_RX_CTL_BIT_EXTENSION_Msk 0x800000UL
|
||||
#define I2S_RX_CTL_SCKO_POL_Pos 24UL
|
||||
#define I2S_RX_CTL_SCKO_POL_Msk 0x1000000UL
|
||||
#define I2S_RX_CTL_SCKI_POL_Pos 25UL
|
||||
#define I2S_RX_CTL_SCKI_POL_Msk 0x2000000UL
|
||||
/* I2S.RX_WATCHDOG */
|
||||
#define I2S_RX_WATCHDOG_WD_COUNTER_Pos 0UL
|
||||
#define I2S_RX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL
|
||||
/* I2S.TX_FIFO_CTL */
|
||||
#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
|
||||
#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
|
||||
#define I2S_TX_FIFO_CTL_CLEAR_Pos 16UL
|
||||
#define I2S_TX_FIFO_CTL_CLEAR_Msk 0x10000UL
|
||||
#define I2S_TX_FIFO_CTL_FREEZE_Pos 17UL
|
||||
#define I2S_TX_FIFO_CTL_FREEZE_Msk 0x20000UL
|
||||
/* I2S.TX_FIFO_STATUS */
|
||||
#define I2S_TX_FIFO_STATUS_USED_Pos 0UL
|
||||
#define I2S_TX_FIFO_STATUS_USED_Msk 0x1FFUL
|
||||
#define I2S_TX_FIFO_STATUS_RD_PTR_Pos 16UL
|
||||
#define I2S_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
|
||||
#define I2S_TX_FIFO_STATUS_WR_PTR_Pos 24UL
|
||||
#define I2S_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
|
||||
/* I2S.TX_FIFO_WR */
|
||||
#define I2S_TX_FIFO_WR_DATA_Pos 0UL
|
||||
#define I2S_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL
|
||||
/* I2S.RX_FIFO_CTL */
|
||||
#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
|
||||
#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
|
||||
#define I2S_RX_FIFO_CTL_CLEAR_Pos 16UL
|
||||
#define I2S_RX_FIFO_CTL_CLEAR_Msk 0x10000UL
|
||||
#define I2S_RX_FIFO_CTL_FREEZE_Pos 17UL
|
||||
#define I2S_RX_FIFO_CTL_FREEZE_Msk 0x20000UL
|
||||
/* I2S.RX_FIFO_STATUS */
|
||||
#define I2S_RX_FIFO_STATUS_USED_Pos 0UL
|
||||
#define I2S_RX_FIFO_STATUS_USED_Msk 0x1FFUL
|
||||
#define I2S_RX_FIFO_STATUS_RD_PTR_Pos 16UL
|
||||
#define I2S_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
|
||||
#define I2S_RX_FIFO_STATUS_WR_PTR_Pos 24UL
|
||||
#define I2S_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
|
||||
/* I2S.RX_FIFO_RD */
|
||||
#define I2S_RX_FIFO_RD_DATA_Pos 0UL
|
||||
#define I2S_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
|
||||
/* I2S.RX_FIFO_RD_SILENT */
|
||||
#define I2S_RX_FIFO_RD_SILENT_DATA_Pos 0UL
|
||||
#define I2S_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
|
||||
/* I2S.INTR */
|
||||
#define I2S_INTR_TX_TRIGGER_Pos 0UL
|
||||
#define I2S_INTR_TX_TRIGGER_Msk 0x1UL
|
||||
#define I2S_INTR_TX_NOT_FULL_Pos 1UL
|
||||
#define I2S_INTR_TX_NOT_FULL_Msk 0x2UL
|
||||
#define I2S_INTR_TX_EMPTY_Pos 4UL
|
||||
#define I2S_INTR_TX_EMPTY_Msk 0x10UL
|
||||
#define I2S_INTR_TX_OVERFLOW_Pos 5UL
|
||||
#define I2S_INTR_TX_OVERFLOW_Msk 0x20UL
|
||||
#define I2S_INTR_TX_UNDERFLOW_Pos 6UL
|
||||
#define I2S_INTR_TX_UNDERFLOW_Msk 0x40UL
|
||||
#define I2S_INTR_TX_WD_Pos 8UL
|
||||
#define I2S_INTR_TX_WD_Msk 0x100UL
|
||||
#define I2S_INTR_RX_TRIGGER_Pos 16UL
|
||||
#define I2S_INTR_RX_TRIGGER_Msk 0x10000UL
|
||||
#define I2S_INTR_RX_NOT_EMPTY_Pos 18UL
|
||||
#define I2S_INTR_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define I2S_INTR_RX_FULL_Pos 19UL
|
||||
#define I2S_INTR_RX_FULL_Msk 0x80000UL
|
||||
#define I2S_INTR_RX_OVERFLOW_Pos 21UL
|
||||
#define I2S_INTR_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define I2S_INTR_RX_UNDERFLOW_Pos 22UL
|
||||
#define I2S_INTR_RX_UNDERFLOW_Msk 0x400000UL
|
||||
#define I2S_INTR_RX_WD_Pos 24UL
|
||||
#define I2S_INTR_RX_WD_Msk 0x1000000UL
|
||||
/* I2S.INTR_SET */
|
||||
#define I2S_INTR_SET_TX_TRIGGER_Pos 0UL
|
||||
#define I2S_INTR_SET_TX_TRIGGER_Msk 0x1UL
|
||||
#define I2S_INTR_SET_TX_NOT_FULL_Pos 1UL
|
||||
#define I2S_INTR_SET_TX_NOT_FULL_Msk 0x2UL
|
||||
#define I2S_INTR_SET_TX_EMPTY_Pos 4UL
|
||||
#define I2S_INTR_SET_TX_EMPTY_Msk 0x10UL
|
||||
#define I2S_INTR_SET_TX_OVERFLOW_Pos 5UL
|
||||
#define I2S_INTR_SET_TX_OVERFLOW_Msk 0x20UL
|
||||
#define I2S_INTR_SET_TX_UNDERFLOW_Pos 6UL
|
||||
#define I2S_INTR_SET_TX_UNDERFLOW_Msk 0x40UL
|
||||
#define I2S_INTR_SET_TX_WD_Pos 8UL
|
||||
#define I2S_INTR_SET_TX_WD_Msk 0x100UL
|
||||
#define I2S_INTR_SET_RX_TRIGGER_Pos 16UL
|
||||
#define I2S_INTR_SET_RX_TRIGGER_Msk 0x10000UL
|
||||
#define I2S_INTR_SET_RX_NOT_EMPTY_Pos 18UL
|
||||
#define I2S_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define I2S_INTR_SET_RX_FULL_Pos 19UL
|
||||
#define I2S_INTR_SET_RX_FULL_Msk 0x80000UL
|
||||
#define I2S_INTR_SET_RX_OVERFLOW_Pos 21UL
|
||||
#define I2S_INTR_SET_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define I2S_INTR_SET_RX_UNDERFLOW_Pos 22UL
|
||||
#define I2S_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL
|
||||
#define I2S_INTR_SET_RX_WD_Pos 24UL
|
||||
#define I2S_INTR_SET_RX_WD_Msk 0x1000000UL
|
||||
/* I2S.INTR_MASK */
|
||||
#define I2S_INTR_MASK_TX_TRIGGER_Pos 0UL
|
||||
#define I2S_INTR_MASK_TX_TRIGGER_Msk 0x1UL
|
||||
#define I2S_INTR_MASK_TX_NOT_FULL_Pos 1UL
|
||||
#define I2S_INTR_MASK_TX_NOT_FULL_Msk 0x2UL
|
||||
#define I2S_INTR_MASK_TX_EMPTY_Pos 4UL
|
||||
#define I2S_INTR_MASK_TX_EMPTY_Msk 0x10UL
|
||||
#define I2S_INTR_MASK_TX_OVERFLOW_Pos 5UL
|
||||
#define I2S_INTR_MASK_TX_OVERFLOW_Msk 0x20UL
|
||||
#define I2S_INTR_MASK_TX_UNDERFLOW_Pos 6UL
|
||||
#define I2S_INTR_MASK_TX_UNDERFLOW_Msk 0x40UL
|
||||
#define I2S_INTR_MASK_TX_WD_Pos 8UL
|
||||
#define I2S_INTR_MASK_TX_WD_Msk 0x100UL
|
||||
#define I2S_INTR_MASK_RX_TRIGGER_Pos 16UL
|
||||
#define I2S_INTR_MASK_RX_TRIGGER_Msk 0x10000UL
|
||||
#define I2S_INTR_MASK_RX_NOT_EMPTY_Pos 18UL
|
||||
#define I2S_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define I2S_INTR_MASK_RX_FULL_Pos 19UL
|
||||
#define I2S_INTR_MASK_RX_FULL_Msk 0x80000UL
|
||||
#define I2S_INTR_MASK_RX_OVERFLOW_Pos 21UL
|
||||
#define I2S_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define I2S_INTR_MASK_RX_UNDERFLOW_Pos 22UL
|
||||
#define I2S_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL
|
||||
#define I2S_INTR_MASK_RX_WD_Pos 24UL
|
||||
#define I2S_INTR_MASK_RX_WD_Msk 0x1000000UL
|
||||
/* I2S.INTR_MASKED */
|
||||
#define I2S_INTR_MASKED_TX_TRIGGER_Pos 0UL
|
||||
#define I2S_INTR_MASKED_TX_TRIGGER_Msk 0x1UL
|
||||
#define I2S_INTR_MASKED_TX_NOT_FULL_Pos 1UL
|
||||
#define I2S_INTR_MASKED_TX_NOT_FULL_Msk 0x2UL
|
||||
#define I2S_INTR_MASKED_TX_EMPTY_Pos 4UL
|
||||
#define I2S_INTR_MASKED_TX_EMPTY_Msk 0x10UL
|
||||
#define I2S_INTR_MASKED_TX_OVERFLOW_Pos 5UL
|
||||
#define I2S_INTR_MASKED_TX_OVERFLOW_Msk 0x20UL
|
||||
#define I2S_INTR_MASKED_TX_UNDERFLOW_Pos 6UL
|
||||
#define I2S_INTR_MASKED_TX_UNDERFLOW_Msk 0x40UL
|
||||
#define I2S_INTR_MASKED_TX_WD_Pos 8UL
|
||||
#define I2S_INTR_MASKED_TX_WD_Msk 0x100UL
|
||||
#define I2S_INTR_MASKED_RX_TRIGGER_Pos 16UL
|
||||
#define I2S_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL
|
||||
#define I2S_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL
|
||||
#define I2S_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define I2S_INTR_MASKED_RX_FULL_Pos 19UL
|
||||
#define I2S_INTR_MASKED_RX_FULL_Msk 0x80000UL
|
||||
#define I2S_INTR_MASKED_RX_OVERFLOW_Pos 21UL
|
||||
#define I2S_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define I2S_INTR_MASKED_RX_UNDERFLOW_Pos 22UL
|
||||
#define I2S_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL
|
||||
#define I2S_INTR_MASKED_RX_WD_Pos 24UL
|
||||
#define I2S_INTR_MASKED_RX_WD_Msk 0x1000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_I2S_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,289 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_ipc.h
|
||||
*
|
||||
* \brief
|
||||
* IPC IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_IPC_H_
|
||||
#define _CYIP_IPC_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_STRUCT_SECTION_SIZE 0x00000020UL
|
||||
#define IPC_INTR_STRUCT_SECTION_SIZE 0x00000020UL
|
||||
#define IPC_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief IPC acquire (IPC_STRUCT_ACQUIRE)
|
||||
*/
|
||||
typedef struct stc_IPC_STRUCT_ACQUIRE_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :2;
|
||||
uint32_t u4PC:4;
|
||||
uint32_t u4MS:4;
|
||||
uint32_t :19;
|
||||
uint32_t u1SUCCESS:1;
|
||||
} stc_IPC_STRUCT_ACQUIRE_field_t;
|
||||
|
||||
typedef union un_IPC_STRUCT_ACQUIRE {
|
||||
uint32_t u32Register;
|
||||
stc_IPC_STRUCT_ACQUIRE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_IPC_STRUCT_ACQUIRE_t;
|
||||
|
||||
/**
|
||||
* \brief IPC release (IPC_STRUCT_RELEASE)
|
||||
*/
|
||||
typedef struct stc_IPC_STRUCT_RELEASE_field {
|
||||
uint32_t u16INTR_RELEASE:16;
|
||||
uint32_t :16;
|
||||
} stc_IPC_STRUCT_RELEASE_field_t;
|
||||
|
||||
typedef union un_IPC_STRUCT_RELEASE {
|
||||
uint32_t u32Register;
|
||||
stc_IPC_STRUCT_RELEASE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_IPC_STRUCT_RELEASE_t;
|
||||
|
||||
/**
|
||||
* \brief IPC notification (IPC_STRUCT_NOTIFY)
|
||||
*/
|
||||
typedef struct stc_IPC_STRUCT_NOTIFY_field {
|
||||
uint32_t u16INTR_NOTIFY:16;
|
||||
uint32_t :16;
|
||||
} stc_IPC_STRUCT_NOTIFY_field_t;
|
||||
|
||||
typedef union un_IPC_STRUCT_NOTIFY {
|
||||
uint32_t u32Register;
|
||||
stc_IPC_STRUCT_NOTIFY_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_IPC_STRUCT_NOTIFY_t;
|
||||
|
||||
/**
|
||||
* \brief IPC data 0 (IPC_STRUCT_DATA0)
|
||||
*/
|
||||
typedef struct stc_IPC_STRUCT_DATA0_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_IPC_STRUCT_DATA0_field_t;
|
||||
|
||||
typedef union un_IPC_STRUCT_DATA0 {
|
||||
uint32_t u32Register;
|
||||
stc_IPC_STRUCT_DATA0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_IPC_STRUCT_DATA0_t;
|
||||
|
||||
/**
|
||||
* \brief IPC data 1 (IPC_STRUCT_DATA1)
|
||||
*/
|
||||
typedef struct stc_IPC_STRUCT_DATA1_field {
|
||||
uint32_t u32DATA:32;
|
||||
} stc_IPC_STRUCT_DATA1_field_t;
|
||||
|
||||
typedef union un_IPC_STRUCT_DATA1 {
|
||||
uint32_t u32Register;
|
||||
stc_IPC_STRUCT_DATA1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_IPC_STRUCT_DATA1_t;
|
||||
|
||||
/**
|
||||
* \brief IPC lock status (IPC_STRUCT_LOCK_STATUS)
|
||||
*/
|
||||
typedef struct stc_IPC_STRUCT_LOCK_STATUS_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :2;
|
||||
uint32_t u4PC:4;
|
||||
uint32_t u4MS:4;
|
||||
uint32_t :19;
|
||||
uint32_t u1ACQUIRED:1;
|
||||
} stc_IPC_STRUCT_LOCK_STATUS_field_t;
|
||||
|
||||
typedef union un_IPC_STRUCT_LOCK_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_IPC_STRUCT_LOCK_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_IPC_STRUCT_LOCK_STATUS_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Interrupt (IPC_INTR_STRUCT_INTR)
|
||||
*/
|
||||
typedef struct stc_IPC_INTR_STRUCT_INTR_field {
|
||||
uint32_t u16RELEASE:16;
|
||||
uint32_t u16NOTIFY:16;
|
||||
} stc_IPC_INTR_STRUCT_INTR_field_t;
|
||||
|
||||
typedef union un_IPC_INTR_STRUCT_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_IPC_INTR_STRUCT_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_IPC_INTR_STRUCT_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt set (IPC_INTR_STRUCT_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_IPC_INTR_STRUCT_INTR_SET_field {
|
||||
uint32_t u16RELEASE:16;
|
||||
uint32_t u16NOTIFY:16;
|
||||
} stc_IPC_INTR_STRUCT_INTR_SET_field_t;
|
||||
|
||||
typedef union un_IPC_INTR_STRUCT_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_IPC_INTR_STRUCT_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_IPC_INTR_STRUCT_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt mask (IPC_INTR_STRUCT_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_IPC_INTR_STRUCT_INTR_MASK_field {
|
||||
uint32_t u16RELEASE:16;
|
||||
uint32_t u16NOTIFY:16;
|
||||
} stc_IPC_INTR_STRUCT_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_IPC_INTR_STRUCT_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_IPC_INTR_STRUCT_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_IPC_INTR_STRUCT_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt masked (IPC_INTR_STRUCT_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_IPC_INTR_STRUCT_INTR_MASKED_field {
|
||||
uint32_t u16RELEASE:16;
|
||||
uint32_t u16NOTIFY:16;
|
||||
} stc_IPC_INTR_STRUCT_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_IPC_INTR_STRUCT_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_IPC_INTR_STRUCT_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_IPC_INTR_STRUCT_INTR_MASKED_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT)
|
||||
*/
|
||||
typedef struct stc_IPC_STRUCT {
|
||||
un_IPC_STRUCT_ACQUIRE_t unACQUIRE; /*!< 0x00000000 IPC acquire */
|
||||
un_IPC_STRUCT_RELEASE_t unRELEASE; /*!< 0x00000004 IPC release */
|
||||
un_IPC_STRUCT_NOTIFY_t unNOTIFY; /*!< 0x00000008 IPC notification */
|
||||
un_IPC_STRUCT_DATA0_t unDATA0; /*!< 0x0000000C IPC data 0 */
|
||||
un_IPC_STRUCT_DATA1_t unDATA1; /*!< 0x00000010 IPC data 1 */
|
||||
uint32_t au32Reserved[2];
|
||||
un_IPC_STRUCT_LOCK_STATUS_t unLOCK_STATUS; /*!< 0x0000001C IPC lock status */
|
||||
} stc_IPC_STRUCT_t; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT)
|
||||
*/
|
||||
typedef struct stc_IPC_INTR_STRUCT {
|
||||
un_IPC_INTR_STRUCT_INTR_t unINTR; /*!< 0x00000000 Interrupt */
|
||||
un_IPC_INTR_STRUCT_INTR_SET_t unINTR_SET; /*!< 0x00000004 Interrupt set */
|
||||
un_IPC_INTR_STRUCT_INTR_MASK_t unINTR_MASK; /*!< 0x00000008 Interrupt mask */
|
||||
un_IPC_INTR_STRUCT_INTR_MASKED_t unINTR_MASKED; /*!< 0x0000000C Interrupt masked */
|
||||
uint32_t au32Reserved[4];
|
||||
} stc_IPC_INTR_STRUCT_t; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief IPC (IPC)
|
||||
*/
|
||||
typedef struct stc_IPC {
|
||||
stc_IPC_STRUCT_t STRUCT[16]; /*!< 0x00000000 IPC structure */
|
||||
uint32_t au32Reserved[896];
|
||||
stc_IPC_INTR_STRUCT_t INTR_STRUCT[16]; /*!< 0x00001000 IPC interrupt structure */
|
||||
} stc_IPC_t; /*!< Size = 4608 (0x1200) */
|
||||
|
||||
|
||||
/* IPC_STRUCT.ACQUIRE */
|
||||
#define IPC_STRUCT_ACQUIRE_P_Pos 0UL
|
||||
#define IPC_STRUCT_ACQUIRE_P_Msk 0x1UL
|
||||
#define IPC_STRUCT_ACQUIRE_NS_Pos 1UL
|
||||
#define IPC_STRUCT_ACQUIRE_NS_Msk 0x2UL
|
||||
#define IPC_STRUCT_ACQUIRE_PC_Pos 4UL
|
||||
#define IPC_STRUCT_ACQUIRE_PC_Msk 0xF0UL
|
||||
#define IPC_STRUCT_ACQUIRE_MS_Pos 8UL
|
||||
#define IPC_STRUCT_ACQUIRE_MS_Msk 0xF00UL
|
||||
#define IPC_STRUCT_ACQUIRE_SUCCESS_Pos 31UL
|
||||
#define IPC_STRUCT_ACQUIRE_SUCCESS_Msk 0x80000000UL
|
||||
/* IPC_STRUCT.RELEASE */
|
||||
#define IPC_STRUCT_RELEASE_INTR_RELEASE_Pos 0UL
|
||||
#define IPC_STRUCT_RELEASE_INTR_RELEASE_Msk 0xFFFFUL
|
||||
/* IPC_STRUCT.NOTIFY */
|
||||
#define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Pos 0UL
|
||||
#define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk 0xFFFFUL
|
||||
/* IPC_STRUCT.DATA0 */
|
||||
#define IPC_STRUCT_DATA0_DATA_Pos 0UL
|
||||
#define IPC_STRUCT_DATA0_DATA_Msk 0xFFFFFFFFUL
|
||||
/* IPC_STRUCT.DATA1 */
|
||||
#define IPC_STRUCT_DATA1_DATA_Pos 0UL
|
||||
#define IPC_STRUCT_DATA1_DATA_Msk 0xFFFFFFFFUL
|
||||
/* IPC_STRUCT.LOCK_STATUS */
|
||||
#define IPC_STRUCT_LOCK_STATUS_P_Pos 0UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_P_Msk 0x1UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_NS_Pos 1UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_NS_Msk 0x2UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_PC_Pos 4UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_PC_Msk 0xF0UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_MS_Pos 8UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_MS_Msk 0xF00UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Pos 31UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* IPC_INTR_STRUCT.INTR */
|
||||
#define IPC_INTR_STRUCT_INTR_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_INTR_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_INTR_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_INTR_NOTIFY_Msk 0xFFFF0000UL
|
||||
/* IPC_INTR_STRUCT.INTR_SET */
|
||||
#define IPC_INTR_STRUCT_INTR_SET_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_INTR_SET_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Msk 0xFFFF0000UL
|
||||
/* IPC_INTR_STRUCT.INTR_MASK */
|
||||
#define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk 0xFFFF0000UL
|
||||
/* IPC_INTR_STRUCT.INTR_MASKED */
|
||||
#define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Msk 0xFFFF0000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_IPC_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,689 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_lin.h
|
||||
*
|
||||
* \brief
|
||||
* LIN IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_LIN_H_
|
||||
#define _CYIP_LIN_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* LIN
|
||||
*******************************************************************************/
|
||||
|
||||
#define LIN_CH_SECTION_SIZE 0x00000100UL
|
||||
#define LIN_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Control 0 (LIN_CH_CTL0)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_CTL0_field {
|
||||
uint32_t u2STOP_BITS:2;
|
||||
uint32_t :2;
|
||||
uint32_t u1AUTO_EN:1;
|
||||
uint32_t :3;
|
||||
uint32_t u2BREAK_DELIMITER_LENGTH:2;
|
||||
uint32_t :6;
|
||||
uint32_t u5BREAK_WAKEUP_LENGTH:5;
|
||||
uint32_t :3;
|
||||
uint32_t u1MODE:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1BIT_ERROR_IGNORE:1;
|
||||
uint32_t u1PARITY:1;
|
||||
uint32_t u1PARITY_EN:1;
|
||||
uint32_t u1FILTER_EN:1;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_LIN_CH_CTL0_field_t;
|
||||
|
||||
typedef union un_LIN_CH_CTL0 {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_CTL0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_CTL0_t;
|
||||
|
||||
/**
|
||||
* \brief Control 1 (LIN_CH_CTL1)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_CTL1_field {
|
||||
uint32_t u3DATA_NR:3;
|
||||
uint32_t :5;
|
||||
uint32_t u1CHECKSUM_ENHANCED:1;
|
||||
uint32_t :7;
|
||||
uint32_t u8FRAME_TIMEOUT:8;
|
||||
uint32_t u2FRAME_TIMEOUT_SEL:2;
|
||||
uint32_t :6;
|
||||
} stc_LIN_CH_CTL1_field_t;
|
||||
|
||||
typedef union un_LIN_CH_CTL1 {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_CTL1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_CTL1_t;
|
||||
|
||||
/**
|
||||
* \brief Status (LIN_CH_STATUS)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_STATUS_field {
|
||||
uint32_t u4DATA_IDX:4;
|
||||
uint32_t u1HEADER_RESPONSE:1;
|
||||
uint32_t u1RX_DATA0_FRAME_ERROR:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1TX_BUSY:1;
|
||||
uint32_t u1RX_BUSY:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1TX_DONE:1;
|
||||
uint32_t u1RX_DONE:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1TX_HEADER_BIT_ERROR:1;
|
||||
uint32_t u1TX_RESPONSE_BIT_ERROR:1;
|
||||
uint32_t :6;
|
||||
uint32_t u1RX_HEADER_FRAME_ERROR:1;
|
||||
uint32_t u1RX_HEADER_SYNC_ERROR:1;
|
||||
uint32_t u1RX_HEADER_PARITY_ERROR:1;
|
||||
uint32_t u1RX_RESPONSE_FRAME_ERROR:1;
|
||||
uint32_t u1RX_RESPONSE_CHECKSUM_ERROR:1;
|
||||
uint32_t :3;
|
||||
} stc_LIN_CH_STATUS_field_t;
|
||||
|
||||
typedef union un_LIN_CH_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Command (LIN_CH_CMD)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_CMD_field {
|
||||
uint32_t u1TX_HEADER:1;
|
||||
uint32_t u1TX_RESPONSE:1;
|
||||
uint32_t u1TX_WAKEUP:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1RX_HEADER:1;
|
||||
uint32_t u1RX_RESPONSE:1;
|
||||
uint32_t :22;
|
||||
} stc_LIN_CH_CMD_field_t;
|
||||
|
||||
typedef union un_LIN_CH_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_CMD_t;
|
||||
|
||||
/**
|
||||
* \brief TX/RX status (LIN_CH_TX_RX_STATUS)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_TX_RX_STATUS_field {
|
||||
uint32_t u8SYNC_COUNTER:8;
|
||||
uint32_t :8;
|
||||
uint32_t u1TX_IN:1;
|
||||
uint32_t u1RX_IN:1;
|
||||
uint32_t :6;
|
||||
uint32_t u1TX_OUT:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1EN_OUT:1;
|
||||
uint32_t :5;
|
||||
} stc_LIN_CH_TX_RX_STATUS_field_t;
|
||||
|
||||
typedef union un_LIN_CH_TX_RX_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_TX_RX_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_TX_RX_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief PID and checksum (LIN_CH_PID_CHECKSUM)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_PID_CHECKSUM_field {
|
||||
uint32_t u8PID:8;
|
||||
uint32_t u8CHECKSUM:8;
|
||||
uint32_t :16;
|
||||
} stc_LIN_CH_PID_CHECKSUM_field_t;
|
||||
|
||||
typedef union un_LIN_CH_PID_CHECKSUM {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_PID_CHECKSUM_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_PID_CHECKSUM_t;
|
||||
|
||||
/**
|
||||
* \brief Response data 0 (LIN_CH_DATA0)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_DATA0_field {
|
||||
uint32_t u8DATA1:8;
|
||||
uint32_t u8DATA2:8;
|
||||
uint32_t u8DATA3:8;
|
||||
uint32_t u8DATA4:8;
|
||||
} stc_LIN_CH_DATA0_field_t;
|
||||
|
||||
typedef union un_LIN_CH_DATA0 {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_DATA0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_DATA0_t;
|
||||
|
||||
/**
|
||||
* \brief Response data 1 (LIN_CH_DATA1)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_DATA1_field {
|
||||
uint32_t u8DATA5:8;
|
||||
uint32_t u8DATA6:8;
|
||||
uint32_t u8DATA7:8;
|
||||
uint32_t u8DATA8:8;
|
||||
} stc_LIN_CH_DATA1_field_t;
|
||||
|
||||
typedef union un_LIN_CH_DATA1 {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_DATA1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_DATA1_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt (LIN_CH_INTR)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_INTR_field {
|
||||
uint32_t u1TX_HEADER_DONE:1;
|
||||
uint32_t u1TX_RESPONSE_DONE:1;
|
||||
uint32_t u1TX_WAKEUP_DONE:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1RX_HEADER_DONE:1;
|
||||
uint32_t u1RX_RESPONSE_DONE:1;
|
||||
uint32_t u1RX_BREAK_WAKEUP_DONE:1;
|
||||
uint32_t u1RX_HEADER_SYNC_DONE:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_NOISE_DETECT:1;
|
||||
uint32_t u1TIMEOUT:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1TX_HEADER_BIT_ERROR:1;
|
||||
uint32_t u1TX_RESPONSE_BIT_ERROR:1;
|
||||
uint32_t :6;
|
||||
uint32_t u1RX_HEADER_FRAME_ERROR:1;
|
||||
uint32_t u1RX_HEADER_SYNC_ERROR:1;
|
||||
uint32_t u1RX_HEADER_PARITY_ERROR:1;
|
||||
uint32_t u1RX_RESPONSE_FRAME_ERROR:1;
|
||||
uint32_t u1RX_RESPONSE_CHECKSUM_ERROR:1;
|
||||
uint32_t :3;
|
||||
} stc_LIN_CH_INTR_field_t;
|
||||
|
||||
typedef union un_LIN_CH_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt set (LIN_CH_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_INTR_SET_field {
|
||||
uint32_t u1TX_HEADER_DONE:1;
|
||||
uint32_t u1TX_RESPONSE_DONE:1;
|
||||
uint32_t u1TX_WAKEUP_DONE:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1RX_HEADER_DONE:1;
|
||||
uint32_t u1RX_RESPONSE_DONE:1;
|
||||
uint32_t u1RX_BREAK_WAKEUP_DONE:1;
|
||||
uint32_t u1RX_HEADER_SYNC_DONE:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_NOISE_DETECT:1;
|
||||
uint32_t u1TIMEOUT:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1TX_HEADER_BIT_ERROR:1;
|
||||
uint32_t u1TX_RESPONSE_BIT_ERROR:1;
|
||||
uint32_t :6;
|
||||
uint32_t u1RX_HEADER_FRAME_ERROR:1;
|
||||
uint32_t u1RX_HEADER_SYNC_ERROR:1;
|
||||
uint32_t u1RX_HEADER_PARITY_ERROR:1;
|
||||
uint32_t u1RX_RESPONSE_FRAME_ERROR:1;
|
||||
uint32_t u1RX_RESPONSE_CHECKSUM_ERROR:1;
|
||||
uint32_t :3;
|
||||
} stc_LIN_CH_INTR_SET_field_t;
|
||||
|
||||
typedef union un_LIN_CH_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt mask (LIN_CH_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_INTR_MASK_field {
|
||||
uint32_t u1TX_HEADER_DONE:1;
|
||||
uint32_t u1TX_RESPONSE_DONE:1;
|
||||
uint32_t u1TX_WAKEUP_DONE:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1RX_HEADER_DONE:1;
|
||||
uint32_t u1RX_RESPONSE_DONE:1;
|
||||
uint32_t u1RX_BREAK_WAKEUP_DONE:1;
|
||||
uint32_t u1RX_HEADER_SYNC_DONE:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_NOISE_DETECT:1;
|
||||
uint32_t u1TIMEOUT:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1TX_HEADER_BIT_ERROR:1;
|
||||
uint32_t u1TX_RESPONSE_BIT_ERROR:1;
|
||||
uint32_t :6;
|
||||
uint32_t u1RX_HEADER_FRAME_ERROR:1;
|
||||
uint32_t u1RX_HEADER_SYNC_ERROR:1;
|
||||
uint32_t u1RX_HEADER_PARITY_ERROR:1;
|
||||
uint32_t u1RX_RESPONSE_FRAME_ERROR:1;
|
||||
uint32_t u1RX_RESPONSE_CHECKSUM_ERROR:1;
|
||||
uint32_t :3;
|
||||
} stc_LIN_CH_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_LIN_CH_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt masked (LIN_CH_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_LIN_CH_INTR_MASKED_field {
|
||||
uint32_t u1TX_HEADER_DONE:1;
|
||||
uint32_t u1TX_RESPONSE_DONE:1;
|
||||
uint32_t u1TX_WAKEUP_DONE:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1RX_HEADER_DONE:1;
|
||||
uint32_t u1RX_RESPONSE_DONE:1;
|
||||
uint32_t u1RX_BREAK_WAKEUP_DONE:1;
|
||||
uint32_t u1RX_HEADER_SYNC_DONE:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RX_NOISE_DETECT:1;
|
||||
uint32_t u1TIMEOUT:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1TX_HEADER_BIT_ERROR:1;
|
||||
uint32_t u1TX_RESPONSE_BIT_ERROR:1;
|
||||
uint32_t :6;
|
||||
uint32_t u1RX_HEADER_FRAME_ERROR:1;
|
||||
uint32_t u1RX_HEADER_SYNC_ERROR:1;
|
||||
uint32_t u1RX_HEADER_PARITY_ERROR:1;
|
||||
uint32_t u1RX_RESPONSE_FRAME_ERROR:1;
|
||||
uint32_t u1RX_RESPONSE_CHECKSUM_ERROR:1;
|
||||
uint32_t :3;
|
||||
} stc_LIN_CH_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_LIN_CH_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_CH_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_CH_INTR_MASKED_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Error control (LIN_ERROR_CTL)
|
||||
*/
|
||||
typedef struct stc_LIN_ERROR_CTL_field {
|
||||
uint32_t u5CH_IDX:5;
|
||||
uint32_t :11;
|
||||
uint32_t u1TX_SYNC_ERROR:1;
|
||||
uint32_t u1TX_SYNC_STOP_ERROR:1;
|
||||
uint32_t u1TX_PARITY_ERROR:1;
|
||||
uint32_t u1TX_PID_STOP_ERROR:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1TX_DATA_STOP_ERROR:1;
|
||||
uint32_t u1TX_CHECKSUM_ERROR:1;
|
||||
uint32_t u1TX_CHECKSUM_STOP_ERROR:1;
|
||||
uint32_t :7;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_LIN_ERROR_CTL_field_t;
|
||||
|
||||
typedef union un_LIN_ERROR_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_ERROR_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_ERROR_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Test control (LIN_TEST_CTL)
|
||||
*/
|
||||
typedef struct stc_LIN_TEST_CTL_field {
|
||||
uint32_t u5CH_IDX:5;
|
||||
uint32_t :11;
|
||||
uint32_t u1MODE:1;
|
||||
uint32_t :14;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_LIN_TEST_CTL_field_t;
|
||||
|
||||
typedef union un_LIN_TEST_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_LIN_TEST_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_LIN_TEST_CTL_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH)
|
||||
*/
|
||||
typedef struct stc_LIN_CH {
|
||||
un_LIN_CH_CTL0_t unCTL0; /*!< 0x00000000 Control 0 */
|
||||
un_LIN_CH_CTL1_t unCTL1; /*!< 0x00000004 Control 1 */
|
||||
un_LIN_CH_STATUS_t unSTATUS; /*!< 0x00000008 Status */
|
||||
uint32_t u32Reserved;
|
||||
un_LIN_CH_CMD_t unCMD; /*!< 0x00000010 Command */
|
||||
uint32_t au32Reserved1[19];
|
||||
un_LIN_CH_TX_RX_STATUS_t unTX_RX_STATUS; /*!< 0x00000060 TX/RX status */
|
||||
uint32_t au32Reserved2[7];
|
||||
un_LIN_CH_PID_CHECKSUM_t unPID_CHECKSUM; /*!< 0x00000080 PID and checksum */
|
||||
un_LIN_CH_DATA0_t unDATA0; /*!< 0x00000084 Response data 0 */
|
||||
un_LIN_CH_DATA1_t unDATA1; /*!< 0x00000088 Response data 1 */
|
||||
uint32_t au32Reserved3[13];
|
||||
un_LIN_CH_INTR_t unINTR; /*!< 0x000000C0 Interrupt */
|
||||
un_LIN_CH_INTR_SET_t unINTR_SET; /*!< 0x000000C4 Interrupt set */
|
||||
un_LIN_CH_INTR_MASK_t unINTR_MASK; /*!< 0x000000C8 Interrupt mask */
|
||||
un_LIN_CH_INTR_MASKED_t unINTR_MASKED; /*!< 0x000000CC Interrupt masked */
|
||||
uint32_t au32Reserved4[12];
|
||||
} stc_LIN_CH_t; /*!< Size = 256 (0x100) */
|
||||
|
||||
/**
|
||||
* \brief LIN (LIN)
|
||||
*/
|
||||
typedef struct stc_LIN {
|
||||
un_LIN_ERROR_CTL_t unERROR_CTL; /*!< 0x00000000 Error control */
|
||||
un_LIN_TEST_CTL_t unTEST_CTL; /*!< 0x00000004 Test control */
|
||||
uint32_t au32Reserved[8190];
|
||||
stc_LIN_CH_t CH[32]; /*!< 0x00008000 LIN channel structure */
|
||||
} stc_LIN_t; /*!< Size = 40960 (0xA000) */
|
||||
|
||||
|
||||
/* LIN_CH.CTL0 */
|
||||
#define LIN_CH_CTL0_STOP_BITS_Pos 0UL
|
||||
#define LIN_CH_CTL0_STOP_BITS_Msk 0x3UL
|
||||
#define LIN_CH_CTL0_AUTO_EN_Pos 4UL
|
||||
#define LIN_CH_CTL0_AUTO_EN_Msk 0x10UL
|
||||
#define LIN_CH_CTL0_BREAK_DELIMITER_LENGTH_Pos 8UL
|
||||
#define LIN_CH_CTL0_BREAK_DELIMITER_LENGTH_Msk 0x300UL
|
||||
#define LIN_CH_CTL0_BREAK_WAKEUP_LENGTH_Pos 16UL
|
||||
#define LIN_CH_CTL0_BREAK_WAKEUP_LENGTH_Msk 0x1F0000UL
|
||||
#define LIN_CH_CTL0_MODE_Pos 24UL
|
||||
#define LIN_CH_CTL0_MODE_Msk 0x1000000UL
|
||||
#define LIN_CH_CTL0_BIT_ERROR_IGNORE_Pos 27UL
|
||||
#define LIN_CH_CTL0_BIT_ERROR_IGNORE_Msk 0x8000000UL
|
||||
#define LIN_CH_CTL0_PARITY_Pos 28UL
|
||||
#define LIN_CH_CTL0_PARITY_Msk 0x10000000UL
|
||||
#define LIN_CH_CTL0_PARITY_EN_Pos 29UL
|
||||
#define LIN_CH_CTL0_PARITY_EN_Msk 0x20000000UL
|
||||
#define LIN_CH_CTL0_FILTER_EN_Pos 30UL
|
||||
#define LIN_CH_CTL0_FILTER_EN_Msk 0x40000000UL
|
||||
#define LIN_CH_CTL0_ENABLED_Pos 31UL
|
||||
#define LIN_CH_CTL0_ENABLED_Msk 0x80000000UL
|
||||
/* LIN_CH.CTL1 */
|
||||
#define LIN_CH_CTL1_DATA_NR_Pos 0UL
|
||||
#define LIN_CH_CTL1_DATA_NR_Msk 0x7UL
|
||||
#define LIN_CH_CTL1_CHECKSUM_ENHANCED_Pos 8UL
|
||||
#define LIN_CH_CTL1_CHECKSUM_ENHANCED_Msk 0x100UL
|
||||
#define LIN_CH_CTL1_FRAME_TIMEOUT_Pos 16UL
|
||||
#define LIN_CH_CTL1_FRAME_TIMEOUT_Msk 0xFF0000UL
|
||||
#define LIN_CH_CTL1_FRAME_TIMEOUT_SEL_Pos 24UL
|
||||
#define LIN_CH_CTL1_FRAME_TIMEOUT_SEL_Msk 0x3000000UL
|
||||
/* LIN_CH.STATUS */
|
||||
#define LIN_CH_STATUS_DATA_IDX_Pos 0UL
|
||||
#define LIN_CH_STATUS_DATA_IDX_Msk 0xFUL
|
||||
#define LIN_CH_STATUS_HEADER_RESPONSE_Pos 4UL
|
||||
#define LIN_CH_STATUS_HEADER_RESPONSE_Msk 0x10UL
|
||||
#define LIN_CH_STATUS_RX_DATA0_FRAME_ERROR_Pos 5UL
|
||||
#define LIN_CH_STATUS_RX_DATA0_FRAME_ERROR_Msk 0x20UL
|
||||
#define LIN_CH_STATUS_TX_BUSY_Pos 8UL
|
||||
#define LIN_CH_STATUS_TX_BUSY_Msk 0x100UL
|
||||
#define LIN_CH_STATUS_RX_BUSY_Pos 9UL
|
||||
#define LIN_CH_STATUS_RX_BUSY_Msk 0x200UL
|
||||
#define LIN_CH_STATUS_TX_DONE_Pos 12UL
|
||||
#define LIN_CH_STATUS_TX_DONE_Msk 0x1000UL
|
||||
#define LIN_CH_STATUS_RX_DONE_Pos 13UL
|
||||
#define LIN_CH_STATUS_RX_DONE_Msk 0x2000UL
|
||||
#define LIN_CH_STATUS_TX_HEADER_BIT_ERROR_Pos 16UL
|
||||
#define LIN_CH_STATUS_TX_HEADER_BIT_ERROR_Msk 0x10000UL
|
||||
#define LIN_CH_STATUS_TX_RESPONSE_BIT_ERROR_Pos 17UL
|
||||
#define LIN_CH_STATUS_TX_RESPONSE_BIT_ERROR_Msk 0x20000UL
|
||||
#define LIN_CH_STATUS_RX_HEADER_FRAME_ERROR_Pos 24UL
|
||||
#define LIN_CH_STATUS_RX_HEADER_FRAME_ERROR_Msk 0x1000000UL
|
||||
#define LIN_CH_STATUS_RX_HEADER_SYNC_ERROR_Pos 25UL
|
||||
#define LIN_CH_STATUS_RX_HEADER_SYNC_ERROR_Msk 0x2000000UL
|
||||
#define LIN_CH_STATUS_RX_HEADER_PARITY_ERROR_Pos 26UL
|
||||
#define LIN_CH_STATUS_RX_HEADER_PARITY_ERROR_Msk 0x4000000UL
|
||||
#define LIN_CH_STATUS_RX_RESPONSE_FRAME_ERROR_Pos 27UL
|
||||
#define LIN_CH_STATUS_RX_RESPONSE_FRAME_ERROR_Msk 0x8000000UL
|
||||
#define LIN_CH_STATUS_RX_RESPONSE_CHECKSUM_ERROR_Pos 28UL
|
||||
#define LIN_CH_STATUS_RX_RESPONSE_CHECKSUM_ERROR_Msk 0x10000000UL
|
||||
/* LIN_CH.CMD */
|
||||
#define LIN_CH_CMD_TX_HEADER_Pos 0UL
|
||||
#define LIN_CH_CMD_TX_HEADER_Msk 0x1UL
|
||||
#define LIN_CH_CMD_TX_RESPONSE_Pos 1UL
|
||||
#define LIN_CH_CMD_TX_RESPONSE_Msk 0x2UL
|
||||
#define LIN_CH_CMD_TX_WAKEUP_Pos 2UL
|
||||
#define LIN_CH_CMD_TX_WAKEUP_Msk 0x4UL
|
||||
#define LIN_CH_CMD_RX_HEADER_Pos 8UL
|
||||
#define LIN_CH_CMD_RX_HEADER_Msk 0x100UL
|
||||
#define LIN_CH_CMD_RX_RESPONSE_Pos 9UL
|
||||
#define LIN_CH_CMD_RX_RESPONSE_Msk 0x200UL
|
||||
/* LIN_CH.TX_RX_STATUS */
|
||||
#define LIN_CH_TX_RX_STATUS_SYNC_COUNTER_Pos 0UL
|
||||
#define LIN_CH_TX_RX_STATUS_SYNC_COUNTER_Msk 0xFFUL
|
||||
#define LIN_CH_TX_RX_STATUS_TX_IN_Pos 16UL
|
||||
#define LIN_CH_TX_RX_STATUS_TX_IN_Msk 0x10000UL
|
||||
#define LIN_CH_TX_RX_STATUS_RX_IN_Pos 17UL
|
||||
#define LIN_CH_TX_RX_STATUS_RX_IN_Msk 0x20000UL
|
||||
#define LIN_CH_TX_RX_STATUS_TX_OUT_Pos 24UL
|
||||
#define LIN_CH_TX_RX_STATUS_TX_OUT_Msk 0x1000000UL
|
||||
#define LIN_CH_TX_RX_STATUS_EN_OUT_Pos 26UL
|
||||
#define LIN_CH_TX_RX_STATUS_EN_OUT_Msk 0x4000000UL
|
||||
/* LIN_CH.PID_CHECKSUM */
|
||||
#define LIN_CH_PID_CHECKSUM_PID_Pos 0UL
|
||||
#define LIN_CH_PID_CHECKSUM_PID_Msk 0xFFUL
|
||||
#define LIN_CH_PID_CHECKSUM_CHECKSUM_Pos 8UL
|
||||
#define LIN_CH_PID_CHECKSUM_CHECKSUM_Msk 0xFF00UL
|
||||
/* LIN_CH.DATA0 */
|
||||
#define LIN_CH_DATA0_DATA1_Pos 0UL
|
||||
#define LIN_CH_DATA0_DATA1_Msk 0xFFUL
|
||||
#define LIN_CH_DATA0_DATA2_Pos 8UL
|
||||
#define LIN_CH_DATA0_DATA2_Msk 0xFF00UL
|
||||
#define LIN_CH_DATA0_DATA3_Pos 16UL
|
||||
#define LIN_CH_DATA0_DATA3_Msk 0xFF0000UL
|
||||
#define LIN_CH_DATA0_DATA4_Pos 24UL
|
||||
#define LIN_CH_DATA0_DATA4_Msk 0xFF000000UL
|
||||
/* LIN_CH.DATA1 */
|
||||
#define LIN_CH_DATA1_DATA5_Pos 0UL
|
||||
#define LIN_CH_DATA1_DATA5_Msk 0xFFUL
|
||||
#define LIN_CH_DATA1_DATA6_Pos 8UL
|
||||
#define LIN_CH_DATA1_DATA6_Msk 0xFF00UL
|
||||
#define LIN_CH_DATA1_DATA7_Pos 16UL
|
||||
#define LIN_CH_DATA1_DATA7_Msk 0xFF0000UL
|
||||
#define LIN_CH_DATA1_DATA8_Pos 24UL
|
||||
#define LIN_CH_DATA1_DATA8_Msk 0xFF000000UL
|
||||
/* LIN_CH.INTR */
|
||||
#define LIN_CH_INTR_TX_HEADER_DONE_Pos 0UL
|
||||
#define LIN_CH_INTR_TX_HEADER_DONE_Msk 0x1UL
|
||||
#define LIN_CH_INTR_TX_RESPONSE_DONE_Pos 1UL
|
||||
#define LIN_CH_INTR_TX_RESPONSE_DONE_Msk 0x2UL
|
||||
#define LIN_CH_INTR_TX_WAKEUP_DONE_Pos 2UL
|
||||
#define LIN_CH_INTR_TX_WAKEUP_DONE_Msk 0x4UL
|
||||
#define LIN_CH_INTR_RX_HEADER_DONE_Pos 8UL
|
||||
#define LIN_CH_INTR_RX_HEADER_DONE_Msk 0x100UL
|
||||
#define LIN_CH_INTR_RX_RESPONSE_DONE_Pos 9UL
|
||||
#define LIN_CH_INTR_RX_RESPONSE_DONE_Msk 0x200UL
|
||||
#define LIN_CH_INTR_RX_BREAK_WAKEUP_DONE_Pos 10UL
|
||||
#define LIN_CH_INTR_RX_BREAK_WAKEUP_DONE_Msk 0x400UL
|
||||
#define LIN_CH_INTR_RX_HEADER_SYNC_DONE_Pos 11UL
|
||||
#define LIN_CH_INTR_RX_HEADER_SYNC_DONE_Msk 0x800UL
|
||||
#define LIN_CH_INTR_RX_NOISE_DETECT_Pos 13UL
|
||||
#define LIN_CH_INTR_RX_NOISE_DETECT_Msk 0x2000UL
|
||||
#define LIN_CH_INTR_TIMEOUT_Pos 14UL
|
||||
#define LIN_CH_INTR_TIMEOUT_Msk 0x4000UL
|
||||
#define LIN_CH_INTR_TX_HEADER_BIT_ERROR_Pos 16UL
|
||||
#define LIN_CH_INTR_TX_HEADER_BIT_ERROR_Msk 0x10000UL
|
||||
#define LIN_CH_INTR_TX_RESPONSE_BIT_ERROR_Pos 17UL
|
||||
#define LIN_CH_INTR_TX_RESPONSE_BIT_ERROR_Msk 0x20000UL
|
||||
#define LIN_CH_INTR_RX_HEADER_FRAME_ERROR_Pos 24UL
|
||||
#define LIN_CH_INTR_RX_HEADER_FRAME_ERROR_Msk 0x1000000UL
|
||||
#define LIN_CH_INTR_RX_HEADER_SYNC_ERROR_Pos 25UL
|
||||
#define LIN_CH_INTR_RX_HEADER_SYNC_ERROR_Msk 0x2000000UL
|
||||
#define LIN_CH_INTR_RX_HEADER_PARITY_ERROR_Pos 26UL
|
||||
#define LIN_CH_INTR_RX_HEADER_PARITY_ERROR_Msk 0x4000000UL
|
||||
#define LIN_CH_INTR_RX_RESPONSE_FRAME_ERROR_Pos 27UL
|
||||
#define LIN_CH_INTR_RX_RESPONSE_FRAME_ERROR_Msk 0x8000000UL
|
||||
#define LIN_CH_INTR_RX_RESPONSE_CHECKSUM_ERROR_Pos 28UL
|
||||
#define LIN_CH_INTR_RX_RESPONSE_CHECKSUM_ERROR_Msk 0x10000000UL
|
||||
/* LIN_CH.INTR_SET */
|
||||
#define LIN_CH_INTR_SET_TX_HEADER_DONE_Pos 0UL
|
||||
#define LIN_CH_INTR_SET_TX_HEADER_DONE_Msk 0x1UL
|
||||
#define LIN_CH_INTR_SET_TX_RESPONSE_DONE_Pos 1UL
|
||||
#define LIN_CH_INTR_SET_TX_RESPONSE_DONE_Msk 0x2UL
|
||||
#define LIN_CH_INTR_SET_TX_WAKEUP_DONE_Pos 2UL
|
||||
#define LIN_CH_INTR_SET_TX_WAKEUP_DONE_Msk 0x4UL
|
||||
#define LIN_CH_INTR_SET_RX_HEADER_DONE_Pos 8UL
|
||||
#define LIN_CH_INTR_SET_RX_HEADER_DONE_Msk 0x100UL
|
||||
#define LIN_CH_INTR_SET_RX_RESPONSE_DONE_Pos 9UL
|
||||
#define LIN_CH_INTR_SET_RX_RESPONSE_DONE_Msk 0x200UL
|
||||
#define LIN_CH_INTR_SET_RX_BREAK_WAKEUP_DONE_Pos 10UL
|
||||
#define LIN_CH_INTR_SET_RX_BREAK_WAKEUP_DONE_Msk 0x400UL
|
||||
#define LIN_CH_INTR_SET_RX_HEADER_SYNC_DONE_Pos 11UL
|
||||
#define LIN_CH_INTR_SET_RX_HEADER_SYNC_DONE_Msk 0x800UL
|
||||
#define LIN_CH_INTR_SET_RX_NOISE_DETECT_Pos 13UL
|
||||
#define LIN_CH_INTR_SET_RX_NOISE_DETECT_Msk 0x2000UL
|
||||
#define LIN_CH_INTR_SET_TIMEOUT_Pos 14UL
|
||||
#define LIN_CH_INTR_SET_TIMEOUT_Msk 0x4000UL
|
||||
#define LIN_CH_INTR_SET_TX_HEADER_BIT_ERROR_Pos 16UL
|
||||
#define LIN_CH_INTR_SET_TX_HEADER_BIT_ERROR_Msk 0x10000UL
|
||||
#define LIN_CH_INTR_SET_TX_RESPONSE_BIT_ERROR_Pos 17UL
|
||||
#define LIN_CH_INTR_SET_TX_RESPONSE_BIT_ERROR_Msk 0x20000UL
|
||||
#define LIN_CH_INTR_SET_RX_HEADER_FRAME_ERROR_Pos 24UL
|
||||
#define LIN_CH_INTR_SET_RX_HEADER_FRAME_ERROR_Msk 0x1000000UL
|
||||
#define LIN_CH_INTR_SET_RX_HEADER_SYNC_ERROR_Pos 25UL
|
||||
#define LIN_CH_INTR_SET_RX_HEADER_SYNC_ERROR_Msk 0x2000000UL
|
||||
#define LIN_CH_INTR_SET_RX_HEADER_PARITY_ERROR_Pos 26UL
|
||||
#define LIN_CH_INTR_SET_RX_HEADER_PARITY_ERROR_Msk 0x4000000UL
|
||||
#define LIN_CH_INTR_SET_RX_RESPONSE_FRAME_ERROR_Pos 27UL
|
||||
#define LIN_CH_INTR_SET_RX_RESPONSE_FRAME_ERROR_Msk 0x8000000UL
|
||||
#define LIN_CH_INTR_SET_RX_RESPONSE_CHECKSUM_ERROR_Pos 28UL
|
||||
#define LIN_CH_INTR_SET_RX_RESPONSE_CHECKSUM_ERROR_Msk 0x10000000UL
|
||||
/* LIN_CH.INTR_MASK */
|
||||
#define LIN_CH_INTR_MASK_TX_HEADER_DONE_Pos 0UL
|
||||
#define LIN_CH_INTR_MASK_TX_HEADER_DONE_Msk 0x1UL
|
||||
#define LIN_CH_INTR_MASK_TX_RESPONSE_DONE_Pos 1UL
|
||||
#define LIN_CH_INTR_MASK_TX_RESPONSE_DONE_Msk 0x2UL
|
||||
#define LIN_CH_INTR_MASK_TX_WAKEUP_DONE_Pos 2UL
|
||||
#define LIN_CH_INTR_MASK_TX_WAKEUP_DONE_Msk 0x4UL
|
||||
#define LIN_CH_INTR_MASK_RX_HEADER_DONE_Pos 8UL
|
||||
#define LIN_CH_INTR_MASK_RX_HEADER_DONE_Msk 0x100UL
|
||||
#define LIN_CH_INTR_MASK_RX_RESPONSE_DONE_Pos 9UL
|
||||
#define LIN_CH_INTR_MASK_RX_RESPONSE_DONE_Msk 0x200UL
|
||||
#define LIN_CH_INTR_MASK_RX_BREAK_WAKEUP_DONE_Pos 10UL
|
||||
#define LIN_CH_INTR_MASK_RX_BREAK_WAKEUP_DONE_Msk 0x400UL
|
||||
#define LIN_CH_INTR_MASK_RX_HEADER_SYNC_DONE_Pos 11UL
|
||||
#define LIN_CH_INTR_MASK_RX_HEADER_SYNC_DONE_Msk 0x800UL
|
||||
#define LIN_CH_INTR_MASK_RX_NOISE_DETECT_Pos 13UL
|
||||
#define LIN_CH_INTR_MASK_RX_NOISE_DETECT_Msk 0x2000UL
|
||||
#define LIN_CH_INTR_MASK_TIMEOUT_Pos 14UL
|
||||
#define LIN_CH_INTR_MASK_TIMEOUT_Msk 0x4000UL
|
||||
#define LIN_CH_INTR_MASK_TX_HEADER_BIT_ERROR_Pos 16UL
|
||||
#define LIN_CH_INTR_MASK_TX_HEADER_BIT_ERROR_Msk 0x10000UL
|
||||
#define LIN_CH_INTR_MASK_TX_RESPONSE_BIT_ERROR_Pos 17UL
|
||||
#define LIN_CH_INTR_MASK_TX_RESPONSE_BIT_ERROR_Msk 0x20000UL
|
||||
#define LIN_CH_INTR_MASK_RX_HEADER_FRAME_ERROR_Pos 24UL
|
||||
#define LIN_CH_INTR_MASK_RX_HEADER_FRAME_ERROR_Msk 0x1000000UL
|
||||
#define LIN_CH_INTR_MASK_RX_HEADER_SYNC_ERROR_Pos 25UL
|
||||
#define LIN_CH_INTR_MASK_RX_HEADER_SYNC_ERROR_Msk 0x2000000UL
|
||||
#define LIN_CH_INTR_MASK_RX_HEADER_PARITY_ERROR_Pos 26UL
|
||||
#define LIN_CH_INTR_MASK_RX_HEADER_PARITY_ERROR_Msk 0x4000000UL
|
||||
#define LIN_CH_INTR_MASK_RX_RESPONSE_FRAME_ERROR_Pos 27UL
|
||||
#define LIN_CH_INTR_MASK_RX_RESPONSE_FRAME_ERROR_Msk 0x8000000UL
|
||||
#define LIN_CH_INTR_MASK_RX_RESPONSE_CHECKSUM_ERROR_Pos 28UL
|
||||
#define LIN_CH_INTR_MASK_RX_RESPONSE_CHECKSUM_ERROR_Msk 0x10000000UL
|
||||
/* LIN_CH.INTR_MASKED */
|
||||
#define LIN_CH_INTR_MASKED_TX_HEADER_DONE_Pos 0UL
|
||||
#define LIN_CH_INTR_MASKED_TX_HEADER_DONE_Msk 0x1UL
|
||||
#define LIN_CH_INTR_MASKED_TX_RESPONSE_DONE_Pos 1UL
|
||||
#define LIN_CH_INTR_MASKED_TX_RESPONSE_DONE_Msk 0x2UL
|
||||
#define LIN_CH_INTR_MASKED_TX_WAKEUP_DONE_Pos 2UL
|
||||
#define LIN_CH_INTR_MASKED_TX_WAKEUP_DONE_Msk 0x4UL
|
||||
#define LIN_CH_INTR_MASKED_RX_HEADER_DONE_Pos 8UL
|
||||
#define LIN_CH_INTR_MASKED_RX_HEADER_DONE_Msk 0x100UL
|
||||
#define LIN_CH_INTR_MASKED_RX_RESPONSE_DONE_Pos 9UL
|
||||
#define LIN_CH_INTR_MASKED_RX_RESPONSE_DONE_Msk 0x200UL
|
||||
#define LIN_CH_INTR_MASKED_RX_BREAK_WAKEUP_DONE_Pos 10UL
|
||||
#define LIN_CH_INTR_MASKED_RX_BREAK_WAKEUP_DONE_Msk 0x400UL
|
||||
#define LIN_CH_INTR_MASKED_RX_HEADER_SYNC_DONE_Pos 11UL
|
||||
#define LIN_CH_INTR_MASKED_RX_HEADER_SYNC_DONE_Msk 0x800UL
|
||||
#define LIN_CH_INTR_MASKED_RX_NOISE_DETECT_Pos 13UL
|
||||
#define LIN_CH_INTR_MASKED_RX_NOISE_DETECT_Msk 0x2000UL
|
||||
#define LIN_CH_INTR_MASKED_TIMEOUT_Pos 14UL
|
||||
#define LIN_CH_INTR_MASKED_TIMEOUT_Msk 0x4000UL
|
||||
#define LIN_CH_INTR_MASKED_TX_HEADER_BIT_ERROR_Pos 16UL
|
||||
#define LIN_CH_INTR_MASKED_TX_HEADER_BIT_ERROR_Msk 0x10000UL
|
||||
#define LIN_CH_INTR_MASKED_TX_RESPONSE_BIT_ERROR_Pos 17UL
|
||||
#define LIN_CH_INTR_MASKED_TX_RESPONSE_BIT_ERROR_Msk 0x20000UL
|
||||
#define LIN_CH_INTR_MASKED_RX_HEADER_FRAME_ERROR_Pos 24UL
|
||||
#define LIN_CH_INTR_MASKED_RX_HEADER_FRAME_ERROR_Msk 0x1000000UL
|
||||
#define LIN_CH_INTR_MASKED_RX_HEADER_SYNC_ERROR_Pos 25UL
|
||||
#define LIN_CH_INTR_MASKED_RX_HEADER_SYNC_ERROR_Msk 0x2000000UL
|
||||
#define LIN_CH_INTR_MASKED_RX_HEADER_PARITY_ERROR_Pos 26UL
|
||||
#define LIN_CH_INTR_MASKED_RX_HEADER_PARITY_ERROR_Msk 0x4000000UL
|
||||
#define LIN_CH_INTR_MASKED_RX_RESPONSE_FRAME_ERROR_Pos 27UL
|
||||
#define LIN_CH_INTR_MASKED_RX_RESPONSE_FRAME_ERROR_Msk 0x8000000UL
|
||||
#define LIN_CH_INTR_MASKED_RX_RESPONSE_CHECKSUM_ERROR_Pos 28UL
|
||||
#define LIN_CH_INTR_MASKED_RX_RESPONSE_CHECKSUM_ERROR_Msk 0x10000000UL
|
||||
|
||||
|
||||
/* LIN.ERROR_CTL */
|
||||
#define LIN_ERROR_CTL_CH_IDX_Pos 0UL
|
||||
#define LIN_ERROR_CTL_CH_IDX_Msk 0x1FUL
|
||||
#define LIN_ERROR_CTL_TX_SYNC_ERROR_Pos 16UL
|
||||
#define LIN_ERROR_CTL_TX_SYNC_ERROR_Msk 0x10000UL
|
||||
#define LIN_ERROR_CTL_TX_SYNC_STOP_ERROR_Pos 17UL
|
||||
#define LIN_ERROR_CTL_TX_SYNC_STOP_ERROR_Msk 0x20000UL
|
||||
#define LIN_ERROR_CTL_TX_PARITY_ERROR_Pos 18UL
|
||||
#define LIN_ERROR_CTL_TX_PARITY_ERROR_Msk 0x40000UL
|
||||
#define LIN_ERROR_CTL_TX_PID_STOP_ERROR_Pos 19UL
|
||||
#define LIN_ERROR_CTL_TX_PID_STOP_ERROR_Msk 0x80000UL
|
||||
#define LIN_ERROR_CTL_TX_DATA_STOP_ERROR_Pos 21UL
|
||||
#define LIN_ERROR_CTL_TX_DATA_STOP_ERROR_Msk 0x200000UL
|
||||
#define LIN_ERROR_CTL_TX_CHECKSUM_ERROR_Pos 22UL
|
||||
#define LIN_ERROR_CTL_TX_CHECKSUM_ERROR_Msk 0x400000UL
|
||||
#define LIN_ERROR_CTL_TX_CHECKSUM_STOP_ERROR_Pos 23UL
|
||||
#define LIN_ERROR_CTL_TX_CHECKSUM_STOP_ERROR_Msk 0x800000UL
|
||||
#define LIN_ERROR_CTL_ENABLED_Pos 31UL
|
||||
#define LIN_ERROR_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* LIN.TEST_CTL */
|
||||
#define LIN_TEST_CTL_CH_IDX_Pos 0UL
|
||||
#define LIN_TEST_CTL_CH_IDX_Msk 0x1FUL
|
||||
#define LIN_TEST_CTL_MODE_Pos 16UL
|
||||
#define LIN_TEST_CTL_MODE_Msk 0x10000UL
|
||||
#define LIN_TEST_CTL_ENABLED_Pos 31UL
|
||||
#define LIN_TEST_CTL_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_LIN_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,967 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_pass.h
|
||||
*
|
||||
* \brief
|
||||
* PASS IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PASS_H_
|
||||
#define _CYIP_PASS_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_SAR_CH_SECTION_SIZE 0x00000040UL
|
||||
#define PASS_SAR_SECTION_SIZE 0x00001000UL
|
||||
#define PASS_EPASS_MMIO_SECTION_SIZE 0x00001000UL
|
||||
#define PASS_SECTION_SIZE 0x00100000UL
|
||||
|
||||
/**
|
||||
* \brief Trigger control. (PASS_SAR_CH_TR_CTL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_TR_CTL_field {
|
||||
uint32_t u3SEL:3;
|
||||
uint32_t :1;
|
||||
uint32_t u3PRIO:3;
|
||||
uint32_t :1;
|
||||
uint32_t u2PREEMPT_TYPE:2;
|
||||
uint32_t :1;
|
||||
uint32_t u1GROUP_END:1;
|
||||
uint32_t :19;
|
||||
uint32_t u1DONE_LEVEL:1;
|
||||
} stc_PASS_SAR_CH_TR_CTL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_TR_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_TR_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_TR_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Sample control. (PASS_SAR_CH_SAMPLE_CTL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_SAMPLE_CTL_field {
|
||||
uint32_t u6PIN_ADDR:6;
|
||||
uint32_t u2PORT_ADDR:2;
|
||||
uint32_t u3EXT_MUX_SEL:3;
|
||||
uint32_t u1EXT_MUX_EN:1;
|
||||
uint32_t u2PRECOND_MODE:2;
|
||||
uint32_t u2OVERLAP_DIAG:2;
|
||||
uint32_t u12SAMPLE_TIME:12;
|
||||
uint32_t :3;
|
||||
uint32_t u1ALT_CAL:1;
|
||||
} stc_PASS_SAR_CH_SAMPLE_CTL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_SAMPLE_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_SAMPLE_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_SAMPLE_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Post processing control (PASS_SAR_CH_POST_CTL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_POST_CTL_field {
|
||||
uint32_t u3POST_PROC:3;
|
||||
uint32_t :3;
|
||||
uint32_t u1LEFT_ALIGN:1;
|
||||
uint32_t u1SIGN_EXT:1;
|
||||
uint32_t u8AVG_CNT:8;
|
||||
uint32_t u5SHIFT_R:5;
|
||||
uint32_t :1;
|
||||
uint32_t u2RANGE_MODE:2;
|
||||
uint32_t :1;
|
||||
uint32_t u1TR_DONE_GRP_VIO:1;
|
||||
uint32_t :6;
|
||||
} stc_PASS_SAR_CH_POST_CTL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_POST_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_POST_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_POST_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Range thresholds (PASS_SAR_CH_RANGE_CTL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_RANGE_CTL_field {
|
||||
uint32_t u16RANGE_LO:16;
|
||||
uint32_t u16RANGE_HI:16;
|
||||
} stc_PASS_SAR_CH_RANGE_CTL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_RANGE_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_RANGE_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_RANGE_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt request register. (PASS_SAR_CH_INTR)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_INTR_field {
|
||||
uint32_t u1GRP_DONE:1;
|
||||
uint32_t u1GRP_CANCELLED:1;
|
||||
uint32_t u1GRP_OVERFLOW:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1CH_RANGE:1;
|
||||
uint32_t u1CH_PULSE:1;
|
||||
uint32_t u1CH_OVERFLOW:1;
|
||||
uint32_t :21;
|
||||
} stc_PASS_SAR_CH_INTR_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt set request register (PASS_SAR_CH_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_INTR_SET_field {
|
||||
uint32_t u1GRP_DONE_SET:1;
|
||||
uint32_t u1GRP_CANCELLED_SET:1;
|
||||
uint32_t u1GRP_OVERFLOW_SET:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1CH_RANGE_SET:1;
|
||||
uint32_t u1CH_PULSE_SET:1;
|
||||
uint32_t u1CH_OVERFLOW_SET:1;
|
||||
uint32_t :21;
|
||||
} stc_PASS_SAR_CH_INTR_SET_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt mask register. (PASS_SAR_CH_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_INTR_MASK_field {
|
||||
uint32_t u1GRP_DONE_MASK:1;
|
||||
uint32_t u1GRP_CANCELLED_MASK:1;
|
||||
uint32_t u1GRP_OVERFLOW_MASK:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1CH_RANGE_MASK:1;
|
||||
uint32_t u1CH_PULSE_MASK:1;
|
||||
uint32_t u1CH_OVERFLOW_MASK:1;
|
||||
uint32_t :21;
|
||||
} stc_PASS_SAR_CH_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt masked request register (PASS_SAR_CH_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_INTR_MASKED_field {
|
||||
uint32_t u1GRP_DONE_MASKED:1;
|
||||
uint32_t u1GRP_CANCELLED_MASKED:1;
|
||||
uint32_t u1GRP_OVERFLOW_MASKED:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1CH_RANGE_MASKED:1;
|
||||
uint32_t u1CH_PULSE_MASKED:1;
|
||||
uint32_t u1CH_OVERFLOW_MASKED:1;
|
||||
uint32_t :21;
|
||||
} stc_PASS_SAR_CH_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_INTR_MASKED_t;
|
||||
|
||||
/**
|
||||
* \brief Working data register (PASS_SAR_CH_WORK)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_WORK_field {
|
||||
uint32_t u16WORK:16;
|
||||
uint32_t :12;
|
||||
uint32_t u1ABOVE_HI_MIR:1;
|
||||
uint32_t u1RANGE_MIR:1;
|
||||
uint32_t u1PULSE_MIR:1;
|
||||
uint32_t u1VALID_MIR:1;
|
||||
} stc_PASS_SAR_CH_WORK_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_WORK {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_WORK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_WORK_t;
|
||||
|
||||
/**
|
||||
* \brief Result data register (PASS_SAR_CH_RESULT)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_RESULT_field {
|
||||
uint32_t u16RESULT:16;
|
||||
uint32_t :12;
|
||||
uint32_t u1ABOVE_HI_MIR:1;
|
||||
uint32_t u1RANGE_INTR_MIR:1;
|
||||
uint32_t u1PULSE_INTR_MIR:1;
|
||||
uint32_t u1VALID_MIR:1;
|
||||
} stc_PASS_SAR_CH_RESULT_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_RESULT {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_RESULT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_RESULT_t;
|
||||
|
||||
/**
|
||||
* \brief Group status register (PASS_SAR_CH_GRP_STAT)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_GRP_STAT_field {
|
||||
uint32_t u1GRP_COMPLETE:1;
|
||||
uint32_t u1GRP_CANCELLED:1;
|
||||
uint32_t u1GRP_OVERFLOW:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1CH_RANGE_COMPLETE:1;
|
||||
uint32_t u1CH_PULSE_COMPLETE:1;
|
||||
uint32_t u1CH_OVERFLOW:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1GRP_BUSY:1;
|
||||
uint32_t :15;
|
||||
} stc_PASS_SAR_CH_GRP_STAT_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_GRP_STAT {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_GRP_STAT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_GRP_STAT_t;
|
||||
|
||||
/**
|
||||
* \brief Enable register (PASS_SAR_CH_ENABLE)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_ENABLE_field {
|
||||
uint32_t u1CHAN_EN:1;
|
||||
uint32_t :31;
|
||||
} stc_PASS_SAR_CH_ENABLE_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_ENABLE {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_ENABLE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_ENABLE_t;
|
||||
|
||||
/**
|
||||
* \brief Software triggers (PASS_SAR_CH_TR_CMD)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH_TR_CMD_field {
|
||||
uint32_t u1START:1;
|
||||
uint32_t :31;
|
||||
} stc_PASS_SAR_CH_TR_CMD_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CH_TR_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CH_TR_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CH_TR_CMD_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Analog control register. (PASS_SAR_CTL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CTL_field {
|
||||
uint32_t u8PWRUP_TIME:8;
|
||||
uint32_t u1IDLE_PWRDWN:1;
|
||||
uint32_t u1MSB_STRETCH:1;
|
||||
uint32_t u1HALF_LSB:1;
|
||||
uint32_t :18;
|
||||
uint32_t u1SARMUX_EN:1;
|
||||
uint32_t u1ADC_EN:1;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_PASS_SAR_CTL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Diagnostic Reference control register. (PASS_SAR_DIAG_CTL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_DIAG_CTL_field {
|
||||
uint32_t u4DIAG_SEL:4;
|
||||
uint32_t :27;
|
||||
uint32_t u1DIAG_EN:1;
|
||||
} stc_PASS_SAR_DIAG_CTL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_DIAG_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_DIAG_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_DIAG_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Preconditioning control register. (PASS_SAR_PRECOND_CTL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_PRECOND_CTL_field {
|
||||
uint32_t u4PRECOND_TIME:4;
|
||||
uint32_t :28;
|
||||
} stc_PASS_SAR_PRECOND_CTL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_PRECOND_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_PRECOND_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_PRECOND_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Current analog calibration values (PASS_SAR_ANA_CAL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_ANA_CAL_field {
|
||||
uint32_t u8AOFFSET:8;
|
||||
uint32_t :8;
|
||||
uint32_t u5AGAIN:5;
|
||||
uint32_t :11;
|
||||
} stc_PASS_SAR_ANA_CAL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_ANA_CAL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_ANA_CAL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_ANA_CAL_t;
|
||||
|
||||
/**
|
||||
* \brief Current digital calibration values (PASS_SAR_DIG_CAL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_DIG_CAL_field {
|
||||
uint32_t u12DOFFSET:12;
|
||||
uint32_t :4;
|
||||
uint32_t u6DGAIN:6;
|
||||
uint32_t :10;
|
||||
} stc_PASS_SAR_DIG_CAL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_DIG_CAL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_DIG_CAL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_DIG_CAL_t;
|
||||
|
||||
/**
|
||||
* \brief Alternate analog calibration values (PASS_SAR_ANA_CAL_ALT)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_ANA_CAL_ALT_field {
|
||||
uint32_t u8AOFFSET:8;
|
||||
uint32_t :8;
|
||||
uint32_t u5AGAIN:5;
|
||||
uint32_t :11;
|
||||
} stc_PASS_SAR_ANA_CAL_ALT_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_ANA_CAL_ALT {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_ANA_CAL_ALT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_ANA_CAL_ALT_t;
|
||||
|
||||
/**
|
||||
* \brief Alternate digital calibration values (PASS_SAR_DIG_CAL_ALT)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_DIG_CAL_ALT_field {
|
||||
uint32_t u12DOFFSET:12;
|
||||
uint32_t :4;
|
||||
uint32_t u6DGAIN:6;
|
||||
uint32_t :10;
|
||||
} stc_PASS_SAR_DIG_CAL_ALT_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_DIG_CAL_ALT {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_DIG_CAL_ALT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_DIG_CAL_ALT_t;
|
||||
|
||||
/**
|
||||
* \brief Calibration update command (PASS_SAR_CAL_UPD_CMD)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CAL_UPD_CMD_field {
|
||||
uint32_t u1UPDATE:1;
|
||||
uint32_t :31;
|
||||
} stc_PASS_SAR_CAL_UPD_CMD_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_CAL_UPD_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_CAL_UPD_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_CAL_UPD_CMD_t;
|
||||
|
||||
/**
|
||||
* \brief Trigger pending status (PASS_SAR_TR_PEND)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_TR_PEND_field {
|
||||
uint32_t u32TR_PEND:32;
|
||||
} stc_PASS_SAR_TR_PEND_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_TR_PEND {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_TR_PEND_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_TR_PEND_t;
|
||||
|
||||
/**
|
||||
* \brief Channel working data register 'valid' bits (PASS_SAR_WORK_VALID)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_WORK_VALID_field {
|
||||
uint32_t u32WORK_VALID:32;
|
||||
} stc_PASS_SAR_WORK_VALID_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_WORK_VALID {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_WORK_VALID_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_WORK_VALID_t;
|
||||
|
||||
/**
|
||||
* \brief Range detected (PASS_SAR_WORK_RANGE)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_WORK_RANGE_field {
|
||||
uint32_t u32RANGE:32;
|
||||
} stc_PASS_SAR_WORK_RANGE_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_WORK_RANGE {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_WORK_RANGE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_WORK_RANGE_t;
|
||||
|
||||
/**
|
||||
* \brief Range detect above Hi flag (PASS_SAR_WORK_RANGE_HI)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_WORK_RANGE_HI_field {
|
||||
uint32_t u32ABOVE_HI:32;
|
||||
} stc_PASS_SAR_WORK_RANGE_HI_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_WORK_RANGE_HI {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_WORK_RANGE_HI_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_WORK_RANGE_HI_t;
|
||||
|
||||
/**
|
||||
* \brief Pulse detected (PASS_SAR_WORK_PULSE)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_WORK_PULSE_field {
|
||||
uint32_t u32PULSE:32;
|
||||
} stc_PASS_SAR_WORK_PULSE_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_WORK_PULSE {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_WORK_PULSE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_WORK_PULSE_t;
|
||||
|
||||
/**
|
||||
* \brief Channel result data register 'valid' bits (PASS_SAR_RESULT_VALID)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_RESULT_VALID_field {
|
||||
uint32_t u32RESULT_VALID:32;
|
||||
} stc_PASS_SAR_RESULT_VALID_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_RESULT_VALID {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_RESULT_VALID_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_RESULT_VALID_t;
|
||||
|
||||
/**
|
||||
* \brief Channel Range above Hi flags (PASS_SAR_RESULT_RANGE_HI)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_RESULT_RANGE_HI_field {
|
||||
uint32_t u32ABOVE_HI:32;
|
||||
} stc_PASS_SAR_RESULT_RANGE_HI_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_RESULT_RANGE_HI {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_RESULT_RANGE_HI_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_RESULT_RANGE_HI_t;
|
||||
|
||||
/**
|
||||
* \brief Current status of internal SAR registers (mostly for debug) (PASS_SAR_STATUS)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_STATUS_field {
|
||||
uint32_t u5CUR_CHAN:5;
|
||||
uint32_t :3;
|
||||
uint32_t u3CUR_PRIO:3;
|
||||
uint32_t :1;
|
||||
uint32_t u2CUR_PREEMPT_TYPE:2;
|
||||
uint32_t :15;
|
||||
uint32_t u1DBG_FREEZE:1;
|
||||
uint32_t u1PWRUP_BUSY:1;
|
||||
uint32_t u1BUSY:1;
|
||||
} stc_PASS_SAR_STATUS_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Current averaging status (for debug) (PASS_SAR_AVG_STAT)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_AVG_STAT_field {
|
||||
uint32_t u20CUR_AVG_ACCU:20;
|
||||
uint32_t :4;
|
||||
uint32_t u8CUR_AVG_CNT:8;
|
||||
} stc_PASS_SAR_AVG_STAT_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_AVG_STAT {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_AVG_STAT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_AVG_STAT_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief PASS control register (PASS_PASS_CTL)
|
||||
*/
|
||||
typedef struct stc_PASS_PASS_CTL_field {
|
||||
uint32_t u1SUPPLY_MON_EN_A:1;
|
||||
uint32_t u1SUPPLY_MON_LVL_A:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1SUPPLY_MON_EN_B:1;
|
||||
uint32_t u1SUPPLY_MON_LVL_B:1;
|
||||
uint32_t :15;
|
||||
uint32_t u2REFBUF_MODE:2;
|
||||
uint32_t :5;
|
||||
uint32_t u4DBG_FREEZE_EN:4;
|
||||
} stc_PASS_PASS_CTL_field_t;
|
||||
|
||||
typedef union un_PASS_PASS_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_PASS_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_PASS_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief per SAR generic input trigger select (PASS_SAR_TR_IN_SEL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_TR_IN_SEL_field {
|
||||
uint32_t u4IN0_SEL:4;
|
||||
uint32_t u4IN1_SEL:4;
|
||||
uint32_t u4IN2_SEL:4;
|
||||
uint32_t u4IN3_SEL:4;
|
||||
uint32_t u4IN4_SEL:4;
|
||||
uint32_t :12;
|
||||
} stc_PASS_SAR_TR_IN_SEL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_TR_IN_SEL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_TR_IN_SEL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_TR_IN_SEL_t;
|
||||
|
||||
/**
|
||||
* \brief per SAR generic output trigger select (PASS_SAR_TR_OUT_SEL)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_TR_OUT_SEL_field {
|
||||
uint32_t u6OUT0_SEL:6;
|
||||
uint32_t :2;
|
||||
uint32_t u6OUT1_SEL:6;
|
||||
uint32_t :18;
|
||||
} stc_PASS_SAR_TR_OUT_SEL_field_t;
|
||||
|
||||
typedef union un_PASS_SAR_TR_OUT_SEL {
|
||||
uint32_t u32Register;
|
||||
stc_PASS_SAR_TR_OUT_SEL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PASS_SAR_TR_OUT_SEL_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Channel structure (PASS_SAR_CH)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR_CH {
|
||||
un_PASS_SAR_CH_TR_CTL_t unTR_CTL; /*!< 0x00000000 Trigger control. */
|
||||
un_PASS_SAR_CH_SAMPLE_CTL_t unSAMPLE_CTL; /*!< 0x00000004 Sample control. */
|
||||
un_PASS_SAR_CH_POST_CTL_t unPOST_CTL; /*!< 0x00000008 Post processing control */
|
||||
un_PASS_SAR_CH_RANGE_CTL_t unRANGE_CTL; /*!< 0x0000000C Range thresholds */
|
||||
un_PASS_SAR_CH_INTR_t unINTR; /*!< 0x00000010 Interrupt request register. */
|
||||
un_PASS_SAR_CH_INTR_SET_t unINTR_SET; /*!< 0x00000014 Interrupt set request register */
|
||||
un_PASS_SAR_CH_INTR_MASK_t unINTR_MASK; /*!< 0x00000018 Interrupt mask register. */
|
||||
un_PASS_SAR_CH_INTR_MASKED_t unINTR_MASKED; /*!< 0x0000001C Interrupt masked request register */
|
||||
un_PASS_SAR_CH_WORK_t unWORK; /*!< 0x00000020 Working data register */
|
||||
un_PASS_SAR_CH_RESULT_t unRESULT; /*!< 0x00000024 Result data register */
|
||||
un_PASS_SAR_CH_GRP_STAT_t unGRP_STAT; /*!< 0x00000028 Group status register */
|
||||
uint32_t au32Reserved[3];
|
||||
un_PASS_SAR_CH_ENABLE_t unENABLE; /*!< 0x00000038 Enable register */
|
||||
un_PASS_SAR_CH_TR_CMD_t unTR_CMD; /*!< 0x0000003C Software triggers */
|
||||
} stc_PASS_SAR_CH_t; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief SAR ADC with Sequencer for S40E (PASS_SAR)
|
||||
*/
|
||||
typedef struct stc_PASS_SAR {
|
||||
un_PASS_SAR_CTL_t unCTL; /*!< 0x00000000 Analog control register. */
|
||||
un_PASS_SAR_DIAG_CTL_t unDIAG_CTL; /*!< 0x00000004 Diagnostic Reference control register. */
|
||||
uint32_t au32Reserved[2];
|
||||
un_PASS_SAR_PRECOND_CTL_t unPRECOND_CTL; /*!< 0x00000010 Preconditioning control register. */
|
||||
uint32_t au32Reserved1[27];
|
||||
un_PASS_SAR_ANA_CAL_t unANA_CAL; /*!< 0x00000080 Current analog calibration values */
|
||||
un_PASS_SAR_DIG_CAL_t unDIG_CAL; /*!< 0x00000084 Current digital calibration values */
|
||||
uint32_t au32Reserved2[2];
|
||||
un_PASS_SAR_ANA_CAL_ALT_t unANA_CAL_ALT; /*!< 0x00000090 Alternate analog calibration values */
|
||||
un_PASS_SAR_DIG_CAL_ALT_t unDIG_CAL_ALT; /*!< 0x00000094 Alternate digital calibration values */
|
||||
un_PASS_SAR_CAL_UPD_CMD_t unCAL_UPD_CMD; /*!< 0x00000098 Calibration update command */
|
||||
uint32_t au32Reserved3[25];
|
||||
un_PASS_SAR_TR_PEND_t unTR_PEND; /*!< 0x00000100 Trigger pending status */
|
||||
uint32_t au32Reserved4[31];
|
||||
un_PASS_SAR_WORK_VALID_t unWORK_VALID; /*!< 0x00000180 Channel working data register 'valid' bits */
|
||||
un_PASS_SAR_WORK_RANGE_t unWORK_RANGE; /*!< 0x00000184 Range detected */
|
||||
un_PASS_SAR_WORK_RANGE_HI_t unWORK_RANGE_HI; /*!< 0x00000188 Range detect above Hi flag */
|
||||
un_PASS_SAR_WORK_PULSE_t unWORK_PULSE; /*!< 0x0000018C Pulse detected */
|
||||
uint32_t au32Reserved5[4];
|
||||
un_PASS_SAR_RESULT_VALID_t unRESULT_VALID; /*!< 0x000001A0 Channel result data register 'valid' bits */
|
||||
un_PASS_SAR_RESULT_RANGE_HI_t unRESULT_RANGE_HI; /*!< 0x000001A4 Channel Range above Hi flags */
|
||||
uint32_t au32Reserved6[22];
|
||||
un_PASS_SAR_STATUS_t unSTATUS; /*!< 0x00000200 Current status of internal SAR registers (mostly for
|
||||
debug) */
|
||||
un_PASS_SAR_AVG_STAT_t unAVG_STAT; /*!< 0x00000204 Current averaging status (for debug) */
|
||||
uint32_t au32Reserved7[382];
|
||||
stc_PASS_SAR_CH_t CH[32]; /*!< 0x00000800 Channel structure */
|
||||
} stc_PASS_SAR_t; /*!< Size = 4096 (0x1000) */
|
||||
|
||||
/**
|
||||
* \brief PASS top-level MMIO (Generic Triggers) (PASS_EPASS_MMIO)
|
||||
*/
|
||||
typedef struct stc_PASS_EPASS_MMIO {
|
||||
un_PASS_PASS_CTL_t unPASS_CTL; /*!< 0x00000000 PASS control register */
|
||||
uint32_t au32Reserved[7];
|
||||
un_PASS_SAR_TR_IN_SEL_t unSAR_TR_IN_SEL[4]; /*!< 0x00000020 per SAR generic input trigger select */
|
||||
uint32_t au32Reserved1[4];
|
||||
un_PASS_SAR_TR_OUT_SEL_t unSAR_TR_OUT_SEL[4]; /*!< 0x00000040 per SAR generic output trigger select */
|
||||
uint32_t au32Reserved2[1004];
|
||||
} stc_PASS_EPASS_MMIO_t; /*!< Size = 4096 (0x1000) */
|
||||
|
||||
/**
|
||||
* \brief Programmable Analog Subsystem for S40E (PASS)
|
||||
*/
|
||||
typedef struct stc_PASS {
|
||||
stc_PASS_SAR_t SAR[4]; /*!< 0x00000000 SAR ADC with Sequencer for S40E */
|
||||
uint32_t au32Reserved[241664];
|
||||
stc_PASS_EPASS_MMIO_t EPASS_MMIO; /*!< 0x000F0000 PASS top-level MMIO (Generic Triggers) */
|
||||
} stc_PASS_t; /*!< Size = 987136 (0xF1000) */
|
||||
|
||||
|
||||
/* PASS_SAR_CH.TR_CTL */
|
||||
#define PASS_SAR_CH_TR_CTL_SEL_Pos 0UL
|
||||
#define PASS_SAR_CH_TR_CTL_SEL_Msk 0x7UL
|
||||
#define PASS_SAR_CH_TR_CTL_PRIO_Pos 4UL
|
||||
#define PASS_SAR_CH_TR_CTL_PRIO_Msk 0x70UL
|
||||
#define PASS_SAR_CH_TR_CTL_PREEMPT_TYPE_Pos 8UL
|
||||
#define PASS_SAR_CH_TR_CTL_PREEMPT_TYPE_Msk 0x300UL
|
||||
#define PASS_SAR_CH_TR_CTL_GROUP_END_Pos 11UL
|
||||
#define PASS_SAR_CH_TR_CTL_GROUP_END_Msk 0x800UL
|
||||
#define PASS_SAR_CH_TR_CTL_DONE_LEVEL_Pos 31UL
|
||||
#define PASS_SAR_CH_TR_CTL_DONE_LEVEL_Msk 0x80000000UL
|
||||
/* PASS_SAR_CH.SAMPLE_CTL */
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_PIN_ADDR_Pos 0UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_PIN_ADDR_Msk 0x3FUL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_PORT_ADDR_Pos 6UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_PORT_ADDR_Msk 0xC0UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_EXT_MUX_SEL_Pos 8UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_EXT_MUX_SEL_Msk 0x700UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_EXT_MUX_EN_Pos 11UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_EXT_MUX_EN_Msk 0x800UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_PRECOND_MODE_Pos 12UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_PRECOND_MODE_Msk 0x3000UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_OVERLAP_DIAG_Pos 14UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_OVERLAP_DIAG_Msk 0xC000UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_SAMPLE_TIME_Pos 16UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_SAMPLE_TIME_Msk 0xFFF0000UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_ALT_CAL_Pos 31UL
|
||||
#define PASS_SAR_CH_SAMPLE_CTL_ALT_CAL_Msk 0x80000000UL
|
||||
/* PASS_SAR_CH.POST_CTL */
|
||||
#define PASS_SAR_CH_POST_CTL_POST_PROC_Pos 0UL
|
||||
#define PASS_SAR_CH_POST_CTL_POST_PROC_Msk 0x7UL
|
||||
#define PASS_SAR_CH_POST_CTL_LEFT_ALIGN_Pos 6UL
|
||||
#define PASS_SAR_CH_POST_CTL_LEFT_ALIGN_Msk 0x40UL
|
||||
#define PASS_SAR_CH_POST_CTL_SIGN_EXT_Pos 7UL
|
||||
#define PASS_SAR_CH_POST_CTL_SIGN_EXT_Msk 0x80UL
|
||||
#define PASS_SAR_CH_POST_CTL_AVG_CNT_Pos 8UL
|
||||
#define PASS_SAR_CH_POST_CTL_AVG_CNT_Msk 0xFF00UL
|
||||
#define PASS_SAR_CH_POST_CTL_SHIFT_R_Pos 16UL
|
||||
#define PASS_SAR_CH_POST_CTL_SHIFT_R_Msk 0x1F0000UL
|
||||
#define PASS_SAR_CH_POST_CTL_RANGE_MODE_Pos 22UL
|
||||
#define PASS_SAR_CH_POST_CTL_RANGE_MODE_Msk 0xC00000UL
|
||||
#define PASS_SAR_CH_POST_CTL_TR_DONE_GRP_VIO_Pos 25UL
|
||||
#define PASS_SAR_CH_POST_CTL_TR_DONE_GRP_VIO_Msk 0x2000000UL
|
||||
/* PASS_SAR_CH.RANGE_CTL */
|
||||
#define PASS_SAR_CH_RANGE_CTL_RANGE_LO_Pos 0UL
|
||||
#define PASS_SAR_CH_RANGE_CTL_RANGE_LO_Msk 0xFFFFUL
|
||||
#define PASS_SAR_CH_RANGE_CTL_RANGE_HI_Pos 16UL
|
||||
#define PASS_SAR_CH_RANGE_CTL_RANGE_HI_Msk 0xFFFF0000UL
|
||||
/* PASS_SAR_CH.INTR */
|
||||
#define PASS_SAR_CH_INTR_GRP_DONE_Pos 0UL
|
||||
#define PASS_SAR_CH_INTR_GRP_DONE_Msk 0x1UL
|
||||
#define PASS_SAR_CH_INTR_GRP_CANCELLED_Pos 1UL
|
||||
#define PASS_SAR_CH_INTR_GRP_CANCELLED_Msk 0x2UL
|
||||
#define PASS_SAR_CH_INTR_GRP_OVERFLOW_Pos 2UL
|
||||
#define PASS_SAR_CH_INTR_GRP_OVERFLOW_Msk 0x4UL
|
||||
#define PASS_SAR_CH_INTR_CH_RANGE_Pos 8UL
|
||||
#define PASS_SAR_CH_INTR_CH_RANGE_Msk 0x100UL
|
||||
#define PASS_SAR_CH_INTR_CH_PULSE_Pos 9UL
|
||||
#define PASS_SAR_CH_INTR_CH_PULSE_Msk 0x200UL
|
||||
#define PASS_SAR_CH_INTR_CH_OVERFLOW_Pos 10UL
|
||||
#define PASS_SAR_CH_INTR_CH_OVERFLOW_Msk 0x400UL
|
||||
/* PASS_SAR_CH.INTR_SET */
|
||||
#define PASS_SAR_CH_INTR_SET_GRP_DONE_SET_Pos 0UL
|
||||
#define PASS_SAR_CH_INTR_SET_GRP_DONE_SET_Msk 0x1UL
|
||||
#define PASS_SAR_CH_INTR_SET_GRP_CANCELLED_SET_Pos 1UL
|
||||
#define PASS_SAR_CH_INTR_SET_GRP_CANCELLED_SET_Msk 0x2UL
|
||||
#define PASS_SAR_CH_INTR_SET_GRP_OVERFLOW_SET_Pos 2UL
|
||||
#define PASS_SAR_CH_INTR_SET_GRP_OVERFLOW_SET_Msk 0x4UL
|
||||
#define PASS_SAR_CH_INTR_SET_CH_RANGE_SET_Pos 8UL
|
||||
#define PASS_SAR_CH_INTR_SET_CH_RANGE_SET_Msk 0x100UL
|
||||
#define PASS_SAR_CH_INTR_SET_CH_PULSE_SET_Pos 9UL
|
||||
#define PASS_SAR_CH_INTR_SET_CH_PULSE_SET_Msk 0x200UL
|
||||
#define PASS_SAR_CH_INTR_SET_CH_OVERFLOW_SET_Pos 10UL
|
||||
#define PASS_SAR_CH_INTR_SET_CH_OVERFLOW_SET_Msk 0x400UL
|
||||
/* PASS_SAR_CH.INTR_MASK */
|
||||
#define PASS_SAR_CH_INTR_MASK_GRP_DONE_MASK_Pos 0UL
|
||||
#define PASS_SAR_CH_INTR_MASK_GRP_DONE_MASK_Msk 0x1UL
|
||||
#define PASS_SAR_CH_INTR_MASK_GRP_CANCELLED_MASK_Pos 1UL
|
||||
#define PASS_SAR_CH_INTR_MASK_GRP_CANCELLED_MASK_Msk 0x2UL
|
||||
#define PASS_SAR_CH_INTR_MASK_GRP_OVERFLOW_MASK_Pos 2UL
|
||||
#define PASS_SAR_CH_INTR_MASK_GRP_OVERFLOW_MASK_Msk 0x4UL
|
||||
#define PASS_SAR_CH_INTR_MASK_CH_RANGE_MASK_Pos 8UL
|
||||
#define PASS_SAR_CH_INTR_MASK_CH_RANGE_MASK_Msk 0x100UL
|
||||
#define PASS_SAR_CH_INTR_MASK_CH_PULSE_MASK_Pos 9UL
|
||||
#define PASS_SAR_CH_INTR_MASK_CH_PULSE_MASK_Msk 0x200UL
|
||||
#define PASS_SAR_CH_INTR_MASK_CH_OVERFLOW_MASK_Pos 10UL
|
||||
#define PASS_SAR_CH_INTR_MASK_CH_OVERFLOW_MASK_Msk 0x400UL
|
||||
/* PASS_SAR_CH.INTR_MASKED */
|
||||
#define PASS_SAR_CH_INTR_MASKED_GRP_DONE_MASKED_Pos 0UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_GRP_DONE_MASKED_Msk 0x1UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_GRP_CANCELLED_MASKED_Pos 1UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_GRP_CANCELLED_MASKED_Msk 0x2UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_GRP_OVERFLOW_MASKED_Pos 2UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_GRP_OVERFLOW_MASKED_Msk 0x4UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_CH_RANGE_MASKED_Pos 8UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_CH_RANGE_MASKED_Msk 0x100UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_CH_PULSE_MASKED_Pos 9UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_CH_PULSE_MASKED_Msk 0x200UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_CH_OVERFLOW_MASKED_Pos 10UL
|
||||
#define PASS_SAR_CH_INTR_MASKED_CH_OVERFLOW_MASKED_Msk 0x400UL
|
||||
/* PASS_SAR_CH.WORK */
|
||||
#define PASS_SAR_CH_WORK_WORK_Pos 0UL
|
||||
#define PASS_SAR_CH_WORK_WORK_Msk 0xFFFFUL
|
||||
#define PASS_SAR_CH_WORK_ABOVE_HI_MIR_Pos 28UL
|
||||
#define PASS_SAR_CH_WORK_ABOVE_HI_MIR_Msk 0x10000000UL
|
||||
#define PASS_SAR_CH_WORK_RANGE_MIR_Pos 29UL
|
||||
#define PASS_SAR_CH_WORK_RANGE_MIR_Msk 0x20000000UL
|
||||
#define PASS_SAR_CH_WORK_PULSE_MIR_Pos 30UL
|
||||
#define PASS_SAR_CH_WORK_PULSE_MIR_Msk 0x40000000UL
|
||||
#define PASS_SAR_CH_WORK_VALID_MIR_Pos 31UL
|
||||
#define PASS_SAR_CH_WORK_VALID_MIR_Msk 0x80000000UL
|
||||
/* PASS_SAR_CH.RESULT */
|
||||
#define PASS_SAR_CH_RESULT_RESULT_Pos 0UL
|
||||
#define PASS_SAR_CH_RESULT_RESULT_Msk 0xFFFFUL
|
||||
#define PASS_SAR_CH_RESULT_ABOVE_HI_MIR_Pos 28UL
|
||||
#define PASS_SAR_CH_RESULT_ABOVE_HI_MIR_Msk 0x10000000UL
|
||||
#define PASS_SAR_CH_RESULT_RANGE_INTR_MIR_Pos 29UL
|
||||
#define PASS_SAR_CH_RESULT_RANGE_INTR_MIR_Msk 0x20000000UL
|
||||
#define PASS_SAR_CH_RESULT_PULSE_INTR_MIR_Pos 30UL
|
||||
#define PASS_SAR_CH_RESULT_PULSE_INTR_MIR_Msk 0x40000000UL
|
||||
#define PASS_SAR_CH_RESULT_VALID_MIR_Pos 31UL
|
||||
#define PASS_SAR_CH_RESULT_VALID_MIR_Msk 0x80000000UL
|
||||
/* PASS_SAR_CH.GRP_STAT */
|
||||
#define PASS_SAR_CH_GRP_STAT_GRP_COMPLETE_Pos 0UL
|
||||
#define PASS_SAR_CH_GRP_STAT_GRP_COMPLETE_Msk 0x1UL
|
||||
#define PASS_SAR_CH_GRP_STAT_GRP_CANCELLED_Pos 1UL
|
||||
#define PASS_SAR_CH_GRP_STAT_GRP_CANCELLED_Msk 0x2UL
|
||||
#define PASS_SAR_CH_GRP_STAT_GRP_OVERFLOW_Pos 2UL
|
||||
#define PASS_SAR_CH_GRP_STAT_GRP_OVERFLOW_Msk 0x4UL
|
||||
#define PASS_SAR_CH_GRP_STAT_CH_RANGE_COMPLETE_Pos 8UL
|
||||
#define PASS_SAR_CH_GRP_STAT_CH_RANGE_COMPLETE_Msk 0x100UL
|
||||
#define PASS_SAR_CH_GRP_STAT_CH_PULSE_COMPLETE_Pos 9UL
|
||||
#define PASS_SAR_CH_GRP_STAT_CH_PULSE_COMPLETE_Msk 0x200UL
|
||||
#define PASS_SAR_CH_GRP_STAT_CH_OVERFLOW_Pos 10UL
|
||||
#define PASS_SAR_CH_GRP_STAT_CH_OVERFLOW_Msk 0x400UL
|
||||
#define PASS_SAR_CH_GRP_STAT_GRP_BUSY_Pos 16UL
|
||||
#define PASS_SAR_CH_GRP_STAT_GRP_BUSY_Msk 0x10000UL
|
||||
/* PASS_SAR_CH.ENABLE */
|
||||
#define PASS_SAR_CH_ENABLE_CHAN_EN_Pos 0UL
|
||||
#define PASS_SAR_CH_ENABLE_CHAN_EN_Msk 0x1UL
|
||||
/* PASS_SAR_CH.TR_CMD */
|
||||
#define PASS_SAR_CH_TR_CMD_START_Pos 0UL
|
||||
#define PASS_SAR_CH_TR_CMD_START_Msk 0x1UL
|
||||
|
||||
|
||||
/* PASS_SAR.CTL */
|
||||
#define PASS_SAR_CTL_PWRUP_TIME_Pos 0UL
|
||||
#define PASS_SAR_CTL_PWRUP_TIME_Msk 0xFFUL
|
||||
#define PASS_SAR_CTL_IDLE_PWRDWN_Pos 8UL
|
||||
#define PASS_SAR_CTL_IDLE_PWRDWN_Msk 0x100UL
|
||||
#define PASS_SAR_CTL_MSB_STRETCH_Pos 9UL
|
||||
#define PASS_SAR_CTL_MSB_STRETCH_Msk 0x200UL
|
||||
#define PASS_SAR_CTL_HALF_LSB_Pos 10UL
|
||||
#define PASS_SAR_CTL_HALF_LSB_Msk 0x400UL
|
||||
#define PASS_SAR_CTL_SARMUX_EN_Pos 29UL
|
||||
#define PASS_SAR_CTL_SARMUX_EN_Msk 0x20000000UL
|
||||
#define PASS_SAR_CTL_ADC_EN_Pos 30UL
|
||||
#define PASS_SAR_CTL_ADC_EN_Msk 0x40000000UL
|
||||
#define PASS_SAR_CTL_ENABLED_Pos 31UL
|
||||
#define PASS_SAR_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* PASS_SAR.DIAG_CTL */
|
||||
#define PASS_SAR_DIAG_CTL_DIAG_SEL_Pos 0UL
|
||||
#define PASS_SAR_DIAG_CTL_DIAG_SEL_Msk 0xFUL
|
||||
#define PASS_SAR_DIAG_CTL_DIAG_EN_Pos 31UL
|
||||
#define PASS_SAR_DIAG_CTL_DIAG_EN_Msk 0x80000000UL
|
||||
/* PASS_SAR.PRECOND_CTL */
|
||||
#define PASS_SAR_PRECOND_CTL_PRECOND_TIME_Pos 0UL
|
||||
#define PASS_SAR_PRECOND_CTL_PRECOND_TIME_Msk 0xFUL
|
||||
/* PASS_SAR.ANA_CAL */
|
||||
#define PASS_SAR_ANA_CAL_AOFFSET_Pos 0UL
|
||||
#define PASS_SAR_ANA_CAL_AOFFSET_Msk 0xFFUL
|
||||
#define PASS_SAR_ANA_CAL_AGAIN_Pos 16UL
|
||||
#define PASS_SAR_ANA_CAL_AGAIN_Msk 0x1F0000UL
|
||||
/* PASS_SAR.DIG_CAL */
|
||||
#define PASS_SAR_DIG_CAL_DOFFSET_Pos 0UL
|
||||
#define PASS_SAR_DIG_CAL_DOFFSET_Msk 0xFFFUL
|
||||
#define PASS_SAR_DIG_CAL_DGAIN_Pos 16UL
|
||||
#define PASS_SAR_DIG_CAL_DGAIN_Msk 0x3F0000UL
|
||||
/* PASS_SAR.ANA_CAL_ALT */
|
||||
#define PASS_SAR_ANA_CAL_ALT_AOFFSET_Pos 0UL
|
||||
#define PASS_SAR_ANA_CAL_ALT_AOFFSET_Msk 0xFFUL
|
||||
#define PASS_SAR_ANA_CAL_ALT_AGAIN_Pos 16UL
|
||||
#define PASS_SAR_ANA_CAL_ALT_AGAIN_Msk 0x1F0000UL
|
||||
/* PASS_SAR.DIG_CAL_ALT */
|
||||
#define PASS_SAR_DIG_CAL_ALT_DOFFSET_Pos 0UL
|
||||
#define PASS_SAR_DIG_CAL_ALT_DOFFSET_Msk 0xFFFUL
|
||||
#define PASS_SAR_DIG_CAL_ALT_DGAIN_Pos 16UL
|
||||
#define PASS_SAR_DIG_CAL_ALT_DGAIN_Msk 0x3F0000UL
|
||||
/* PASS_SAR.CAL_UPD_CMD */
|
||||
#define PASS_SAR_CAL_UPD_CMD_UPDATE_Pos 0UL
|
||||
#define PASS_SAR_CAL_UPD_CMD_UPDATE_Msk 0x1UL
|
||||
/* PASS_SAR.TR_PEND */
|
||||
#define PASS_SAR_TR_PEND_TR_PEND_Pos 0UL
|
||||
#define PASS_SAR_TR_PEND_TR_PEND_Msk 0xFFFFFFFFUL
|
||||
/* PASS_SAR.WORK_VALID */
|
||||
#define PASS_SAR_WORK_VALID_WORK_VALID_Pos 0UL
|
||||
#define PASS_SAR_WORK_VALID_WORK_VALID_Msk 0xFFFFFFFFUL
|
||||
/* PASS_SAR.WORK_RANGE */
|
||||
#define PASS_SAR_WORK_RANGE_RANGE_Pos 0UL
|
||||
#define PASS_SAR_WORK_RANGE_RANGE_Msk 0xFFFFFFFFUL
|
||||
/* PASS_SAR.WORK_RANGE_HI */
|
||||
#define PASS_SAR_WORK_RANGE_HI_ABOVE_HI_Pos 0UL
|
||||
#define PASS_SAR_WORK_RANGE_HI_ABOVE_HI_Msk 0xFFFFFFFFUL
|
||||
/* PASS_SAR.WORK_PULSE */
|
||||
#define PASS_SAR_WORK_PULSE_PULSE_Pos 0UL
|
||||
#define PASS_SAR_WORK_PULSE_PULSE_Msk 0xFFFFFFFFUL
|
||||
/* PASS_SAR.RESULT_VALID */
|
||||
#define PASS_SAR_RESULT_VALID_RESULT_VALID_Pos 0UL
|
||||
#define PASS_SAR_RESULT_VALID_RESULT_VALID_Msk 0xFFFFFFFFUL
|
||||
/* PASS_SAR.RESULT_RANGE_HI */
|
||||
#define PASS_SAR_RESULT_RANGE_HI_ABOVE_HI_Pos 0UL
|
||||
#define PASS_SAR_RESULT_RANGE_HI_ABOVE_HI_Msk 0xFFFFFFFFUL
|
||||
/* PASS_SAR.STATUS */
|
||||
#define PASS_SAR_STATUS_CUR_CHAN_Pos 0UL
|
||||
#define PASS_SAR_STATUS_CUR_CHAN_Msk 0x1FUL
|
||||
#define PASS_SAR_STATUS_CUR_PRIO_Pos 8UL
|
||||
#define PASS_SAR_STATUS_CUR_PRIO_Msk 0x700UL
|
||||
#define PASS_SAR_STATUS_CUR_PREEMPT_TYPE_Pos 12UL
|
||||
#define PASS_SAR_STATUS_CUR_PREEMPT_TYPE_Msk 0x3000UL
|
||||
#define PASS_SAR_STATUS_DBG_FREEZE_Pos 29UL
|
||||
#define PASS_SAR_STATUS_DBG_FREEZE_Msk 0x20000000UL
|
||||
#define PASS_SAR_STATUS_PWRUP_BUSY_Pos 30UL
|
||||
#define PASS_SAR_STATUS_PWRUP_BUSY_Msk 0x40000000UL
|
||||
#define PASS_SAR_STATUS_BUSY_Pos 31UL
|
||||
#define PASS_SAR_STATUS_BUSY_Msk 0x80000000UL
|
||||
/* PASS_SAR.AVG_STAT */
|
||||
#define PASS_SAR_AVG_STAT_CUR_AVG_ACCU_Pos 0UL
|
||||
#define PASS_SAR_AVG_STAT_CUR_AVG_ACCU_Msk 0xFFFFFUL
|
||||
#define PASS_SAR_AVG_STAT_CUR_AVG_CNT_Pos 24UL
|
||||
#define PASS_SAR_AVG_STAT_CUR_AVG_CNT_Msk 0xFF000000UL
|
||||
|
||||
|
||||
/* PASS_EPASS_MMIO.PASS_CTL */
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_EN_A_Pos 0UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_EN_A_Msk 0x1UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_LVL_A_Pos 1UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_LVL_A_Msk 0x2UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_EN_B_Pos 4UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_EN_B_Msk 0x10UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_LVL_B_Pos 5UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_SUPPLY_MON_LVL_B_Msk 0x20UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_REFBUF_MODE_Pos 21UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_REFBUF_MODE_Msk 0x600000UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_DBG_FREEZE_EN_Pos 28UL
|
||||
#define PASS_EPASS_MMIO_PASS_CTL_DBG_FREEZE_EN_Msk 0xF0000000UL
|
||||
/* PASS_EPASS_MMIO.SAR_TR_IN_SEL */
|
||||
#define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN0_SEL_Pos 0UL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN0_SEL_Msk 0xFUL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN1_SEL_Pos 4UL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN1_SEL_Msk 0xF0UL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN2_SEL_Pos 8UL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN2_SEL_Msk 0xF00UL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN3_SEL_Pos 12UL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN3_SEL_Msk 0xF000UL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN4_SEL_Pos 16UL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_IN_SEL_IN4_SEL_Msk 0xF0000UL
|
||||
/* PASS_EPASS_MMIO.SAR_TR_OUT_SEL */
|
||||
#define PASS_EPASS_MMIO_SAR_TR_OUT_SEL_OUT0_SEL_Pos 0UL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_OUT_SEL_OUT0_SEL_Msk 0x3FUL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_OUT_SEL_OUT1_SEL_Pos 8UL
|
||||
#define PASS_EPASS_MMIO_SAR_TR_OUT_SEL_OUT1_SEL_Msk 0x3F00UL
|
||||
|
||||
|
||||
#endif /* _CYIP_PASS_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,208 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_peri_pclk_v3.h
|
||||
*
|
||||
* \brief
|
||||
* PERI_PCLK IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PERI_PCLK_V3_H_
|
||||
#define _CYIP_PERI_PCLK_V3_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI_PCLK
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_PCLK_GR_SECTION_SIZE 0x00002000UL
|
||||
#define PERI_PCLK_SECTION_SIZE 0x00020000UL
|
||||
|
||||
/**
|
||||
* \brief Divider command (PERI_PCLK_GR_DIV_CMD)
|
||||
*/
|
||||
typedef struct stc_PERI_PCLK_GR_DIV_CMD_field {
|
||||
uint32_t u8DIV_SEL:8;
|
||||
uint32_t u2TYPE_SEL:2;
|
||||
uint32_t :6;
|
||||
uint32_t u8PA_DIV_SEL:8;
|
||||
uint32_t u2PA_TYPE_SEL:2;
|
||||
uint32_t :4;
|
||||
uint32_t u1DISABLE:1;
|
||||
uint32_t u1ENABLE:1;
|
||||
} stc_PERI_PCLK_GR_DIV_CMD_field_t;
|
||||
|
||||
typedef union un_PERI_PCLK_GR_DIV_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_PCLK_GR_DIV_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_PCLK_GR_DIV_CMD_t;
|
||||
|
||||
/**
|
||||
* \brief Clock control (PERI_PCLK_GR_CLOCK_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_PCLK_GR_CLOCK_CTL_field {
|
||||
uint32_t u8DIV_SEL:8;
|
||||
uint32_t u2TYPE_SEL:2;
|
||||
uint32_t :22;
|
||||
} stc_PERI_PCLK_GR_CLOCK_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_PCLK_GR_CLOCK_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_PCLK_GR_CLOCK_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_PCLK_GR_CLOCK_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Divider control (for 8.0 divider) (PERI_PCLK_GR_DIV_8_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_PCLK_GR_DIV_8_CTL_field {
|
||||
uint32_t u1EN:1;
|
||||
uint32_t :7;
|
||||
uint32_t u8INT8_DIV:8;
|
||||
uint32_t :16;
|
||||
} stc_PERI_PCLK_GR_DIV_8_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_PCLK_GR_DIV_8_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_PCLK_GR_DIV_8_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_PCLK_GR_DIV_8_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Divider control (for 16.0 divider) (PERI_PCLK_GR_DIV_16_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_PCLK_GR_DIV_16_CTL_field {
|
||||
uint32_t u1EN:1;
|
||||
uint32_t :7;
|
||||
uint32_t u16INT16_DIV:16;
|
||||
uint32_t :8;
|
||||
} stc_PERI_PCLK_GR_DIV_16_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_PCLK_GR_DIV_16_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_PCLK_GR_DIV_16_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_PCLK_GR_DIV_16_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Divider control (for 16.5 divider) (PERI_PCLK_GR_DIV_16_5_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_PCLK_GR_DIV_16_5_CTL_field {
|
||||
uint32_t u1EN:1;
|
||||
uint32_t :2;
|
||||
uint32_t u5FRAC5_DIV:5;
|
||||
uint32_t u16INT16_DIV:16;
|
||||
uint32_t :8;
|
||||
} stc_PERI_PCLK_GR_DIV_16_5_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_PCLK_GR_DIV_16_5_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_PCLK_GR_DIV_16_5_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_PCLK_GR_DIV_16_5_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Divider control (for 24.5 divider) (PERI_PCLK_GR_DIV_24_5_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_PCLK_GR_DIV_24_5_CTL_field {
|
||||
uint32_t u1EN:1;
|
||||
uint32_t :2;
|
||||
uint32_t u5FRAC5_DIV:5;
|
||||
uint32_t u24INT24_DIV:24;
|
||||
} stc_PERI_PCLK_GR_DIV_24_5_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_PCLK_GR_DIV_24_5_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_PCLK_GR_DIV_24_5_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_PCLK_GR_DIV_24_5_CTL_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief PERI clock domains (PERI_PCLK_GR)
|
||||
*/
|
||||
typedef struct stc_PERI_PCLK_GR {
|
||||
un_PERI_PCLK_GR_DIV_CMD_t unDIV_CMD; /*!< 0x00000000 Divider command */
|
||||
uint32_t au32Reserved[767];
|
||||
un_PERI_PCLK_GR_CLOCK_CTL_t unCLOCK_CTL[256]; /*!< 0x00000C00 Clock control */
|
||||
un_PERI_PCLK_GR_DIV_8_CTL_t unDIV_8_CTL[256]; /*!< 0x00001000 Divider control (for 8.0 divider) */
|
||||
un_PERI_PCLK_GR_DIV_16_CTL_t unDIV_16_CTL[256]; /*!< 0x00001400 Divider control (for 16.0 divider) */
|
||||
un_PERI_PCLK_GR_DIV_16_5_CTL_t unDIV_16_5_CTL[256]; /*!< 0x00001800 Divider control (for 16.5 divider) */
|
||||
un_PERI_PCLK_GR_DIV_24_5_CTL_t unDIV_24_5_CTL[255]; /*!< 0x00001C00 Divider control (for 24.5 divider) */
|
||||
uint32_t u32Reserved1;
|
||||
} stc_PERI_PCLK_GR_t; /*!< Size = 8192 (0x2000) */
|
||||
|
||||
/**
|
||||
* \brief Peripheral PCLK groups (PERI_PCLK)
|
||||
*/
|
||||
typedef struct stc_PERI_PCLK {
|
||||
stc_PERI_PCLK_GR_t GR[16]; /*!< 0x00000000 PERI clock domains */
|
||||
} stc_PERI_PCLK_t; /*!< Size = 131072 (0x20000) */
|
||||
|
||||
|
||||
/* PERI_PCLK_GR.DIV_CMD */
|
||||
#define PERI_PCLK_GR_DIV_CMD_DIV_SEL_Pos 0UL
|
||||
#define PERI_PCLK_GR_DIV_CMD_DIV_SEL_Msk 0xFFUL
|
||||
#define PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos 8UL
|
||||
#define PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Msk 0x300UL
|
||||
#define PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Pos 16UL
|
||||
#define PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk 0xFF0000UL
|
||||
#define PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Pos 24UL
|
||||
#define PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk 0x3000000UL
|
||||
#define PERI_PCLK_GR_DIV_CMD_DISABLE_Pos 30UL
|
||||
#define PERI_PCLK_GR_DIV_CMD_DISABLE_Msk 0x40000000UL
|
||||
#define PERI_PCLK_GR_DIV_CMD_ENABLE_Pos 31UL
|
||||
#define PERI_PCLK_GR_DIV_CMD_ENABLE_Msk 0x80000000UL
|
||||
/* PERI_PCLK_GR.CLOCK_CTL */
|
||||
#define PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Pos 0UL
|
||||
#define PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Msk 0xFFUL
|
||||
#define PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Pos 8UL
|
||||
#define PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Msk 0x300UL
|
||||
/* PERI_PCLK_GR.DIV_8_CTL */
|
||||
#define PERI_PCLK_GR_DIV_8_CTL_EN_Pos 0UL
|
||||
#define PERI_PCLK_GR_DIV_8_CTL_EN_Msk 0x1UL
|
||||
#define PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Pos 8UL
|
||||
#define PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Msk 0xFF00UL
|
||||
/* PERI_PCLK_GR.DIV_16_CTL */
|
||||
#define PERI_PCLK_GR_DIV_16_CTL_EN_Pos 0UL
|
||||
#define PERI_PCLK_GR_DIV_16_CTL_EN_Msk 0x1UL
|
||||
#define PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Pos 8UL
|
||||
#define PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Msk 0xFFFF00UL
|
||||
/* PERI_PCLK_GR.DIV_16_5_CTL */
|
||||
#define PERI_PCLK_GR_DIV_16_5_CTL_EN_Pos 0UL
|
||||
#define PERI_PCLK_GR_DIV_16_5_CTL_EN_Msk 0x1UL
|
||||
#define PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Pos 3UL
|
||||
#define PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Msk 0xF8UL
|
||||
#define PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Pos 8UL
|
||||
#define PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Msk 0xFFFF00UL
|
||||
/* PERI_PCLK_GR.DIV_24_5_CTL */
|
||||
#define PERI_PCLK_GR_DIV_24_5_CTL_EN_Pos 0UL
|
||||
#define PERI_PCLK_GR_DIV_24_5_CTL_EN_Msk 0x1UL
|
||||
#define PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Pos 3UL
|
||||
#define PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Msk 0xF8UL
|
||||
#define PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Pos 8UL
|
||||
#define PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Msk 0xFFFFFF00UL
|
||||
|
||||
|
||||
#endif /* _CYIP_PERI_PCLK_V3_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,310 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_peri_v3.h
|
||||
*
|
||||
* \brief
|
||||
* PERI IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PERI_V3_H_
|
||||
#define _CYIP_PERI_V3_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_GR_SECTION_SIZE 0x00000040UL
|
||||
#define PERI_TR_GR_SECTION_SIZE 0x00000400UL
|
||||
#define PERI_TR_1TO1_GR_SECTION_SIZE 0x00000400UL
|
||||
#define PERI_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Clock control (PERI_GR_CLOCK_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_GR_CLOCK_CTL_field {
|
||||
uint32_t :8;
|
||||
uint32_t u8INT8_DIV:8;
|
||||
uint32_t :16;
|
||||
} stc_PERI_GR_CLOCK_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_GR_CLOCK_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_GR_CLOCK_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_GR_CLOCK_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Slave control (PERI_GR_SL_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_GR_SL_CTL_field {
|
||||
uint32_t u1ENABLED_0:1;
|
||||
uint32_t u1ENABLED_1:1;
|
||||
uint32_t u1ENABLED_2:1;
|
||||
uint32_t u1ENABLED_3:1;
|
||||
uint32_t u1ENABLED_4:1;
|
||||
uint32_t u1ENABLED_5:1;
|
||||
uint32_t u1ENABLED_6:1;
|
||||
uint32_t u1ENABLED_7:1;
|
||||
uint32_t u1ENABLED_8:1;
|
||||
uint32_t u1ENABLED_9:1;
|
||||
uint32_t u1ENABLED_10:1;
|
||||
uint32_t u1ENABLED_11:1;
|
||||
uint32_t u1ENABLED_12:1;
|
||||
uint32_t u1ENABLED_13:1;
|
||||
uint32_t u1ENABLED_14:1;
|
||||
uint32_t u1ENABLED_15:1;
|
||||
uint32_t :16;
|
||||
} stc_PERI_GR_SL_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_GR_SL_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_GR_SL_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_GR_SL_CTL_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Trigger control register (PERI_TR_GR_TR_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_TR_GR_TR_CTL_field {
|
||||
uint32_t u8TR_SEL:8;
|
||||
uint32_t u1TR_INV:1;
|
||||
uint32_t u1TR_EDGE:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1DBG_FREEZE_EN:1;
|
||||
uint32_t :19;
|
||||
} stc_PERI_TR_GR_TR_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_TR_GR_TR_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_TR_GR_TR_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_TR_GR_TR_CTL_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Trigger control register (PERI_TR_1TO1_GR_TR_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_TR_1TO1_GR_TR_CTL_field {
|
||||
uint32_t u1TR_SEL:1;
|
||||
uint32_t :7;
|
||||
uint32_t u1TR_INV:1;
|
||||
uint32_t u1TR_EDGE:1;
|
||||
uint32_t :2;
|
||||
uint32_t u1DBG_FREEZE_EN:1;
|
||||
uint32_t :19;
|
||||
} stc_PERI_TR_1TO1_GR_TR_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_TR_1TO1_GR_TR_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_TR_1TO1_GR_TR_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_TR_1TO1_GR_TR_CTL_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Timeout control (PERI_TIMEOUT_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_TIMEOUT_CTL_field {
|
||||
uint32_t u16TIMEOUT:16;
|
||||
uint32_t :16;
|
||||
} stc_PERI_TIMEOUT_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_TIMEOUT_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_TIMEOUT_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_TIMEOUT_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Trigger command (PERI_TR_CMD)
|
||||
*/
|
||||
typedef struct stc_PERI_TR_CMD_field {
|
||||
uint32_t u8TR_SEL:8;
|
||||
uint32_t u5GROUP_SEL:5;
|
||||
uint32_t :16;
|
||||
uint32_t u1TR_EDGE:1;
|
||||
uint32_t u1OUT_SEL:1;
|
||||
uint32_t u1ACTIVATE:1;
|
||||
} stc_PERI_TR_CMD_field_t;
|
||||
|
||||
typedef union un_PERI_TR_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_TR_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_TR_CMD_t;
|
||||
|
||||
/**
|
||||
* \brief ECC control (PERI_ECC_CTL)
|
||||
*/
|
||||
typedef struct stc_PERI_ECC_CTL_field {
|
||||
uint32_t u11WORD_ADDR:11;
|
||||
uint32_t :5;
|
||||
uint32_t u1ECC_EN:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1ECC_INJ_EN:1;
|
||||
uint32_t :5;
|
||||
uint32_t u8PARITY:8;
|
||||
} stc_PERI_ECC_CTL_field_t;
|
||||
|
||||
typedef union un_PERI_ECC_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PERI_ECC_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PERI_ECC_CTL_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR)
|
||||
*/
|
||||
typedef struct stc_PERI_GR {
|
||||
un_PERI_GR_CLOCK_CTL_t unCLOCK_CTL; /*!< 0x00000000 Clock control */
|
||||
uint32_t au32Reserved[3];
|
||||
un_PERI_GR_SL_CTL_t unSL_CTL; /*!< 0x00000010 Slave control */
|
||||
uint32_t au32Reserved1[11];
|
||||
} stc_PERI_GR_t; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR)
|
||||
*/
|
||||
typedef struct stc_PERI_TR_GR {
|
||||
un_PERI_TR_GR_TR_CTL_t unTR_CTL[256]; /*!< 0x00000000 Trigger control register */
|
||||
} stc_PERI_TR_GR_t; /*!< Size = 1024 (0x400) */
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR)
|
||||
*/
|
||||
typedef struct stc_PERI_TR_1TO1_GR {
|
||||
un_PERI_TR_1TO1_GR_TR_CTL_t unTR_CTL[256]; /*!< 0x00000000 Trigger control register */
|
||||
} stc_PERI_TR_1TO1_GR_t; /*!< Size = 1024 (0x400) */
|
||||
|
||||
/**
|
||||
* \brief Peripheral interconnect (PERI)
|
||||
*/
|
||||
typedef struct stc_PERI {
|
||||
uint32_t au32Reserved[128];
|
||||
un_PERI_TIMEOUT_CTL_t unTIMEOUT_CTL; /*!< 0x00000200 Timeout control */
|
||||
uint32_t au32Reserved1[7];
|
||||
un_PERI_TR_CMD_t unTR_CMD; /*!< 0x00000220 Trigger command */
|
||||
uint32_t au32Reserved2[1911];
|
||||
un_PERI_ECC_CTL_t unECC_CTL; /*!< 0x00002000 ECC control */
|
||||
uint32_t au32Reserved3[2047];
|
||||
stc_PERI_GR_t GR[16]; /*!< 0x00004000 Peripheral group structure */
|
||||
uint32_t au32Reserved4[3840];
|
||||
stc_PERI_TR_GR_t TR_GR[16]; /*!< 0x00008000 Trigger group */
|
||||
stc_PERI_TR_1TO1_GR_t TR_1TO1_GR[16]; /*!< 0x0000C000 Trigger 1-to-1 group */
|
||||
} stc_PERI_t; /*!< Size = 65536 (0x10000) */
|
||||
|
||||
|
||||
/* PERI_GR.CLOCK_CTL */
|
||||
#define PERI_GR_CLOCK_CTL_INT8_DIV_Pos 8UL
|
||||
#define PERI_GR_CLOCK_CTL_INT8_DIV_Msk 0xFF00UL
|
||||
/* PERI_GR.SL_CTL */
|
||||
#define PERI_GR_SL_CTL_ENABLED_0_Pos 0UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_0_Msk 0x1UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_1_Pos 1UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_1_Msk 0x2UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_2_Pos 2UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_2_Msk 0x4UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_3_Pos 3UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_3_Msk 0x8UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_4_Pos 4UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_4_Msk 0x10UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_5_Pos 5UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_5_Msk 0x20UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_6_Pos 6UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_6_Msk 0x40UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_7_Pos 7UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_7_Msk 0x80UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_8_Pos 8UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_8_Msk 0x100UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_9_Pos 9UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_9_Msk 0x200UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_10_Pos 10UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_10_Msk 0x400UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_11_Pos 11UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_11_Msk 0x800UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_12_Pos 12UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_12_Msk 0x1000UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_13_Pos 13UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_13_Msk 0x2000UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_14_Pos 14UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_14_Msk 0x4000UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_15_Pos 15UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_15_Msk 0x8000UL
|
||||
|
||||
|
||||
/* PERI_TR_GR.TR_CTL */
|
||||
#define PERI_TR_GR_TR_CTL_TR_SEL_Pos 0UL
|
||||
#define PERI_TR_GR_TR_CTL_TR_SEL_Msk 0xFFUL
|
||||
#define PERI_TR_GR_TR_CTL_TR_INV_Pos 8UL
|
||||
#define PERI_TR_GR_TR_CTL_TR_INV_Msk 0x100UL
|
||||
#define PERI_TR_GR_TR_CTL_TR_EDGE_Pos 9UL
|
||||
#define PERI_TR_GR_TR_CTL_TR_EDGE_Msk 0x200UL
|
||||
#define PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Pos 12UL
|
||||
#define PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Msk 0x1000UL
|
||||
|
||||
|
||||
/* PERI_TR_1TO1_GR.TR_CTL */
|
||||
#define PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Pos 0UL
|
||||
#define PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Msk 0x1UL
|
||||
#define PERI_TR_1TO1_GR_TR_CTL_TR_INV_Pos 8UL
|
||||
#define PERI_TR_1TO1_GR_TR_CTL_TR_INV_Msk 0x100UL
|
||||
#define PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Pos 9UL
|
||||
#define PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Msk 0x200UL
|
||||
#define PERI_TR_1TO1_GR_TR_CTL_DBG_FREEZE_EN_Pos 12UL
|
||||
#define PERI_TR_1TO1_GR_TR_CTL_DBG_FREEZE_EN_Msk 0x1000UL
|
||||
|
||||
|
||||
/* PERI.TIMEOUT_CTL */
|
||||
#define PERI_TIMEOUT_CTL_TIMEOUT_Pos 0UL
|
||||
#define PERI_TIMEOUT_CTL_TIMEOUT_Msk 0xFFFFUL
|
||||
/* PERI.TR_CMD */
|
||||
#define PERI_TR_CMD_TR_SEL_Pos 0UL
|
||||
#define PERI_TR_CMD_TR_SEL_Msk 0xFFUL
|
||||
#define PERI_TR_CMD_GROUP_SEL_Pos 8UL
|
||||
#define PERI_TR_CMD_GROUP_SEL_Msk 0x1F00UL
|
||||
#define PERI_TR_CMD_TR_EDGE_Pos 29UL
|
||||
#define PERI_TR_CMD_TR_EDGE_Msk 0x20000000UL
|
||||
#define PERI_TR_CMD_OUT_SEL_Pos 30UL
|
||||
#define PERI_TR_CMD_OUT_SEL_Msk 0x40000000UL
|
||||
#define PERI_TR_CMD_ACTIVATE_Pos 31UL
|
||||
#define PERI_TR_CMD_ACTIVATE_Msk 0x80000000UL
|
||||
/* PERI.ECC_CTL */
|
||||
#define PERI_ECC_CTL_WORD_ADDR_Pos 0UL
|
||||
#define PERI_ECC_CTL_WORD_ADDR_Msk 0x7FFUL
|
||||
#define PERI_ECC_CTL_ECC_EN_Pos 16UL
|
||||
#define PERI_ECC_CTL_ECC_EN_Msk 0x10000UL
|
||||
#define PERI_ECC_CTL_ECC_INJ_EN_Pos 18UL
|
||||
#define PERI_ECC_CTL_ECC_INJ_EN_Msk 0x40000UL
|
||||
#define PERI_ECC_CTL_PARITY_Pos 24UL
|
||||
#define PERI_ECC_CTL_PARITY_Msk 0xFF000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_PERI_V3_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,864 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_prot.h
|
||||
*
|
||||
* \brief
|
||||
* PROT IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PROT_H_
|
||||
#define _CYIP_PROT_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_SMPU_SMPU_STRUCT_SECTION_SIZE 0x00000040UL
|
||||
#define PROT_SMPU_SECTION_SIZE 0x00004000UL
|
||||
#define PROT_MPU_MPU_STRUCT_SECTION_SIZE 0x00000020UL
|
||||
#define PROT_MPU_SECTION_SIZE 0x00000400UL
|
||||
#define PROT_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief SMPU region address 0 (slave structure) (PROT_SMPU_SMPU_STRUCT_ADDR0)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_SMPU_STRUCT_ADDR0_field {
|
||||
uint32_t u8SUBREGION_DISABLE:8;
|
||||
uint32_t u24ADDR24:24;
|
||||
} stc_PROT_SMPU_SMPU_STRUCT_ADDR0_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_SMPU_STRUCT_ADDR0 {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_SMPU_STRUCT_ADDR0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_SMPU_STRUCT_ADDR0_t;
|
||||
|
||||
/**
|
||||
* \brief SMPU region attributes 0 (slave structure) (PROT_SMPU_SMPU_STRUCT_ATT0)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_SMPU_STRUCT_ATT0_field {
|
||||
uint32_t u1UR:1;
|
||||
uint32_t u1UW:1;
|
||||
uint32_t u1UX:1;
|
||||
uint32_t u1PR:1;
|
||||
uint32_t u1PW:1;
|
||||
uint32_t u1PX:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
uint32_t u5REGION_SIZE:5;
|
||||
uint32_t :1;
|
||||
uint32_t u1PC_MATCH:1;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_PROT_SMPU_SMPU_STRUCT_ATT0_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_SMPU_STRUCT_ATT0 {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_SMPU_STRUCT_ATT0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_SMPU_STRUCT_ATT0_t;
|
||||
|
||||
/**
|
||||
* \brief SMPU region address 1 (master structure) (PROT_SMPU_SMPU_STRUCT_ADDR1)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_SMPU_STRUCT_ADDR1_field {
|
||||
uint32_t u8SUBREGION_DISABLE:8;
|
||||
uint32_t u24ADDR24:24;
|
||||
} stc_PROT_SMPU_SMPU_STRUCT_ADDR1_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_SMPU_STRUCT_ADDR1 {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_SMPU_STRUCT_ADDR1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_SMPU_STRUCT_ADDR1_t;
|
||||
|
||||
/**
|
||||
* \brief SMPU region attributes 1 (master structure) (PROT_SMPU_SMPU_STRUCT_ATT1)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_SMPU_STRUCT_ATT1_field {
|
||||
uint32_t u1UR:1;
|
||||
uint32_t u1UW:1;
|
||||
uint32_t u1UX:1;
|
||||
uint32_t u1PR:1;
|
||||
uint32_t u1PW:1;
|
||||
uint32_t u1PX:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
uint32_t u5REGION_SIZE:5;
|
||||
uint32_t :1;
|
||||
uint32_t u1PC_MATCH:1;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_PROT_SMPU_SMPU_STRUCT_ATT1_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_SMPU_STRUCT_ATT1 {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_SMPU_STRUCT_ATT1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_SMPU_STRUCT_ATT1_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Master 0 protection context control (PROT_SMPU_MS0_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS0_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS0_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS0_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS0_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS0_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 1 protection context control (PROT_SMPU_MS1_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS1_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS1_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS1_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS1_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS1_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 2 protection context control (PROT_SMPU_MS2_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS2_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS2_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS2_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS2_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS2_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 3 protection context control (PROT_SMPU_MS3_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS3_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS3_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS3_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS3_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS3_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 4 protection context control (PROT_SMPU_MS4_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS4_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS4_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS4_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS4_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS4_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 5 protection context control (PROT_SMPU_MS5_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS5_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS5_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS5_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS5_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS5_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 6 protection context control (PROT_SMPU_MS6_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS6_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS6_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS6_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS6_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS6_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 7 protection context control (PROT_SMPU_MS7_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS7_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS7_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS7_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS7_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS7_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 8 protection context control (PROT_SMPU_MS8_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS8_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS8_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS8_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS8_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS8_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 9 protection context control (PROT_SMPU_MS9_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS9_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS9_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS9_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS9_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS9_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 10 protection context control (PROT_SMPU_MS10_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS10_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS10_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS10_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS10_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS10_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 11 protection context control (PROT_SMPU_MS11_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS11_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS11_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS11_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS11_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS11_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 12 protection context control (PROT_SMPU_MS12_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS12_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS12_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS12_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS12_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS12_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 13 protection context control (PROT_SMPU_MS13_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS13_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS13_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS13_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS13_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS13_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 14 protection context control (PROT_SMPU_MS14_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS14_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS14_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS14_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS14_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS14_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master 15 protection context control (PROT_SMPU_MS15_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_MS15_CTL_field {
|
||||
uint32_t u1P:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :6;
|
||||
uint32_t u2PRIO:2;
|
||||
uint32_t :6;
|
||||
uint32_t u1PC_MASK_0:1;
|
||||
uint32_t u15PC_MASK_15_TO_1:15;
|
||||
} stc_PROT_SMPU_MS15_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_SMPU_MS15_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_SMPU_MS15_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_SMPU_MS15_CTL_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief MPU region address (PROT_MPU_MPU_STRUCT_ADDR)
|
||||
*/
|
||||
typedef struct stc_PROT_MPU_MPU_STRUCT_ADDR_field {
|
||||
uint32_t u8SUBREGION_DISABLE:8;
|
||||
uint32_t u24ADDR24:24;
|
||||
} stc_PROT_MPU_MPU_STRUCT_ADDR_field_t;
|
||||
|
||||
typedef union un_PROT_MPU_MPU_STRUCT_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_MPU_MPU_STRUCT_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_MPU_MPU_STRUCT_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief MPU region attrributes (PROT_MPU_MPU_STRUCT_ATT)
|
||||
*/
|
||||
typedef struct stc_PROT_MPU_MPU_STRUCT_ATT_field {
|
||||
uint32_t u1UR:1;
|
||||
uint32_t u1UW:1;
|
||||
uint32_t u1UX:1;
|
||||
uint32_t u1PR:1;
|
||||
uint32_t u1PW:1;
|
||||
uint32_t u1PX:1;
|
||||
uint32_t u1NS:1;
|
||||
uint32_t :17;
|
||||
uint32_t u5REGION_SIZE:5;
|
||||
uint32_t :2;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_PROT_MPU_MPU_STRUCT_ATT_field_t;
|
||||
|
||||
typedef union un_PROT_MPU_MPU_STRUCT_ATT {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_MPU_MPU_STRUCT_ATT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_MPU_MPU_STRUCT_ATT_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Master control (PROT_MPU_MS_CTL)
|
||||
*/
|
||||
typedef struct stc_PROT_MPU_MS_CTL_field {
|
||||
uint32_t u4PC:4;
|
||||
uint32_t :12;
|
||||
uint32_t u4PC_SAVED:4;
|
||||
uint32_t :12;
|
||||
} stc_PROT_MPU_MS_CTL_field_t;
|
||||
|
||||
typedef union un_PROT_MPU_MS_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_MPU_MS_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_MPU_MS_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Master control read mirror (PROT_MPU_MS_CTL_READ_MIR)
|
||||
*/
|
||||
typedef struct stc_PROT_MPU_MS_CTL_READ_MIR_field {
|
||||
uint32_t u4PC:4;
|
||||
uint32_t :12;
|
||||
uint32_t u4PC_SAVED:4;
|
||||
uint32_t :12;
|
||||
} stc_PROT_MPU_MS_CTL_READ_MIR_field_t;
|
||||
|
||||
typedef union un_PROT_MPU_MS_CTL_READ_MIR {
|
||||
uint32_t u32Register;
|
||||
stc_PROT_MPU_MS_CTL_READ_MIR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_PROT_MPU_MS_CTL_READ_MIR_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief SMPU structure (PROT_SMPU_SMPU_STRUCT)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU_SMPU_STRUCT {
|
||||
un_PROT_SMPU_SMPU_STRUCT_ADDR0_t unADDR0; /*!< 0x00000000 SMPU region address 0 (slave structure) */
|
||||
un_PROT_SMPU_SMPU_STRUCT_ATT0_t unATT0; /*!< 0x00000004 SMPU region attributes 0 (slave structure) */
|
||||
uint32_t au32Reserved[6];
|
||||
un_PROT_SMPU_SMPU_STRUCT_ADDR1_t unADDR1; /*!< 0x00000020 SMPU region address 1 (master structure) */
|
||||
un_PROT_SMPU_SMPU_STRUCT_ATT1_t unATT1; /*!< 0x00000024 SMPU region attributes 1 (master structure) */
|
||||
uint32_t au32Reserved1[6];
|
||||
} stc_PROT_SMPU_SMPU_STRUCT_t; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief SMPU (PROT_SMPU)
|
||||
*/
|
||||
typedef struct stc_PROT_SMPU {
|
||||
un_PROT_SMPU_MS0_CTL_t unMS0_CTL; /*!< 0x00000000 Master 0 protection context control */
|
||||
un_PROT_SMPU_MS1_CTL_t unMS1_CTL; /*!< 0x00000004 Master 1 protection context control */
|
||||
un_PROT_SMPU_MS2_CTL_t unMS2_CTL; /*!< 0x00000008 Master 2 protection context control */
|
||||
un_PROT_SMPU_MS3_CTL_t unMS3_CTL; /*!< 0x0000000C Master 3 protection context control */
|
||||
un_PROT_SMPU_MS4_CTL_t unMS4_CTL; /*!< 0x00000010 Master 4 protection context control */
|
||||
un_PROT_SMPU_MS5_CTL_t unMS5_CTL; /*!< 0x00000014 Master 5 protection context control */
|
||||
un_PROT_SMPU_MS6_CTL_t unMS6_CTL; /*!< 0x00000018 Master 6 protection context control */
|
||||
un_PROT_SMPU_MS7_CTL_t unMS7_CTL; /*!< 0x0000001C Master 7 protection context control */
|
||||
un_PROT_SMPU_MS8_CTL_t unMS8_CTL; /*!< 0x00000020 Master 8 protection context control */
|
||||
un_PROT_SMPU_MS9_CTL_t unMS9_CTL; /*!< 0x00000024 Master 9 protection context control */
|
||||
un_PROT_SMPU_MS10_CTL_t unMS10_CTL; /*!< 0x00000028 Master 10 protection context control */
|
||||
un_PROT_SMPU_MS11_CTL_t unMS11_CTL; /*!< 0x0000002C Master 11 protection context control */
|
||||
un_PROT_SMPU_MS12_CTL_t unMS12_CTL; /*!< 0x00000030 Master 12 protection context control */
|
||||
un_PROT_SMPU_MS13_CTL_t unMS13_CTL; /*!< 0x00000034 Master 13 protection context control */
|
||||
un_PROT_SMPU_MS14_CTL_t unMS14_CTL; /*!< 0x00000038 Master 14 protection context control */
|
||||
un_PROT_SMPU_MS15_CTL_t unMS15_CTL; /*!< 0x0000003C Master 15 protection context control */
|
||||
uint32_t au32Reserved[2032];
|
||||
stc_PROT_SMPU_SMPU_STRUCT_t SMPU_STRUCT[32]; /*!< 0x00002000 SMPU structure */
|
||||
uint32_t au32Reserved1[1536];
|
||||
} stc_PROT_SMPU_t; /*!< Size = 16384 (0x4000) */
|
||||
|
||||
/**
|
||||
* \brief MPU structure (PROT_MPU_MPU_STRUCT)
|
||||
*/
|
||||
typedef struct stc_PROT_MPU_MPU_STRUCT {
|
||||
un_PROT_MPU_MPU_STRUCT_ADDR_t unADDR; /*!< 0x00000000 MPU region address */
|
||||
un_PROT_MPU_MPU_STRUCT_ATT_t unATT; /*!< 0x00000004 MPU region attrributes */
|
||||
uint32_t au32Reserved[6];
|
||||
} stc_PROT_MPU_MPU_STRUCT_t; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief MPU (PROT_MPU)
|
||||
*/
|
||||
typedef struct stc_PROT_MPU {
|
||||
un_PROT_MPU_MS_CTL_t unMS_CTL; /*!< 0x00000000 Master control */
|
||||
un_PROT_MPU_MS_CTL_READ_MIR_t unMS_CTL_READ_MIR[127]; /*!< 0x00000004 Master control read mirror */
|
||||
stc_PROT_MPU_MPU_STRUCT_t MPU_STRUCT[16]; /*!< 0x00000200 MPU structure */
|
||||
} stc_PROT_MPU_t; /*!< Size = 1024 (0x400) */
|
||||
|
||||
/**
|
||||
* \brief Protection (PROT)
|
||||
*/
|
||||
typedef struct stc_PROT {
|
||||
stc_PROT_SMPU_t SMPU; /*!< 0x00000000 SMPU */
|
||||
stc_PROT_MPU_t CYMPU[16]; /*!< 0x00004000 MPU */
|
||||
} stc_PROT_t; /*!< Size = 32768 (0x8000) */
|
||||
|
||||
|
||||
/* PROT_SMPU_SMPU_STRUCT.ADDR0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PROT_SMPU_SMPU_STRUCT.ATT0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Msk 0x1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Pos 1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Msk 0x2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Pos 2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Msk 0x4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Pos 3UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Msk 0x8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Pos 4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Msk 0x10UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Pos 5UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Msk 0x20UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Pos 6UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Msk 0x40UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk 0x100UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Pos 24UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Pos 30UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Msk 0x40000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Pos 31UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Msk 0x80000000UL
|
||||
/* PROT_SMPU_SMPU_STRUCT.ADDR1 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PROT_SMPU_SMPU_STRUCT.ATT1 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Msk 0x1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Pos 1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Msk 0x2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Pos 2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk 0x4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Pos 3UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Msk 0x8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Pos 4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Msk 0x10UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Pos 5UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk 0x20UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Pos 6UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Msk 0x40UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk 0x100UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Pos 24UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Pos 30UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Msk 0x40000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Pos 31UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PROT_SMPU.MS0_CTL */
|
||||
#define PROT_SMPU_MS0_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS0_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS0_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS0_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS0_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS0_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS0_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS0_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS1_CTL */
|
||||
#define PROT_SMPU_MS1_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS1_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS1_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS1_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS1_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS1_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS1_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS1_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS2_CTL */
|
||||
#define PROT_SMPU_MS2_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS2_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS2_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS2_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS2_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS2_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS2_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS2_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS3_CTL */
|
||||
#define PROT_SMPU_MS3_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS3_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS3_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS3_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS3_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS3_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS3_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS3_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS4_CTL */
|
||||
#define PROT_SMPU_MS4_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS4_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS4_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS4_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS4_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS4_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS4_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS4_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS5_CTL */
|
||||
#define PROT_SMPU_MS5_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS5_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS5_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS5_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS5_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS5_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS5_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS5_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS6_CTL */
|
||||
#define PROT_SMPU_MS6_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS6_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS6_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS6_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS6_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS6_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS6_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS6_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS7_CTL */
|
||||
#define PROT_SMPU_MS7_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS7_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS7_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS7_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS7_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS7_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS7_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS7_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS8_CTL */
|
||||
#define PROT_SMPU_MS8_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS8_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS8_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS8_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS8_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS8_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS8_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS8_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS9_CTL */
|
||||
#define PROT_SMPU_MS9_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS9_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS9_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS9_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS9_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS9_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS9_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS9_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS10_CTL */
|
||||
#define PROT_SMPU_MS10_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS10_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS10_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS10_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS10_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS10_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS10_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS10_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS11_CTL */
|
||||
#define PROT_SMPU_MS11_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS11_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS11_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS11_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS11_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS11_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS11_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS11_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS12_CTL */
|
||||
#define PROT_SMPU_MS12_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS12_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS12_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS12_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS12_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS12_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS12_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS12_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS13_CTL */
|
||||
#define PROT_SMPU_MS13_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS13_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS13_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS13_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS13_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS13_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS13_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS13_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS14_CTL */
|
||||
#define PROT_SMPU_MS14_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS14_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS14_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS14_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS14_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS14_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS14_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS14_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS15_CTL */
|
||||
#define PROT_SMPU_MS15_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS15_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS15_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS15_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS15_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS15_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS15_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS15_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
|
||||
|
||||
/* PROT_MPU_MPU_STRUCT.ADDR */
|
||||
#define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Pos 8UL
|
||||
#define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PROT_MPU_MPU_STRUCT.ATT */
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UR_Pos 0UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UR_Msk 0x1UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UW_Pos 1UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UW_Msk 0x2UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UX_Pos 2UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UX_Msk 0x4UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PR_Pos 3UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PR_Msk 0x8UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PW_Pos 4UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PW_Msk 0x10UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PX_Pos 5UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PX_Msk 0x20UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_NS_Pos 6UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_NS_Msk 0x40UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Pos 24UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Pos 31UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PROT_MPU.MS_CTL */
|
||||
#define PROT_MPU_MS_CTL_PC_Pos 0UL
|
||||
#define PROT_MPU_MS_CTL_PC_Msk 0xFUL
|
||||
#define PROT_MPU_MS_CTL_PC_SAVED_Pos 16UL
|
||||
#define PROT_MPU_MS_CTL_PC_SAVED_Msk 0xF0000UL
|
||||
/* PROT_MPU.MS_CTL_READ_MIR */
|
||||
#define PROT_MPU_MS_CTL_READ_MIR_PC_Pos 0UL
|
||||
#define PROT_MPU_MS_CTL_READ_MIR_PC_Msk 0xFUL
|
||||
#define PROT_MPU_MS_CTL_READ_MIR_PC_SAVED_Pos 16UL
|
||||
#define PROT_MPU_MS_CTL_READ_MIR_PC_SAVED_Msk 0xF0000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_PROT_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,774 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_sflash_v2.h
|
||||
*
|
||||
* \brief
|
||||
* SFLASH IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_SFLASH_V2_H_
|
||||
#define _CYIP_SFLASH_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_SECTION_SIZE 0x00008000UL
|
||||
|
||||
/**
|
||||
* \brief Indicates Silicon Revision ID of the device (SFLASH_SI_REVISION_ID)
|
||||
*/
|
||||
typedef struct stc_SFLASH_SI_REVISION_ID_field {
|
||||
uint8_t u8SI_REVISION_ID:8;
|
||||
} stc_SFLASH_SI_REVISION_ID_field_t;
|
||||
|
||||
typedef union un_SFLASH_SI_REVISION_ID {
|
||||
uint8_t u8Register;
|
||||
stc_SFLASH_SI_REVISION_ID_field_t stcField;
|
||||
} un_SFLASH_SI_REVISION_ID_t;
|
||||
|
||||
/**
|
||||
* \brief Indicates Silicon ID of the device (SFLASH_SILICON_ID)
|
||||
*/
|
||||
typedef struct stc_SFLASH_SILICON_ID_field {
|
||||
uint16_t u16ID:16;
|
||||
} stc_SFLASH_SILICON_ID_field_t;
|
||||
|
||||
typedef union un_SFLASH_SILICON_ID {
|
||||
uint16_t u16Register;
|
||||
stc_SFLASH_SILICON_ID_field_t stcField;
|
||||
uint8_t au8Byte[2];
|
||||
} un_SFLASH_SILICON_ID_t;
|
||||
|
||||
/**
|
||||
* \brief SRSS_PWR_OFFSET (SFLASH_SRSS_PWR_OFFSET)
|
||||
*/
|
||||
typedef struct stc_SFLASH_SRSS_PWR_OFFSET_field {
|
||||
uint32_t u5PMIC_VADJ_OFFSET:5;
|
||||
uint32_t :3;
|
||||
uint32_t u5REGHC_TRANS_VADJ_OFFSET:5;
|
||||
uint32_t :19;
|
||||
} stc_SFLASH_SRSS_PWR_OFFSET_field_t;
|
||||
|
||||
typedef union un_SFLASH_SRSS_PWR_OFFSET {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_SRSS_PWR_OFFSET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_SRSS_PWR_OFFSET_t;
|
||||
|
||||
/**
|
||||
* \brief USER_FREE_ROW0 (SFLASH_USER_FREE_ROW0)
|
||||
*/
|
||||
typedef struct stc_SFLASH_USER_FREE_ROW0_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_USER_FREE_ROW0_field_t;
|
||||
|
||||
typedef union un_SFLASH_USER_FREE_ROW0 {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_USER_FREE_ROW0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_USER_FREE_ROW0_t;
|
||||
|
||||
/**
|
||||
* \brief USER_FREE_ROW1 (SFLASH_USER_FREE_ROW1)
|
||||
*/
|
||||
typedef struct stc_SFLASH_USER_FREE_ROW1_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_USER_FREE_ROW1_field_t;
|
||||
|
||||
typedef union un_SFLASH_USER_FREE_ROW1 {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_USER_FREE_ROW1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_USER_FREE_ROW1_t;
|
||||
|
||||
/**
|
||||
* \brief USER_FREE_ROW2 (SFLASH_USER_FREE_ROW2)
|
||||
*/
|
||||
typedef struct stc_SFLASH_USER_FREE_ROW2_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_USER_FREE_ROW2_field_t;
|
||||
|
||||
typedef union un_SFLASH_USER_FREE_ROW2 {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_USER_FREE_ROW2_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_USER_FREE_ROW2_t;
|
||||
|
||||
/**
|
||||
* \brief USER_FREE_ROW3 (SFLASH_USER_FREE_ROW3)
|
||||
*/
|
||||
typedef struct stc_SFLASH_USER_FREE_ROW3_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_USER_FREE_ROW3_field_t;
|
||||
|
||||
typedef union un_SFLASH_USER_FREE_ROW3 {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_USER_FREE_ROW3_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_USER_FREE_ROW3_t;
|
||||
|
||||
/**
|
||||
* \brief Markers for storing SFLASH programming states (SFLASH_SFLASH_UPDATE_MARKER)
|
||||
*/
|
||||
typedef struct stc_SFLASH_SFLASH_UPDATE_MARKER_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_SFLASH_UPDATE_MARKER_field_t;
|
||||
|
||||
typedef union un_SFLASH_SFLASH_UPDATE_MARKER {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_SFLASH_UPDATE_MARKER_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_SFLASH_UPDATE_MARKER_t;
|
||||
|
||||
/**
|
||||
* \brief Flash Boot - Object Size (SFLASH_FLASH_BOOT_OBJECT_SIZE)
|
||||
*/
|
||||
typedef struct stc_SFLASH_FLASH_BOOT_OBJECT_SIZE_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_FLASH_BOOT_OBJECT_SIZE_field_t;
|
||||
|
||||
typedef union un_SFLASH_FLASH_BOOT_OBJECT_SIZE {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_FLASH_BOOT_OBJECT_SIZE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_FLASH_BOOT_OBJECT_SIZE_t;
|
||||
|
||||
/**
|
||||
* \brief Flash Boot - Application ID/Version (SFLASH_FLASH_BOOT_APP_ID)
|
||||
*/
|
||||
typedef struct stc_SFLASH_FLASH_BOOT_APP_ID_field {
|
||||
uint32_t u16APP_ID:16;
|
||||
uint32_t u8MINOR_VERSION:8;
|
||||
uint32_t u4MAJOR_VERSION:4;
|
||||
uint32_t :4;
|
||||
} stc_SFLASH_FLASH_BOOT_APP_ID_field_t;
|
||||
|
||||
typedef union un_SFLASH_FLASH_BOOT_APP_ID {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_FLASH_BOOT_APP_ID_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_FLASH_BOOT_APP_ID_t;
|
||||
|
||||
/**
|
||||
* \brief Flash Boot - Core Vector Table (SFLASH_FLASH_BOOT_VECTOR_TABLE)
|
||||
*/
|
||||
typedef struct stc_SFLASH_FLASH_BOOT_VECTOR_TABLE_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_FLASH_BOOT_VECTOR_TABLE_field_t;
|
||||
|
||||
typedef union un_SFLASH_FLASH_BOOT_VECTOR_TABLE {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_FLASH_BOOT_VECTOR_TABLE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_FLASH_BOOT_VECTOR_TABLE_t;
|
||||
|
||||
/**
|
||||
* \brief Public key for signature verification (max RSA key size 4096) (SFLASH_PUBLIC_KEY)
|
||||
*/
|
||||
typedef struct stc_SFLASH_PUBLIC_KEY_field {
|
||||
uint8_t u8DATA:8;
|
||||
} stc_SFLASH_PUBLIC_KEY_field_t;
|
||||
|
||||
typedef union un_SFLASH_PUBLIC_KEY {
|
||||
uint8_t u8Register;
|
||||
stc_SFLASH_PUBLIC_KEY_field_t stcField;
|
||||
} un_SFLASH_PUBLIC_KEY_t;
|
||||
|
||||
/**
|
||||
* \brief Application protection settings (4*128=512 bytes) (SFLASH_APP_PROT_SETTINGS)
|
||||
*/
|
||||
typedef struct stc_SFLASH_APP_PROT_SETTINGS_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_APP_PROT_SETTINGS_field_t;
|
||||
|
||||
typedef union un_SFLASH_APP_PROT_SETTINGS {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_APP_PROT_SETTINGS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_APP_PROT_SETTINGS_t;
|
||||
|
||||
/**
|
||||
* \brief Object size in bytes for CRC calculation starting from offset 0x00 (SFLASH_TOC1_OBJECT_SIZE)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC1_OBJECT_SIZE_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC1_OBJECT_SIZE_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC1_OBJECT_SIZE {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC1_OBJECT_SIZE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC1_OBJECT_SIZE_t;
|
||||
|
||||
/**
|
||||
* \brief Magic number(0x01211219) (SFLASH_TOC1_MAGIC_NUMBER)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC1_MAGIC_NUMBER_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC1_MAGIC_NUMBER_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC1_MAGIC_NUMBER {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC1_MAGIC_NUMBER_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC1_MAGIC_NUMBER_t;
|
||||
|
||||
/**
|
||||
* \brief Number of objects to be verified for FACTORY_HASH (SFLASH_TOC1_FHASH_OBJECTS)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC1_FHASH_OBJECTS_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC1_FHASH_OBJECTS_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC1_FHASH_OBJECTS {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC1_FHASH_OBJECTS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC1_FHASH_OBJECTS_t;
|
||||
|
||||
/**
|
||||
* \brief Unused (Address is Hardcoded in ROM) (SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_t;
|
||||
|
||||
/**
|
||||
* \brief Address of Unique ID stored in SFLASH (SFLASH_TOC1_UNIQUE_ID_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC1_UNIQUE_ID_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC1_UNIQUE_ID_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC1_UNIQUE_ID_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC1_UNIQUE_ID_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC1_UNIQUE_ID_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Addresss of FLASH Boot(FB) object that include FLASH patch also (SFLASH_TOC1_FB_OBJECT_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC1_FB_OBJECT_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC1_FB_OBJECT_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC1_FB_OBJECT_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC1_FB_OBJECT_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC1_FB_OBJECT_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Unused (Address is Hardcoded in ROM) (SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_t;
|
||||
|
||||
/**
|
||||
* \brief Unused (Address is Hardcoded in ROM) (SFLASH_TOC1_OBJECT_ADDR_UNUSED)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC1_OBJECT_ADDR_UNUSED_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC1_OBJECT_ADDR_UNUSED_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC1_OBJECT_ADDR_UNUSED {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC1_OBJECT_ADDR_UNUSED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC1_OBJECT_ADDR_UNUSED_t;
|
||||
|
||||
/**
|
||||
* \brief Address of boot protection object (SFLASH_TOC1_BOOT_PROTECTION_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC1_BOOT_PROTECTION_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC1_BOOT_PROTECTION_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC1_BOOT_PROTECTION_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC1_BOOT_PROTECTION_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC1_BOOT_PROTECTION_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Address of 8051 code OTP flash (SFLASH_TOC1_8051_CODE_OTP_FLASH_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC1_8051_CODE_OTP_FLASH_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC1_8051_CODE_OTP_FLASH_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC1_8051_CODE_OTP_FLASH_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC1_8051_CODE_OTP_FLASH_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC1_8051_CODE_OTP_FLASH_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Object size in bytes for CRC calculation starting from offset 0x00 (SFLASH_TOC2_OBJECT_SIZE)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_OBJECT_SIZE_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_OBJECT_SIZE_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_OBJECT_SIZE {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_OBJECT_SIZE_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_OBJECT_SIZE_t;
|
||||
|
||||
/**
|
||||
* \brief Magic number(0x01211220) (SFLASH_TOC2_MAGIC_NUMBER)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_MAGIC_NUMBER_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_MAGIC_NUMBER_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_MAGIC_NUMBER {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_MAGIC_NUMBER_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_MAGIC_NUMBER_t;
|
||||
|
||||
/**
|
||||
* \brief Null terminated table of pointers representing the SMIF configuration structure (SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Address of First User Application Object (SFLASH_TOC2_FIRST_USER_APP_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_FIRST_USER_APP_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_FIRST_USER_APP_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_FIRST_USER_APP_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_FIRST_USER_APP_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_FIRST_USER_APP_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Format of First User Application Object. 0 - Basic, 1 - Cypress standard & 2 - Simplified (SFLASH_TOC2_FIRST_USER_APP_FORMAT)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_FIRST_USER_APP_FORMAT_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_FIRST_USER_APP_FORMAT_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_FIRST_USER_APP_FORMAT {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_FIRST_USER_APP_FORMAT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_FIRST_USER_APP_FORMAT_t;
|
||||
|
||||
/**
|
||||
* \brief Address of Second User Application Object (SFLASH_TOC2_SECOND_USER_APP_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_SECOND_USER_APP_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_SECOND_USER_APP_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_SECOND_USER_APP_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_SECOND_USER_APP_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_SECOND_USER_APP_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Format of Second User Application Object. 0 - Basic, 1 - Cypress standard & 2 - Simplified (SFLASH_TOC2_SECOND_USER_APP_FORMAT)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_SECOND_USER_APP_FORMAT_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_SECOND_USER_APP_FORMAT_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_SECOND_USER_APP_FORMAT {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_SECOND_USER_APP_FORMAT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_SECOND_USER_APP_FORMAT_t;
|
||||
|
||||
/**
|
||||
* \brief Address of First CM4 or CM7 core1 User Application Object (SFLASH_TOC2_FIRST_CMX_1_USER_APP_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_FIRST_CMX_1_USER_APP_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_FIRST_CMX_1_USER_APP_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_FIRST_CMX_1_USER_APP_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_FIRST_CMX_1_USER_APP_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_FIRST_CMX_1_USER_APP_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Address of Second CM4 or CM7 core1 User Application Object (SFLASH_TOC2_SECOND_CMX_1_USER_APP_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_SECOND_CMX_1_USER_APP_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_SECOND_CMX_1_USER_APP_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_SECOND_CMX_1_USER_APP_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_SECOND_CMX_1_USER_APP_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_SECOND_CMX_1_USER_APP_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Address of First CM4 or CM7 core2 User Application Object (SFLASH_TOC2_FIRST_CMX_2_USER_APP_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_FIRST_CMX_2_USER_APP_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_FIRST_CMX_2_USER_APP_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_FIRST_CMX_2_USER_APP_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_FIRST_CMX_2_USER_APP_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_FIRST_CMX_2_USER_APP_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Address of Second CM4 or CM7 core2 User Application Object (SFLASH_TOC2_SECOND_CMX_2_USER_APP_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_SECOND_CMX_2_USER_APP_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_SECOND_CMX_2_USER_APP_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_SECOND_CMX_2_USER_APP_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_SECOND_CMX_2_USER_APP_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_SECOND_CMX_2_USER_APP_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Number of additional objects to be verified for SECURE_HASH (SFLASH_TOC2_SHASH_OBJECTS)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_SHASH_OBJECTS_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_SHASH_OBJECTS_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_SHASH_OBJECTS {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_SHASH_OBJECTS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_SHASH_OBJECTS_t;
|
||||
|
||||
/**
|
||||
* \brief Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA (SFLASH_TOC2_SIGNATURE_VERIF_KEY)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_SIGNATURE_VERIF_KEY_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_SIGNATURE_VERIF_KEY_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_SIGNATURE_VERIF_KEY {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_SIGNATURE_VERIF_KEY_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_SIGNATURE_VERIF_KEY_t;
|
||||
|
||||
/**
|
||||
* \brief Address of Application Protection (SFLASH_TOC2_APP_PROTECTION_ADDR)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_APP_PROTECTION_ADDR_field {
|
||||
uint32_t u32DATA32:32;
|
||||
} stc_SFLASH_TOC2_APP_PROTECTION_ADDR_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_APP_PROTECTION_ADDR {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_APP_PROTECTION_ADDR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_APP_PROTECTION_ADDR_t;
|
||||
|
||||
/**
|
||||
* \brief Controls default configuration (SFLASH_TOC2_FLAGS)
|
||||
*/
|
||||
typedef struct stc_SFLASH_TOC2_FLAGS_field {
|
||||
uint32_t u2CLOCK_CONFIG:2;
|
||||
uint32_t u3LISTEN_WINDOW:3;
|
||||
uint32_t u2SWJ_PINS_CTL:2;
|
||||
uint32_t u2APP_AUTH_DISABLE:2;
|
||||
uint32_t u2FB_BOOTLOADER_DISABLE:2;
|
||||
uint32_t :21;
|
||||
} stc_SFLASH_TOC2_FLAGS_field_t;
|
||||
|
||||
typedef union un_SFLASH_TOC2_FLAGS {
|
||||
uint32_t u32Register;
|
||||
stc_SFLASH_TOC2_FLAGS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SFLASH_TOC2_FLAGS_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief FLASH Supervisory Region (SFLASH)
|
||||
*/
|
||||
typedef struct stc_SFLASH {
|
||||
uint8_t u8Reserved;
|
||||
un_SFLASH_SI_REVISION_ID_t unSI_REVISION_ID; /*!< 0x00000001 Indicates Silicon Revision ID of the device */
|
||||
un_SFLASH_SILICON_ID_t unSILICON_ID; /*!< 0x00000002 Indicates Silicon ID of the device */
|
||||
uint32_t au32Reserved1[459];
|
||||
un_SFLASH_SRSS_PWR_OFFSET_t unSRSS_PWR_OFFSET; /*!< 0x00000730 SRSS_PWR_OFFSET */
|
||||
uint32_t au32Reserved2[51];
|
||||
un_SFLASH_USER_FREE_ROW0_t unUSER_FREE_ROW0[128]; /*!< 0x00000800 USER_FREE_ROW0 */
|
||||
un_SFLASH_USER_FREE_ROW1_t unUSER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */
|
||||
un_SFLASH_USER_FREE_ROW2_t unUSER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */
|
||||
un_SFLASH_USER_FREE_ROW3_t unUSER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */
|
||||
uint32_t au32Reserved3[512];
|
||||
un_SFLASH_SFLASH_UPDATE_MARKER_t unSFLASH_UPDATE_MARKER[2]; /*!< 0x00001800 Markers for storing SFLASH programming states */
|
||||
uint32_t au32Reserved4[510];
|
||||
un_SFLASH_FLASH_BOOT_OBJECT_SIZE_t unFLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */
|
||||
un_SFLASH_FLASH_BOOT_APP_ID_t unFLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */
|
||||
uint32_t au32Reserved5[4];
|
||||
un_SFLASH_FLASH_BOOT_VECTOR_TABLE_t unFLASH_BOOT_VECTOR_TABLE[48]; /*!< 0x00002018 Flash Boot - Core Vector Table */
|
||||
uint32_t au32Reserved6[4298];
|
||||
un_SFLASH_PUBLIC_KEY_t unPUBLIC_KEY[3072]; /*!< 0x00006400 Public key for signature verification (max RSA key size
|
||||
4096) */
|
||||
uint32_t au32Reserved7[384];
|
||||
un_SFLASH_APP_PROT_SETTINGS_t unAPP_PROT_SETTINGS[128]; /*!< 0x00007600 Application protection settings (4*128=512 bytes) */
|
||||
un_SFLASH_TOC1_OBJECT_SIZE_t unTOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from
|
||||
offset 0x00 */
|
||||
un_SFLASH_TOC1_MAGIC_NUMBER_t unTOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */
|
||||
uint32_t au32Reserved8[2];
|
||||
un_SFLASH_TOC1_FHASH_OBJECTS_t unTOC1_FHASH_OBJECTS; /*!< 0x00007810 Number of objects to be verified for FACTORY_HASH */
|
||||
un_SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_t unTOC1_GENERAL_TRIM_ADDR_UNUSED; /*!< 0x00007814 Unused (Address is Hardcoded in ROM) */
|
||||
un_SFLASH_TOC1_UNIQUE_ID_ADDR_t unTOC1_UNIQUE_ID_ADDR; /*!< 0x00007818 Address of Unique ID stored in SFLASH */
|
||||
un_SFLASH_TOC1_FB_OBJECT_ADDR_t unTOC1_FB_OBJECT_ADDR; /*!< 0x0000781C Addresss of FLASH Boot(FB) object that include FLASH
|
||||
patch also */
|
||||
un_SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_t unTOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007820 Unused (Address is Hardcoded in ROM) */
|
||||
un_SFLASH_TOC1_OBJECT_ADDR_UNUSED_t unTOC1_OBJECT_ADDR_UNUSED; /*!< 0x00007824 Unused (Address is Hardcoded in ROM) */
|
||||
un_SFLASH_TOC1_BOOT_PROTECTION_ADDR_t unTOC1_BOOT_PROTECTION_ADDR; /*!< 0x00007828 Address of boot protection object */
|
||||
un_SFLASH_TOC1_8051_CODE_OTP_FLASH_ADDR_t unTOC1_8051_CODE_OTP_FLASH_ADDR; /*!< 0x0000782C Address of 8051 code OTP flash */
|
||||
uint32_t au32Reserved9[244];
|
||||
un_SFLASH_TOC2_OBJECT_SIZE_t unTOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from
|
||||
offset 0x00 */
|
||||
un_SFLASH_TOC2_MAGIC_NUMBER_t unTOC2_MAGIC_NUMBER; /*!< 0x00007C04 Magic number(0x01211220) */
|
||||
un_SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_t unTOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007C08 Null terminated table of pointers representing the SMIF
|
||||
configuration structure */
|
||||
un_SFLASH_TOC2_FIRST_USER_APP_ADDR_t unTOC2_FIRST_USER_APP_ADDR; /*!< 0x00007C0C Address of First User Application Object */
|
||||
un_SFLASH_TOC2_FIRST_USER_APP_FORMAT_t unTOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007C10 Format of First User Application Object. 0 - Basic, 1 -
|
||||
Cypress standard & 2 - Simplified */
|
||||
un_SFLASH_TOC2_SECOND_USER_APP_ADDR_t unTOC2_SECOND_USER_APP_ADDR; /*!< 0x00007C14 Address of Second User Application Object */
|
||||
un_SFLASH_TOC2_SECOND_USER_APP_FORMAT_t unTOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007C18 Format of Second User Application Object. 0 - Basic, 1 -
|
||||
Cypress standard & 2 - Simplified */
|
||||
un_SFLASH_TOC2_FIRST_CMX_1_USER_APP_ADDR_t unTOC2_FIRST_CMX_1_USER_APP_ADDR; /*!< 0x00007C1C Address of First CM4 or CM7 core1 User Application
|
||||
Object */
|
||||
un_SFLASH_TOC2_SECOND_CMX_1_USER_APP_ADDR_t unTOC2_SECOND_CMX_1_USER_APP_ADDR; /*!< 0x00007C20 Address of Second CM4 or CM7 core1 User Application
|
||||
Object */
|
||||
un_SFLASH_TOC2_FIRST_CMX_2_USER_APP_ADDR_t unTOC2_FIRST_CMX_2_USER_APP_ADDR; /*!< 0x00007C24 Address of First CM4 or CM7 core2 User Application
|
||||
Object */
|
||||
un_SFLASH_TOC2_SECOND_CMX_2_USER_APP_ADDR_t unTOC2_SECOND_CMX_2_USER_APP_ADDR; /*!< 0x00007C28 Address of Second CM4 or CM7 core2 User Application
|
||||
Object */
|
||||
uint32_t au32Reserved10[53];
|
||||
un_SFLASH_TOC2_SHASH_OBJECTS_t unTOC2_SHASH_OBJECTS; /*!< 0x00007D00 Number of additional objects to be verified for
|
||||
SECURE_HASH */
|
||||
un_SFLASH_TOC2_SIGNATURE_VERIF_KEY_t unTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007D04 Address of signature verification key (0 if none).The
|
||||
object is signature specific key. It is the
|
||||
public key in case of RSA */
|
||||
un_SFLASH_TOC2_APP_PROTECTION_ADDR_t unTOC2_APP_PROTECTION_ADDR; /*!< 0x00007D08 Address of Application Protection */
|
||||
uint32_t au32Reserved11[59];
|
||||
un_SFLASH_TOC2_FLAGS_t unTOC2_FLAGS; /*!< 0x00007DF8 Controls default configuration */
|
||||
} stc_SFLASH_t; /*!< Size = 32252 (0x7DFC) */
|
||||
|
||||
|
||||
/* SFLASH.SI_REVISION_ID */
|
||||
#define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Pos 0UL
|
||||
#define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Msk 0xFFUL
|
||||
/* SFLASH.SILICON_ID */
|
||||
#define SFLASH_SILICON_ID_ID_Pos 0UL
|
||||
#define SFLASH_SILICON_ID_ID_Msk 0xFFFFUL
|
||||
/* SFLASH.SRSS_PWR_OFFSET */
|
||||
#define SFLASH_SRSS_PWR_OFFSET_PMIC_VADJ_OFFSET_Pos 0UL
|
||||
#define SFLASH_SRSS_PWR_OFFSET_PMIC_VADJ_OFFSET_Msk 0x1FUL
|
||||
#define SFLASH_SRSS_PWR_OFFSET_REGHC_TRANS_VADJ_OFFSET_Pos 8UL
|
||||
#define SFLASH_SRSS_PWR_OFFSET_REGHC_TRANS_VADJ_OFFSET_Msk 0x1F00UL
|
||||
/* SFLASH.USER_FREE_ROW0 */
|
||||
#define SFLASH_USER_FREE_ROW0_DATA32_Pos 0UL
|
||||
#define SFLASH_USER_FREE_ROW0_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.USER_FREE_ROW1 */
|
||||
#define SFLASH_USER_FREE_ROW1_DATA32_Pos 0UL
|
||||
#define SFLASH_USER_FREE_ROW1_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.USER_FREE_ROW2 */
|
||||
#define SFLASH_USER_FREE_ROW2_DATA32_Pos 0UL
|
||||
#define SFLASH_USER_FREE_ROW2_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.USER_FREE_ROW3 */
|
||||
#define SFLASH_USER_FREE_ROW3_DATA32_Pos 0UL
|
||||
#define SFLASH_USER_FREE_ROW3_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.SFLASH_UPDATE_MARKER */
|
||||
#define SFLASH_SFLASH_UPDATE_MARKER_DATA32_Pos 0UL
|
||||
#define SFLASH_SFLASH_UPDATE_MARKER_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.FLASH_BOOT_OBJECT_SIZE */
|
||||
#define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Pos 0UL
|
||||
#define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.FLASH_BOOT_APP_ID */
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Pos 0UL
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Msk 0xFFFFUL
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Pos 16UL
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Msk 0xFF0000UL
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Pos 24UL
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Msk 0xF000000UL
|
||||
/* SFLASH.FLASH_BOOT_VECTOR_TABLE */
|
||||
#define SFLASH_FLASH_BOOT_VECTOR_TABLE_DATA32_Pos 0UL
|
||||
#define SFLASH_FLASH_BOOT_VECTOR_TABLE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.PUBLIC_KEY */
|
||||
#define SFLASH_PUBLIC_KEY_DATA_Pos 0UL
|
||||
#define SFLASH_PUBLIC_KEY_DATA_Msk 0xFFUL
|
||||
/* SFLASH.APP_PROT_SETTINGS */
|
||||
#define SFLASH_APP_PROT_SETTINGS_DATA32_Pos 0UL
|
||||
#define SFLASH_APP_PROT_SETTINGS_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_OBJECT_SIZE */
|
||||
#define SFLASH_TOC1_OBJECT_SIZE_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_MAGIC_NUMBER */
|
||||
#define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_FHASH_OBJECTS */
|
||||
#define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_GENERAL_TRIM_ADDR_UNUSED */
|
||||
#define SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_UNIQUE_ID_ADDR */
|
||||
#define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_FB_OBJECT_ADDR */
|
||||
#define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_SYSCALL_TABLE_ADDR_UNUSED */
|
||||
#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_OBJECT_ADDR_UNUSED */
|
||||
#define SFLASH_TOC1_OBJECT_ADDR_UNUSED_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_OBJECT_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_BOOT_PROTECTION_ADDR */
|
||||
#define SFLASH_TOC1_BOOT_PROTECTION_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_BOOT_PROTECTION_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_8051_CODE_OTP_FLASH_ADDR */
|
||||
#define SFLASH_TOC1_8051_CODE_OTP_FLASH_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_8051_CODE_OTP_FLASH_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_OBJECT_SIZE */
|
||||
#define SFLASH_TOC2_OBJECT_SIZE_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_MAGIC_NUMBER */
|
||||
#define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SMIF_CFG_STRUCT_ADDR */
|
||||
#define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_FIRST_USER_APP_ADDR */
|
||||
#define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_FIRST_USER_APP_FORMAT */
|
||||
#define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SECOND_USER_APP_ADDR */
|
||||
#define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SECOND_USER_APP_FORMAT */
|
||||
#define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_FIRST_CMX_1_USER_APP_ADDR */
|
||||
#define SFLASH_TOC2_FIRST_CMX_1_USER_APP_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_FIRST_CMX_1_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SECOND_CMX_1_USER_APP_ADDR */
|
||||
#define SFLASH_TOC2_SECOND_CMX_1_USER_APP_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SECOND_CMX_1_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_FIRST_CMX_2_USER_APP_ADDR */
|
||||
#define SFLASH_TOC2_FIRST_CMX_2_USER_APP_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_FIRST_CMX_2_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SECOND_CMX_2_USER_APP_ADDR */
|
||||
#define SFLASH_TOC2_SECOND_CMX_2_USER_APP_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SECOND_CMX_2_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SHASH_OBJECTS */
|
||||
#define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SIGNATURE_VERIF_KEY */
|
||||
#define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_APP_PROTECTION_ADDR */
|
||||
#define SFLASH_TOC2_APP_PROTECTION_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_APP_PROTECTION_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_FLAGS */
|
||||
#define SFLASH_TOC2_FLAGS_CLOCK_CONFIG_Pos 0UL
|
||||
#define SFLASH_TOC2_FLAGS_CLOCK_CONFIG_Msk 0x3UL
|
||||
#define SFLASH_TOC2_FLAGS_LISTEN_WINDOW_Pos 2UL
|
||||
#define SFLASH_TOC2_FLAGS_LISTEN_WINDOW_Msk 0x1CUL
|
||||
#define SFLASH_TOC2_FLAGS_SWJ_PINS_CTL_Pos 5UL
|
||||
#define SFLASH_TOC2_FLAGS_SWJ_PINS_CTL_Msk 0x60UL
|
||||
#define SFLASH_TOC2_FLAGS_APP_AUTH_DISABLE_Pos 7UL
|
||||
#define SFLASH_TOC2_FLAGS_APP_AUTH_DISABLE_Msk 0x180UL
|
||||
#define SFLASH_TOC2_FLAGS_FB_BOOTLOADER_DISABLE_Pos 9UL
|
||||
#define SFLASH_TOC2_FLAGS_FB_BOOTLOADER_DISABLE_Msk 0x600UL
|
||||
|
||||
|
||||
#endif /* _CYIP_SFLASH_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,237 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_smartio_v3.h
|
||||
*
|
||||
* \brief
|
||||
* SMARTIO IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_SMARTIO_V3_H_
|
||||
#define _CYIP_SMARTIO_V3_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_PRT_SECTION_SIZE 0x00000100UL
|
||||
#define SMARTIO_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Control register (SMARTIO_PRT_CTL)
|
||||
*/
|
||||
typedef struct stc_SMARTIO_PRT_CTL_field {
|
||||
uint32_t u8BYPASS:8;
|
||||
uint32_t u5CLOCK_SRC:5;
|
||||
uint32_t :11;
|
||||
uint32_t u1HLD_OVR:1;
|
||||
uint32_t u1PIPELINE_EN:1;
|
||||
uint32_t :5;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_SMARTIO_PRT_CTL_field_t;
|
||||
|
||||
typedef union un_SMARTIO_PRT_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_SMARTIO_PRT_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SMARTIO_PRT_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Synchronization control register (SMARTIO_PRT_SYNC_CTL)
|
||||
*/
|
||||
typedef struct stc_SMARTIO_PRT_SYNC_CTL_field {
|
||||
uint32_t u8IO_SYNC_EN:8;
|
||||
uint32_t u8CHIP_SYNC_EN:8;
|
||||
uint32_t :16;
|
||||
} stc_SMARTIO_PRT_SYNC_CTL_field_t;
|
||||
|
||||
typedef union un_SMARTIO_PRT_SYNC_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_SMARTIO_PRT_SYNC_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SMARTIO_PRT_SYNC_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief LUT component input selection (SMARTIO_PRT_LUT_SEL)
|
||||
*/
|
||||
typedef struct stc_SMARTIO_PRT_LUT_SEL_field {
|
||||
uint32_t u4LUT_TR0_SEL:4;
|
||||
uint32_t :4;
|
||||
uint32_t u4LUT_TR1_SEL:4;
|
||||
uint32_t :4;
|
||||
uint32_t u4LUT_TR2_SEL:4;
|
||||
uint32_t :12;
|
||||
} stc_SMARTIO_PRT_LUT_SEL_field_t;
|
||||
|
||||
typedef union un_SMARTIO_PRT_LUT_SEL {
|
||||
uint32_t u32Register;
|
||||
stc_SMARTIO_PRT_LUT_SEL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SMARTIO_PRT_LUT_SEL_t;
|
||||
|
||||
/**
|
||||
* \brief LUT component control register (SMARTIO_PRT_LUT_CTL)
|
||||
*/
|
||||
typedef struct stc_SMARTIO_PRT_LUT_CTL_field {
|
||||
uint32_t u8LUT:8;
|
||||
uint32_t u2LUT_OPC:2;
|
||||
uint32_t :22;
|
||||
} stc_SMARTIO_PRT_LUT_CTL_field_t;
|
||||
|
||||
typedef union un_SMARTIO_PRT_LUT_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_SMARTIO_PRT_LUT_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SMARTIO_PRT_LUT_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Data unit component input selection (SMARTIO_PRT_DU_SEL)
|
||||
*/
|
||||
typedef struct stc_SMARTIO_PRT_DU_SEL_field {
|
||||
uint32_t u4DU_TR0_SEL:4;
|
||||
uint32_t :4;
|
||||
uint32_t u4DU_TR1_SEL:4;
|
||||
uint32_t :4;
|
||||
uint32_t u4DU_TR2_SEL:4;
|
||||
uint32_t :4;
|
||||
uint32_t u2DU_DATA0_SEL:2;
|
||||
uint32_t :2;
|
||||
uint32_t u2DU_DATA1_SEL:2;
|
||||
uint32_t :2;
|
||||
} stc_SMARTIO_PRT_DU_SEL_field_t;
|
||||
|
||||
typedef union un_SMARTIO_PRT_DU_SEL {
|
||||
uint32_t u32Register;
|
||||
stc_SMARTIO_PRT_DU_SEL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SMARTIO_PRT_DU_SEL_t;
|
||||
|
||||
/**
|
||||
* \brief Data unit component control register (SMARTIO_PRT_DU_CTL)
|
||||
*/
|
||||
typedef struct stc_SMARTIO_PRT_DU_CTL_field {
|
||||
uint32_t u3DU_SIZE:3;
|
||||
uint32_t :5;
|
||||
uint32_t u4DU_OPC:4;
|
||||
uint32_t :20;
|
||||
} stc_SMARTIO_PRT_DU_CTL_field_t;
|
||||
|
||||
typedef union un_SMARTIO_PRT_DU_CTL {
|
||||
uint32_t u32Register;
|
||||
stc_SMARTIO_PRT_DU_CTL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SMARTIO_PRT_DU_CTL_t;
|
||||
|
||||
/**
|
||||
* \brief Data register (SMARTIO_PRT_DATA)
|
||||
*/
|
||||
typedef struct stc_SMARTIO_PRT_DATA_field {
|
||||
uint32_t u8DATA:8;
|
||||
uint32_t :24;
|
||||
} stc_SMARTIO_PRT_DATA_field_t;
|
||||
|
||||
typedef union un_SMARTIO_PRT_DATA {
|
||||
uint32_t u32Register;
|
||||
stc_SMARTIO_PRT_DATA_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_SMARTIO_PRT_DATA_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Programmable IO port registers (SMARTIO_PRT)
|
||||
*/
|
||||
typedef struct stc_SMARTIO_PRT {
|
||||
un_SMARTIO_PRT_CTL_t unCTL; /*!< 0x00000000 Control register */
|
||||
uint32_t au32Reserved[3];
|
||||
un_SMARTIO_PRT_SYNC_CTL_t unSYNC_CTL; /*!< 0x00000010 Synchronization control register */
|
||||
uint32_t au32Reserved1[3];
|
||||
un_SMARTIO_PRT_LUT_SEL_t unLUT_SEL[8]; /*!< 0x00000020 LUT component input selection */
|
||||
un_SMARTIO_PRT_LUT_CTL_t unLUT_CTL[8]; /*!< 0x00000040 LUT component control register */
|
||||
uint32_t au32Reserved2[24];
|
||||
un_SMARTIO_PRT_DU_SEL_t unDU_SEL; /*!< 0x000000C0 Data unit component input selection */
|
||||
un_SMARTIO_PRT_DU_CTL_t unDU_CTL; /*!< 0x000000C4 Data unit component control register */
|
||||
uint32_t au32Reserved3[10];
|
||||
un_SMARTIO_PRT_DATA_t unDATA; /*!< 0x000000F0 Data register */
|
||||
uint32_t au32Reserved4[3];
|
||||
} stc_SMARTIO_PRT_t; /*!< Size = 256 (0x100) */
|
||||
|
||||
/**
|
||||
* \brief Programmable IO configuration (SMARTIO)
|
||||
*/
|
||||
typedef struct stc_SMARTIO {
|
||||
stc_SMARTIO_PRT_t PRT[128]; /*!< 0x00000000 Programmable IO port registers */
|
||||
} stc_SMARTIO_t; /*!< Size = 32768 (0x8000) */
|
||||
|
||||
|
||||
/* SMARTIO_PRT.CTL */
|
||||
#define SMARTIO_PRT_CTL_BYPASS_Pos 0UL
|
||||
#define SMARTIO_PRT_CTL_BYPASS_Msk 0xFFUL
|
||||
#define SMARTIO_PRT_CTL_CLOCK_SRC_Pos 8UL
|
||||
#define SMARTIO_PRT_CTL_CLOCK_SRC_Msk 0x1F00UL
|
||||
#define SMARTIO_PRT_CTL_HLD_OVR_Pos 24UL
|
||||
#define SMARTIO_PRT_CTL_HLD_OVR_Msk 0x1000000UL
|
||||
#define SMARTIO_PRT_CTL_PIPELINE_EN_Pos 25UL
|
||||
#define SMARTIO_PRT_CTL_PIPELINE_EN_Msk 0x2000000UL
|
||||
#define SMARTIO_PRT_CTL_ENABLED_Pos 31UL
|
||||
#define SMARTIO_PRT_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* SMARTIO_PRT.SYNC_CTL */
|
||||
#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Pos 0UL
|
||||
#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Msk 0xFFUL
|
||||
#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Pos 8UL
|
||||
#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Msk 0xFF00UL
|
||||
/* SMARTIO_PRT.LUT_SEL */
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Pos 0UL
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk 0xFUL
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Pos 8UL
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk 0xF00UL
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Pos 16UL
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Msk 0xF0000UL
|
||||
/* SMARTIO_PRT.LUT_CTL */
|
||||
#define SMARTIO_PRT_LUT_CTL_LUT_Pos 0UL
|
||||
#define SMARTIO_PRT_LUT_CTL_LUT_Msk 0xFFUL
|
||||
#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Pos 8UL
|
||||
#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Msk 0x300UL
|
||||
/* SMARTIO_PRT.DU_SEL */
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Pos 0UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk 0xFUL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Pos 8UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk 0xF00UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Pos 16UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Msk 0xF0000UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Pos 24UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Msk 0x3000000UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Pos 28UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Msk 0x30000000UL
|
||||
/* SMARTIO_PRT.DU_CTL */
|
||||
#define SMARTIO_PRT_DU_CTL_DU_SIZE_Pos 0UL
|
||||
#define SMARTIO_PRT_DU_CTL_DU_SIZE_Msk 0x7UL
|
||||
#define SMARTIO_PRT_DU_CTL_DU_OPC_Pos 8UL
|
||||
#define SMARTIO_PRT_DU_CTL_DU_OPC_Msk 0xF00UL
|
||||
/* SMARTIO_PRT.DATA */
|
||||
#define SMARTIO_PRT_DATA_DATA_Pos 0UL
|
||||
#define SMARTIO_PRT_DATA_DATA_Msk 0xFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_SMARTIO_V3_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,652 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyip_tcpwm_v2.h
|
||||
*
|
||||
* \brief
|
||||
* TCPWM IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_TCPWM_V2_H_
|
||||
#define _CYIP_TCPWM_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM_GRP_CNT_SECTION_SIZE 0x00000080UL
|
||||
#define TCPWM_GRP_SECTION_SIZE 0x00008000UL
|
||||
#define TCPWM_SECTION_SIZE 0x00020000UL
|
||||
|
||||
/**
|
||||
* \brief Counter control register (TCPWM_GRP_CNT_CTRL)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_CTRL_field {
|
||||
uint32_t u1AUTO_RELOAD_CC0:1;
|
||||
uint32_t u1AUTO_RELOAD_CC1:1;
|
||||
uint32_t u1AUTO_RELOAD_PERIOD:1;
|
||||
uint32_t u1AUTO_RELOAD_LINE_SEL:1;
|
||||
uint32_t u1CC0_MATCH_UP_EN:1;
|
||||
uint32_t u1CC0_MATCH_DOWN_EN:1;
|
||||
uint32_t u1CC1_MATCH_UP_EN:1;
|
||||
uint32_t u1CC1_MATCH_DOWN_EN:1;
|
||||
uint32_t u1PWM_IMM_KILL:1;
|
||||
uint32_t u1PWM_STOP_ON_KILL:1;
|
||||
uint32_t u1PWM_SYNC_KILL:1;
|
||||
uint32_t :1;
|
||||
uint32_t u2PWM_DISABLE_MODE:2;
|
||||
uint32_t :2;
|
||||
uint32_t u2UP_DOWN_MODE:2;
|
||||
uint32_t u1ONE_SHOT:1;
|
||||
uint32_t :1;
|
||||
uint32_t u2QUAD_ENCODING_MODE:2;
|
||||
uint32_t :2;
|
||||
uint32_t u3MODE:3;
|
||||
uint32_t :3;
|
||||
uint32_t u1DBG_FREEZE_EN:1;
|
||||
uint32_t u1ENABLED:1;
|
||||
} stc_TCPWM_GRP_CNT_CTRL_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_CTRL {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_CTRL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_CTRL_t;
|
||||
|
||||
/**
|
||||
* \brief Counter status register (TCPWM_GRP_CNT_STATUS)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_STATUS_field {
|
||||
uint32_t u1DOWN:1;
|
||||
uint32_t :3;
|
||||
uint32_t u1TR_CAPTURE0:1;
|
||||
uint32_t u1TR_COUNT:1;
|
||||
uint32_t u1TR_RELOAD:1;
|
||||
uint32_t u1TR_STOP:1;
|
||||
uint32_t u1TR_START:1;
|
||||
uint32_t u1TR_CAPTURE1:1;
|
||||
uint32_t u1LINE_OUT:1;
|
||||
uint32_t u1LINE_COMPL_OUT:1;
|
||||
uint32_t :3;
|
||||
uint32_t u1RUNNING:1;
|
||||
uint32_t u8DT_CNT_L:8;
|
||||
uint32_t u8DT_CNT_H:8;
|
||||
} stc_TCPWM_GRP_CNT_STATUS_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_STATUS {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_STATUS_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_STATUS_t;
|
||||
|
||||
/**
|
||||
* \brief Counter count register (TCPWM_GRP_CNT_COUNTER)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_COUNTER_field {
|
||||
uint32_t u32COUNTER:32;
|
||||
} stc_TCPWM_GRP_CNT_COUNTER_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_COUNTER {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_COUNTER_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_COUNTER_t;
|
||||
|
||||
/**
|
||||
* \brief Counter compare/capture 0 register (TCPWM_GRP_CNT_CC0)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_CC0_field {
|
||||
uint32_t u32CC:32;
|
||||
} stc_TCPWM_GRP_CNT_CC0_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_CC0 {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_CC0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_CC0_t;
|
||||
|
||||
/**
|
||||
* \brief Counter buffered compare/capture 0 register (TCPWM_GRP_CNT_CC0_BUFF)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_CC0_BUFF_field {
|
||||
uint32_t u32CC:32;
|
||||
} stc_TCPWM_GRP_CNT_CC0_BUFF_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_CC0_BUFF {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_CC0_BUFF_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_CC0_BUFF_t;
|
||||
|
||||
/**
|
||||
* \brief Counter compare/capture 1 register (TCPWM_GRP_CNT_CC1)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_CC1_field {
|
||||
uint32_t u32CC:32;
|
||||
} stc_TCPWM_GRP_CNT_CC1_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_CC1 {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_CC1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_CC1_t;
|
||||
|
||||
/**
|
||||
* \brief Counter buffered compare/capture 1 register (TCPWM_GRP_CNT_CC1_BUFF)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_CC1_BUFF_field {
|
||||
uint32_t u32CC:32;
|
||||
} stc_TCPWM_GRP_CNT_CC1_BUFF_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_CC1_BUFF {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_CC1_BUFF_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_CC1_BUFF_t;
|
||||
|
||||
/**
|
||||
* \brief Counter period register (TCPWM_GRP_CNT_PERIOD)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_PERIOD_field {
|
||||
uint32_t u32PERIOD:32;
|
||||
} stc_TCPWM_GRP_CNT_PERIOD_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_PERIOD {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_PERIOD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_PERIOD_t;
|
||||
|
||||
/**
|
||||
* \brief Counter buffered period register (TCPWM_GRP_CNT_PERIOD_BUFF)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_PERIOD_BUFF_field {
|
||||
uint32_t u32PERIOD:32;
|
||||
} stc_TCPWM_GRP_CNT_PERIOD_BUFF_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_PERIOD_BUFF {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_PERIOD_BUFF_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_PERIOD_BUFF_t;
|
||||
|
||||
/**
|
||||
* \brief Counter line selection register (TCPWM_GRP_CNT_LINE_SEL)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_LINE_SEL_field {
|
||||
uint32_t u3OUT_SEL:3;
|
||||
uint32_t :1;
|
||||
uint32_t u3COMPL_OUT_SEL:3;
|
||||
uint32_t :25;
|
||||
} stc_TCPWM_GRP_CNT_LINE_SEL_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_LINE_SEL {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_LINE_SEL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_LINE_SEL_t;
|
||||
|
||||
/**
|
||||
* \brief Counter buffered line selection register (TCPWM_GRP_CNT_LINE_SEL_BUFF)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_LINE_SEL_BUFF_field {
|
||||
uint32_t u3OUT_SEL:3;
|
||||
uint32_t :1;
|
||||
uint32_t u3COMPL_OUT_SEL:3;
|
||||
uint32_t :25;
|
||||
} stc_TCPWM_GRP_CNT_LINE_SEL_BUFF_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_LINE_SEL_BUFF {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_LINE_SEL_BUFF_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t;
|
||||
|
||||
/**
|
||||
* \brief Counter PWM dead time register (TCPWM_GRP_CNT_DT)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_DT_field {
|
||||
uint32_t u8DT_LINE_OUT_L:8;
|
||||
uint32_t u8DT_LINE_OUT_H:8;
|
||||
uint32_t u16DT_LINE_COMPL_OUT:16;
|
||||
} stc_TCPWM_GRP_CNT_DT_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_DT {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_DT_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_DT_t;
|
||||
|
||||
/**
|
||||
* \brief Counter trigger command register (TCPWM_GRP_CNT_TR_CMD)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_TR_CMD_field {
|
||||
uint32_t u1CAPTURE0:1;
|
||||
uint32_t :1;
|
||||
uint32_t u1RELOAD:1;
|
||||
uint32_t u1STOP:1;
|
||||
uint32_t u1START:1;
|
||||
uint32_t u1CAPTURE1:1;
|
||||
uint32_t :26;
|
||||
} stc_TCPWM_GRP_CNT_TR_CMD_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_TR_CMD {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_TR_CMD_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_TR_CMD_t;
|
||||
|
||||
/**
|
||||
* \brief Counter input trigger selection register 0 (TCPWM_GRP_CNT_TR_IN_SEL0)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_TR_IN_SEL0_field {
|
||||
uint32_t u8CAPTURE0_SEL:8;
|
||||
uint32_t u8COUNT_SEL:8;
|
||||
uint32_t u8RELOAD_SEL:8;
|
||||
uint32_t u8STOP_SEL:8;
|
||||
} stc_TCPWM_GRP_CNT_TR_IN_SEL0_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_TR_IN_SEL0 {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_TR_IN_SEL0_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_TR_IN_SEL0_t;
|
||||
|
||||
/**
|
||||
* \brief Counter input trigger selection register 1 (TCPWM_GRP_CNT_TR_IN_SEL1)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_TR_IN_SEL1_field {
|
||||
uint32_t u8START_SEL:8;
|
||||
uint32_t u8CAPTURE1_SEL:8;
|
||||
uint32_t :16;
|
||||
} stc_TCPWM_GRP_CNT_TR_IN_SEL1_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_TR_IN_SEL1 {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_TR_IN_SEL1_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_TR_IN_SEL1_t;
|
||||
|
||||
/**
|
||||
* \brief Counter input trigger edge selection register (TCPWM_GRP_CNT_TR_IN_EDGE_SEL)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_field {
|
||||
uint32_t u2CAPTURE0_EDGE:2;
|
||||
uint32_t u2COUNT_EDGE:2;
|
||||
uint32_t u2RELOAD_EDGE:2;
|
||||
uint32_t u2STOP_EDGE:2;
|
||||
uint32_t u2START_EDGE:2;
|
||||
uint32_t u2CAPTURE1_EDGE:2;
|
||||
uint32_t :20;
|
||||
} stc_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t;
|
||||
|
||||
/**
|
||||
* \brief Counter trigger PWM control register (TCPWM_GRP_CNT_TR_PWM_CTRL)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_TR_PWM_CTRL_field {
|
||||
uint32_t u2CC0_MATCH_MODE:2;
|
||||
uint32_t u2OVERFLOW_MODE:2;
|
||||
uint32_t u2UNDERFLOW_MODE:2;
|
||||
uint32_t u2CC1_MATCH_MODE:2;
|
||||
uint32_t :24;
|
||||
} stc_TCPWM_GRP_CNT_TR_PWM_CTRL_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_TR_PWM_CTRL {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_TR_PWM_CTRL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_TR_PWM_CTRL_t;
|
||||
|
||||
/**
|
||||
* \brief Counter output trigger selection register (TCPWM_GRP_CNT_TR_OUT_SEL)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_TR_OUT_SEL_field {
|
||||
uint32_t u3OUT0:3;
|
||||
uint32_t :1;
|
||||
uint32_t u3OUT1:3;
|
||||
uint32_t :25;
|
||||
} stc_TCPWM_GRP_CNT_TR_OUT_SEL_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_TR_OUT_SEL {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_TR_OUT_SEL_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_TR_OUT_SEL_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt request register (TCPWM_GRP_CNT_INTR)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_INTR_field {
|
||||
uint32_t u1TC:1;
|
||||
uint32_t u1CC0_MATCH:1;
|
||||
uint32_t u1CC1_MATCH:1;
|
||||
uint32_t :29;
|
||||
} stc_TCPWM_GRP_CNT_INTR_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_INTR {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_INTR_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_INTR_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt set request register (TCPWM_GRP_CNT_INTR_SET)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_INTR_SET_field {
|
||||
uint32_t u1TC:1;
|
||||
uint32_t u1CC0_MATCH:1;
|
||||
uint32_t u1CC1_MATCH:1;
|
||||
uint32_t :29;
|
||||
} stc_TCPWM_GRP_CNT_INTR_SET_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_INTR_SET {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_INTR_SET_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_INTR_SET_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt mask register (TCPWM_GRP_CNT_INTR_MASK)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_INTR_MASK_field {
|
||||
uint32_t u1TC:1;
|
||||
uint32_t u1CC0_MATCH:1;
|
||||
uint32_t u1CC1_MATCH:1;
|
||||
uint32_t :29;
|
||||
} stc_TCPWM_GRP_CNT_INTR_MASK_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_INTR_MASK {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_INTR_MASK_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_INTR_MASK_t;
|
||||
|
||||
/**
|
||||
* \brief Interrupt masked request register (TCPWM_GRP_CNT_INTR_MASKED)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT_INTR_MASKED_field {
|
||||
uint32_t u1TC:1;
|
||||
uint32_t u1CC0_MATCH:1;
|
||||
uint32_t u1CC1_MATCH:1;
|
||||
uint32_t :29;
|
||||
} stc_TCPWM_GRP_CNT_INTR_MASKED_field_t;
|
||||
|
||||
typedef union un_TCPWM_GRP_CNT_INTR_MASKED {
|
||||
uint32_t u32Register;
|
||||
stc_TCPWM_GRP_CNT_INTR_MASKED_field_t stcField;
|
||||
uint8_t au8Byte[4];
|
||||
uint16_t au16Halfword[2];
|
||||
} un_TCPWM_GRP_CNT_INTR_MASKED_t;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP_CNT {
|
||||
un_TCPWM_GRP_CNT_CTRL_t unCTRL; /*!< 0x00000000 Counter control register */
|
||||
un_TCPWM_GRP_CNT_STATUS_t unSTATUS; /*!< 0x00000004 Counter status register */
|
||||
un_TCPWM_GRP_CNT_COUNTER_t unCOUNTER; /*!< 0x00000008 Counter count register */
|
||||
uint32_t u32Reserved;
|
||||
un_TCPWM_GRP_CNT_CC0_t unCC0; /*!< 0x00000010 Counter compare/capture 0 register */
|
||||
un_TCPWM_GRP_CNT_CC0_BUFF_t unCC0_BUFF; /*!< 0x00000014 Counter buffered compare/capture 0 register */
|
||||
un_TCPWM_GRP_CNT_CC1_t unCC1; /*!< 0x00000018 Counter compare/capture 1 register */
|
||||
un_TCPWM_GRP_CNT_CC1_BUFF_t unCC1_BUFF; /*!< 0x0000001C Counter buffered compare/capture 1 register */
|
||||
un_TCPWM_GRP_CNT_PERIOD_t unPERIOD; /*!< 0x00000020 Counter period register */
|
||||
un_TCPWM_GRP_CNT_PERIOD_BUFF_t unPERIOD_BUFF; /*!< 0x00000024 Counter buffered period register */
|
||||
un_TCPWM_GRP_CNT_LINE_SEL_t unLINE_SEL; /*!< 0x00000028 Counter line selection register */
|
||||
un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t unLINE_SEL_BUFF; /*!< 0x0000002C Counter buffered line selection register */
|
||||
un_TCPWM_GRP_CNT_DT_t unDT; /*!< 0x00000030 Counter PWM dead time register */
|
||||
uint32_t au32Reserved1[3];
|
||||
un_TCPWM_GRP_CNT_TR_CMD_t unTR_CMD; /*!< 0x00000040 Counter trigger command register */
|
||||
un_TCPWM_GRP_CNT_TR_IN_SEL0_t unTR_IN_SEL0; /*!< 0x00000044 Counter input trigger selection register 0 */
|
||||
un_TCPWM_GRP_CNT_TR_IN_SEL1_t unTR_IN_SEL1; /*!< 0x00000048 Counter input trigger selection register 1 */
|
||||
un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t unTR_IN_EDGE_SEL; /*!< 0x0000004C Counter input trigger edge selection register */
|
||||
un_TCPWM_GRP_CNT_TR_PWM_CTRL_t unTR_PWM_CTRL; /*!< 0x00000050 Counter trigger PWM control register */
|
||||
un_TCPWM_GRP_CNT_TR_OUT_SEL_t unTR_OUT_SEL; /*!< 0x00000054 Counter output trigger selection register */
|
||||
uint32_t au32Reserved2[6];
|
||||
un_TCPWM_GRP_CNT_INTR_t unINTR; /*!< 0x00000070 Interrupt request register */
|
||||
un_TCPWM_GRP_CNT_INTR_SET_t unINTR_SET; /*!< 0x00000074 Interrupt set request register */
|
||||
un_TCPWM_GRP_CNT_INTR_MASK_t unINTR_MASK; /*!< 0x00000078 Interrupt mask register */
|
||||
un_TCPWM_GRP_CNT_INTR_MASKED_t unINTR_MASKED; /*!< 0x0000007C Interrupt masked request register */
|
||||
} stc_TCPWM_GRP_CNT_t; /*!< Size = 128 (0x80) */
|
||||
|
||||
/**
|
||||
* \brief Group of counters (TCPWM_GRP)
|
||||
*/
|
||||
typedef struct stc_TCPWM_GRP {
|
||||
stc_TCPWM_GRP_CNT_t CNT[256]; /*!< 0x00000000 Timer/Counter/PWM Counter Module */
|
||||
} stc_TCPWM_GRP_t; /*!< Size = 32768 (0x8000) */
|
||||
|
||||
/**
|
||||
* \brief Timer/Counter/PWM (TCPWM)
|
||||
*/
|
||||
typedef struct stc_TCPWM {
|
||||
stc_TCPWM_GRP_t GRP[4]; /*!< 0x00000000 Group of counters */
|
||||
} stc_TCPWM_t; /*!< Size = 131072 (0x20000) */
|
||||
|
||||
|
||||
/* TCPWM_GRP_CNT.CTRL */
|
||||
#define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Msk 0x1UL
|
||||
#define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Pos 1UL
|
||||
#define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Msk 0x2UL
|
||||
#define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos 2UL
|
||||
#define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk 0x4UL
|
||||
#define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Pos 3UL
|
||||
#define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Msk 0x8UL
|
||||
#define TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Pos 4UL
|
||||
#define TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Msk 0x10UL
|
||||
#define TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Pos 5UL
|
||||
#define TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Msk 0x20UL
|
||||
#define TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Pos 6UL
|
||||
#define TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Msk 0x40UL
|
||||
#define TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Pos 7UL
|
||||
#define TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Msk 0x80UL
|
||||
#define TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Pos 8UL
|
||||
#define TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Msk 0x100UL
|
||||
#define TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Pos 9UL
|
||||
#define TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Msk 0x200UL
|
||||
#define TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Pos 10UL
|
||||
#define TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Msk 0x400UL
|
||||
#define TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Pos 12UL
|
||||
#define TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Msk 0x3000UL
|
||||
#define TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Pos 16UL
|
||||
#define TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Msk 0x30000UL
|
||||
#define TCPWM_GRP_CNT_CTRL_ONE_SHOT_Pos 18UL
|
||||
#define TCPWM_GRP_CNT_CTRL_ONE_SHOT_Msk 0x40000UL
|
||||
#define TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Pos 20UL
|
||||
#define TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Msk 0x300000UL
|
||||
#define TCPWM_GRP_CNT_CTRL_MODE_Pos 24UL
|
||||
#define TCPWM_GRP_CNT_CTRL_MODE_Msk 0x7000000UL
|
||||
#define TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Pos 30UL
|
||||
#define TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Msk 0x40000000UL
|
||||
#define TCPWM_GRP_CNT_CTRL_ENABLED_Pos 31UL
|
||||
#define TCPWM_GRP_CNT_CTRL_ENABLED_Msk 0x80000000UL
|
||||
/* TCPWM_GRP_CNT.STATUS */
|
||||
#define TCPWM_GRP_CNT_STATUS_DOWN_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_STATUS_DOWN_Msk 0x1UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Pos 4UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Msk 0x10UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_COUNT_Pos 5UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_COUNT_Msk 0x20UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_RELOAD_Pos 6UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_RELOAD_Msk 0x40UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_STOP_Pos 7UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_STOP_Msk 0x80UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_START_Pos 8UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_START_Msk 0x100UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Pos 9UL
|
||||
#define TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Msk 0x200UL
|
||||
#define TCPWM_GRP_CNT_STATUS_LINE_OUT_Pos 10UL
|
||||
#define TCPWM_GRP_CNT_STATUS_LINE_OUT_Msk 0x400UL
|
||||
#define TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Pos 11UL
|
||||
#define TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Msk 0x800UL
|
||||
#define TCPWM_GRP_CNT_STATUS_RUNNING_Pos 15UL
|
||||
#define TCPWM_GRP_CNT_STATUS_RUNNING_Msk 0x8000UL
|
||||
#define TCPWM_GRP_CNT_STATUS_DT_CNT_L_Pos 16UL
|
||||
#define TCPWM_GRP_CNT_STATUS_DT_CNT_L_Msk 0xFF0000UL
|
||||
#define TCPWM_GRP_CNT_STATUS_DT_CNT_H_Pos 24UL
|
||||
#define TCPWM_GRP_CNT_STATUS_DT_CNT_H_Msk 0xFF000000UL
|
||||
/* TCPWM_GRP_CNT.COUNTER */
|
||||
#define TCPWM_GRP_CNT_COUNTER_COUNTER_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_COUNTER_COUNTER_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_GRP_CNT.CC0 */
|
||||
#define TCPWM_GRP_CNT_CC0_CC_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_CC0_CC_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_GRP_CNT.CC0_BUFF */
|
||||
#define TCPWM_GRP_CNT_CC0_BUFF_CC_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_CC0_BUFF_CC_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_GRP_CNT.CC1 */
|
||||
#define TCPWM_GRP_CNT_CC1_CC_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_CC1_CC_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_GRP_CNT.CC1_BUFF */
|
||||
#define TCPWM_GRP_CNT_CC1_BUFF_CC_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_CC1_BUFF_CC_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_GRP_CNT.PERIOD */
|
||||
#define TCPWM_GRP_CNT_PERIOD_PERIOD_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_PERIOD_PERIOD_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_GRP_CNT.PERIOD_BUFF */
|
||||
#define TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_GRP_CNT.LINE_SEL */
|
||||
#define TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Msk 0x7UL
|
||||
#define TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Pos 4UL
|
||||
#define TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Msk 0x70UL
|
||||
/* TCPWM_GRP_CNT.LINE_SEL_BUFF */
|
||||
#define TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Msk 0x7UL
|
||||
#define TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos 4UL
|
||||
#define TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk 0x70UL
|
||||
/* TCPWM_GRP_CNT.DT */
|
||||
#define TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Msk 0xFFUL
|
||||
#define TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Pos 8UL
|
||||
#define TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Msk 0xFF00UL
|
||||
#define TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Pos 16UL
|
||||
#define TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Msk 0xFFFF0000UL
|
||||
/* TCPWM_GRP_CNT.TR_CMD */
|
||||
#define TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Msk 0x1UL
|
||||
#define TCPWM_GRP_CNT_TR_CMD_RELOAD_Pos 2UL
|
||||
#define TCPWM_GRP_CNT_TR_CMD_RELOAD_Msk 0x4UL
|
||||
#define TCPWM_GRP_CNT_TR_CMD_STOP_Pos 3UL
|
||||
#define TCPWM_GRP_CNT_TR_CMD_STOP_Msk 0x8UL
|
||||
#define TCPWM_GRP_CNT_TR_CMD_START_Pos 4UL
|
||||
#define TCPWM_GRP_CNT_TR_CMD_START_Msk 0x10UL
|
||||
#define TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Pos 5UL
|
||||
#define TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Msk 0x20UL
|
||||
/* TCPWM_GRP_CNT.TR_IN_SEL0 */
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Msk 0xFFUL
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Pos 8UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Msk 0xFF00UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Pos 16UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Msk 0xFF0000UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Pos 24UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Msk 0xFF000000UL
|
||||
/* TCPWM_GRP_CNT.TR_IN_SEL1 */
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Msk 0xFFUL
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Pos 8UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Msk 0xFF00UL
|
||||
/* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk 0x3UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Pos 2UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Msk 0xCUL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos 4UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk 0x30UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Pos 6UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Msk 0xC0UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Pos 8UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Msk 0x300UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos 10UL
|
||||
#define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk 0xC00UL
|
||||
/* TCPWM_GRP_CNT.TR_PWM_CTRL */
|
||||
#define TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Msk 0x3UL
|
||||
#define TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Pos 2UL
|
||||
#define TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Msk 0xCUL
|
||||
#define TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Pos 4UL
|
||||
#define TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Msk 0x30UL
|
||||
#define TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Pos 6UL
|
||||
#define TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Msk 0xC0UL
|
||||
/* TCPWM_GRP_CNT.TR_OUT_SEL */
|
||||
#define TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Msk 0x7UL
|
||||
#define TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Pos 4UL
|
||||
#define TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Msk 0x70UL
|
||||
/* TCPWM_GRP_CNT.INTR */
|
||||
#define TCPWM_GRP_CNT_INTR_TC_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_INTR_TC_Msk 0x1UL
|
||||
#define TCPWM_GRP_CNT_INTR_CC0_MATCH_Pos 1UL
|
||||
#define TCPWM_GRP_CNT_INTR_CC0_MATCH_Msk 0x2UL
|
||||
#define TCPWM_GRP_CNT_INTR_CC1_MATCH_Pos 2UL
|
||||
#define TCPWM_GRP_CNT_INTR_CC1_MATCH_Msk 0x4UL
|
||||
/* TCPWM_GRP_CNT.INTR_SET */
|
||||
#define TCPWM_GRP_CNT_INTR_SET_TC_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_INTR_SET_TC_Msk 0x1UL
|
||||
#define TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Pos 1UL
|
||||
#define TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Msk 0x2UL
|
||||
#define TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Pos 2UL
|
||||
#define TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Msk 0x4UL
|
||||
/* TCPWM_GRP_CNT.INTR_MASK */
|
||||
#define TCPWM_GRP_CNT_INTR_MASK_TC_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_INTR_MASK_TC_Msk 0x1UL
|
||||
#define TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Pos 1UL
|
||||
#define TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Msk 0x2UL
|
||||
#define TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Pos 2UL
|
||||
#define TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Msk 0x4UL
|
||||
/* TCPWM_GRP_CNT.INTR_MASKED */
|
||||
#define TCPWM_GRP_CNT_INTR_MASKED_TC_Pos 0UL
|
||||
#define TCPWM_GRP_CNT_INTR_MASKED_TC_Msk 0x1UL
|
||||
#define TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Pos 1UL
|
||||
#define TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Msk 0x2UL
|
||||
#define TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Pos 2UL
|
||||
#define TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Msk 0x4UL
|
||||
|
||||
|
||||
#endif /* _CYIP_TCPWM_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,50 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_backup.h
|
||||
*
|
||||
* \brief
|
||||
* BACKUP register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_BACKUP_H_
|
||||
#define _CYREG_BACKUP_H_
|
||||
|
||||
#include "cyip_backup_v3.h"
|
||||
|
||||
/**
|
||||
* \brief SRSS Backup Domain (ver3) (BACKUP)
|
||||
*/
|
||||
#define CYREG_BACKUP_CTL ((volatile un_BACKUP_CTL_t*) 0x40270000UL)
|
||||
#define CYREG_BACKUP_RTC_RW ((volatile un_BACKUP_RTC_RW_t*) 0x40270008UL)
|
||||
#define CYREG_BACKUP_CAL_CTL ((volatile un_BACKUP_CAL_CTL_t*) 0x4027000CUL)
|
||||
#define CYREG_BACKUP_STATUS ((volatile un_BACKUP_STATUS_t*) 0x40270010UL)
|
||||
#define CYREG_BACKUP_RTC_TIME ((volatile un_BACKUP_RTC_TIME_t*) 0x40270014UL)
|
||||
#define CYREG_BACKUP_RTC_DATE ((volatile un_BACKUP_RTC_DATE_t*) 0x40270018UL)
|
||||
#define CYREG_BACKUP_ALM1_TIME ((volatile un_BACKUP_ALM1_TIME_t*) 0x4027001CUL)
|
||||
#define CYREG_BACKUP_ALM1_DATE ((volatile un_BACKUP_ALM1_DATE_t*) 0x40270020UL)
|
||||
#define CYREG_BACKUP_ALM2_TIME ((volatile un_BACKUP_ALM2_TIME_t*) 0x40270024UL)
|
||||
#define CYREG_BACKUP_ALM2_DATE ((volatile un_BACKUP_ALM2_DATE_t*) 0x40270028UL)
|
||||
#define CYREG_BACKUP_INTR ((volatile un_BACKUP_INTR_t*) 0x4027002CUL)
|
||||
#define CYREG_BACKUP_INTR_SET ((volatile un_BACKUP_INTR_SET_t*) 0x40270030UL)
|
||||
#define CYREG_BACKUP_INTR_MASK ((volatile un_BACKUP_INTR_MASK_t*) 0x40270034UL)
|
||||
#define CYREG_BACKUP_INTR_MASKED ((volatile un_BACKUP_INTR_MASKED_t*) 0x40270038UL)
|
||||
#define CYREG_BACKUP_RESET ((volatile un_BACKUP_RESET_t*) 0x40270048UL)
|
||||
#define CYREG_BACKUP_BREG0 ((volatile un_BACKUP_BREG_t*) 0x40271000UL)
|
||||
#define CYREG_BACKUP_BREG1 ((volatile un_BACKUP_BREG_t*) 0x40271004UL)
|
||||
#define CYREG_BACKUP_BREG2 ((volatile un_BACKUP_BREG_t*) 0x40271008UL)
|
||||
#define CYREG_BACKUP_BREG3 ((volatile un_BACKUP_BREG_t*) 0x4027100CUL)
|
||||
|
||||
#endif /* _CYREG_BACKUP_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,809 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_canfd.h
|
||||
*
|
||||
* \brief
|
||||
* CANFD register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_CANFD_H_
|
||||
#define _CYREG_CANFD_H_
|
||||
|
||||
#include "cyip_canfd.h"
|
||||
|
||||
/**
|
||||
* \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN0)
|
||||
*/
|
||||
#define CYREG_CANFD0_CH0_CREL ((volatile un_CANFD_CH_CREL_t*) 0x40520000UL)
|
||||
#define CYREG_CANFD0_CH0_ENDN ((volatile un_CANFD_CH_ENDN_t*) 0x40520004UL)
|
||||
#define CYREG_CANFD0_CH0_DBTP ((volatile un_CANFD_CH_DBTP_t*) 0x4052000CUL)
|
||||
#define CYREG_CANFD0_CH0_TEST ((volatile un_CANFD_CH_TEST_t*) 0x40520010UL)
|
||||
#define CYREG_CANFD0_CH0_RWD ((volatile un_CANFD_CH_RWD_t*) 0x40520014UL)
|
||||
#define CYREG_CANFD0_CH0_CCCR ((volatile un_CANFD_CH_CCCR_t*) 0x40520018UL)
|
||||
#define CYREG_CANFD0_CH0_NBTP ((volatile un_CANFD_CH_NBTP_t*) 0x4052001CUL)
|
||||
#define CYREG_CANFD0_CH0_TSCC ((volatile un_CANFD_CH_TSCC_t*) 0x40520020UL)
|
||||
#define CYREG_CANFD0_CH0_TSCV ((volatile un_CANFD_CH_TSCV_t*) 0x40520024UL)
|
||||
#define CYREG_CANFD0_CH0_TOCC ((volatile un_CANFD_CH_TOCC_t*) 0x40520028UL)
|
||||
#define CYREG_CANFD0_CH0_TOCV ((volatile un_CANFD_CH_TOCV_t*) 0x4052002CUL)
|
||||
#define CYREG_CANFD0_CH0_ECR ((volatile un_CANFD_CH_ECR_t*) 0x40520040UL)
|
||||
#define CYREG_CANFD0_CH0_PSR ((volatile un_CANFD_CH_PSR_t*) 0x40520044UL)
|
||||
#define CYREG_CANFD0_CH0_TDCR ((volatile un_CANFD_CH_TDCR_t*) 0x40520048UL)
|
||||
#define CYREG_CANFD0_CH0_IR ((volatile un_CANFD_CH_IR_t*) 0x40520050UL)
|
||||
#define CYREG_CANFD0_CH0_IE ((volatile un_CANFD_CH_IE_t*) 0x40520054UL)
|
||||
#define CYREG_CANFD0_CH0_ILS ((volatile un_CANFD_CH_ILS_t*) 0x40520058UL)
|
||||
#define CYREG_CANFD0_CH0_ILE ((volatile un_CANFD_CH_ILE_t*) 0x4052005CUL)
|
||||
#define CYREG_CANFD0_CH0_GFC ((volatile un_CANFD_CH_GFC_t*) 0x40520080UL)
|
||||
#define CYREG_CANFD0_CH0_SIDFC ((volatile un_CANFD_CH_SIDFC_t*) 0x40520084UL)
|
||||
#define CYREG_CANFD0_CH0_XIDFC ((volatile un_CANFD_CH_XIDFC_t*) 0x40520088UL)
|
||||
#define CYREG_CANFD0_CH0_XIDAM ((volatile un_CANFD_CH_XIDAM_t*) 0x40520090UL)
|
||||
#define CYREG_CANFD0_CH0_HPMS ((volatile un_CANFD_CH_HPMS_t*) 0x40520094UL)
|
||||
#define CYREG_CANFD0_CH0_NDAT1 ((volatile un_CANFD_CH_NDAT1_t*) 0x40520098UL)
|
||||
#define CYREG_CANFD0_CH0_NDAT2 ((volatile un_CANFD_CH_NDAT2_t*) 0x4052009CUL)
|
||||
#define CYREG_CANFD0_CH0_RXF0C ((volatile un_CANFD_CH_RXF0C_t*) 0x405200A0UL)
|
||||
#define CYREG_CANFD0_CH0_RXF0S ((volatile un_CANFD_CH_RXF0S_t*) 0x405200A4UL)
|
||||
#define CYREG_CANFD0_CH0_RXF0A ((volatile un_CANFD_CH_RXF0A_t*) 0x405200A8UL)
|
||||
#define CYREG_CANFD0_CH0_RXBC ((volatile un_CANFD_CH_RXBC_t*) 0x405200ACUL)
|
||||
#define CYREG_CANFD0_CH0_RXF1C ((volatile un_CANFD_CH_RXF1C_t*) 0x405200B0UL)
|
||||
#define CYREG_CANFD0_CH0_RXF1S ((volatile un_CANFD_CH_RXF1S_t*) 0x405200B4UL)
|
||||
#define CYREG_CANFD0_CH0_RXF1A ((volatile un_CANFD_CH_RXF1A_t*) 0x405200B8UL)
|
||||
#define CYREG_CANFD0_CH0_RXESC ((volatile un_CANFD_CH_RXESC_t*) 0x405200BCUL)
|
||||
#define CYREG_CANFD0_CH0_TXBC ((volatile un_CANFD_CH_TXBC_t*) 0x405200C0UL)
|
||||
#define CYREG_CANFD0_CH0_TXFQS ((volatile un_CANFD_CH_TXFQS_t*) 0x405200C4UL)
|
||||
#define CYREG_CANFD0_CH0_TXESC ((volatile un_CANFD_CH_TXESC_t*) 0x405200C8UL)
|
||||
#define CYREG_CANFD0_CH0_TXBRP ((volatile un_CANFD_CH_TXBRP_t*) 0x405200CCUL)
|
||||
#define CYREG_CANFD0_CH0_TXBAR ((volatile un_CANFD_CH_TXBAR_t*) 0x405200D0UL)
|
||||
#define CYREG_CANFD0_CH0_TXBCR ((volatile un_CANFD_CH_TXBCR_t*) 0x405200D4UL)
|
||||
#define CYREG_CANFD0_CH0_TXBTO ((volatile un_CANFD_CH_TXBTO_t*) 0x405200D8UL)
|
||||
#define CYREG_CANFD0_CH0_TXBCF ((volatile un_CANFD_CH_TXBCF_t*) 0x405200DCUL)
|
||||
#define CYREG_CANFD0_CH0_TXBTIE ((volatile un_CANFD_CH_TXBTIE_t*) 0x405200E0UL)
|
||||
#define CYREG_CANFD0_CH0_TXBCIE ((volatile un_CANFD_CH_TXBCIE_t*) 0x405200E4UL)
|
||||
#define CYREG_CANFD0_CH0_TXEFC ((volatile un_CANFD_CH_TXEFC_t*) 0x405200F0UL)
|
||||
#define CYREG_CANFD0_CH0_TXEFS ((volatile un_CANFD_CH_TXEFS_t*) 0x405200F4UL)
|
||||
#define CYREG_CANFD0_CH0_TXEFA ((volatile un_CANFD_CH_TXEFA_t*) 0x405200F8UL)
|
||||
#define CYREG_CANFD0_CH0_TTTMC ((volatile un_CANFD_CH_TTTMC_t*) 0x40520100UL)
|
||||
#define CYREG_CANFD0_CH0_TTRMC ((volatile un_CANFD_CH_TTRMC_t*) 0x40520104UL)
|
||||
#define CYREG_CANFD0_CH0_TTOCF ((volatile un_CANFD_CH_TTOCF_t*) 0x40520108UL)
|
||||
#define CYREG_CANFD0_CH0_TTMLM ((volatile un_CANFD_CH_TTMLM_t*) 0x4052010CUL)
|
||||
#define CYREG_CANFD0_CH0_TURCF ((volatile un_CANFD_CH_TURCF_t*) 0x40520110UL)
|
||||
#define CYREG_CANFD0_CH0_TTOCN ((volatile un_CANFD_CH_TTOCN_t*) 0x40520114UL)
|
||||
#define CYREG_CANFD0_CH0_TTGTP ((volatile un_CANFD_CH_TTGTP_t*) 0x40520118UL)
|
||||
#define CYREG_CANFD0_CH0_TTTMK ((volatile un_CANFD_CH_TTTMK_t*) 0x4052011CUL)
|
||||
#define CYREG_CANFD0_CH0_TTIR ((volatile un_CANFD_CH_TTIR_t*) 0x40520120UL)
|
||||
#define CYREG_CANFD0_CH0_TTIE ((volatile un_CANFD_CH_TTIE_t*) 0x40520124UL)
|
||||
#define CYREG_CANFD0_CH0_TTILS ((volatile un_CANFD_CH_TTILS_t*) 0x40520128UL)
|
||||
#define CYREG_CANFD0_CH0_TTOST ((volatile un_CANFD_CH_TTOST_t*) 0x4052012CUL)
|
||||
#define CYREG_CANFD0_CH0_TURNA ((volatile un_CANFD_CH_TURNA_t*) 0x40520130UL)
|
||||
#define CYREG_CANFD0_CH0_TTLGT ((volatile un_CANFD_CH_TTLGT_t*) 0x40520134UL)
|
||||
#define CYREG_CANFD0_CH0_TTCTC ((volatile un_CANFD_CH_TTCTC_t*) 0x40520138UL)
|
||||
#define CYREG_CANFD0_CH0_TTCPT ((volatile un_CANFD_CH_TTCPT_t*) 0x4052013CUL)
|
||||
#define CYREG_CANFD0_CH0_TTCSM ((volatile un_CANFD_CH_TTCSM_t*) 0x40520140UL)
|
||||
|
||||
/**
|
||||
* \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH0)
|
||||
*/
|
||||
#define CYREG_CANFD0_CH0_RXFTOP_CTL ((volatile un_CANFD_CH_RXFTOP_CTL_t*) 0x40520180UL)
|
||||
#define CYREG_CANFD0_CH0_RXFTOP0_STAT ((volatile un_CANFD_CH_RXFTOP0_STAT_t*) 0x405201A0UL)
|
||||
#define CYREG_CANFD0_CH0_RXFTOP0_DATA ((volatile un_CANFD_CH_RXFTOP0_DATA_t*) 0x405201A8UL)
|
||||
#define CYREG_CANFD0_CH0_RXFTOP1_STAT ((volatile un_CANFD_CH_RXFTOP1_STAT_t*) 0x405201B0UL)
|
||||
#define CYREG_CANFD0_CH0_RXFTOP1_DATA ((volatile un_CANFD_CH_RXFTOP1_DATA_t*) 0x405201B8UL)
|
||||
|
||||
/**
|
||||
* \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN0)
|
||||
*/
|
||||
#define CYREG_CANFD0_CH1_CREL ((volatile un_CANFD_CH_CREL_t*) 0x40520200UL)
|
||||
#define CYREG_CANFD0_CH1_ENDN ((volatile un_CANFD_CH_ENDN_t*) 0x40520204UL)
|
||||
#define CYREG_CANFD0_CH1_DBTP ((volatile un_CANFD_CH_DBTP_t*) 0x4052020CUL)
|
||||
#define CYREG_CANFD0_CH1_TEST ((volatile un_CANFD_CH_TEST_t*) 0x40520210UL)
|
||||
#define CYREG_CANFD0_CH1_RWD ((volatile un_CANFD_CH_RWD_t*) 0x40520214UL)
|
||||
#define CYREG_CANFD0_CH1_CCCR ((volatile un_CANFD_CH_CCCR_t*) 0x40520218UL)
|
||||
#define CYREG_CANFD0_CH1_NBTP ((volatile un_CANFD_CH_NBTP_t*) 0x4052021CUL)
|
||||
#define CYREG_CANFD0_CH1_TSCC ((volatile un_CANFD_CH_TSCC_t*) 0x40520220UL)
|
||||
#define CYREG_CANFD0_CH1_TSCV ((volatile un_CANFD_CH_TSCV_t*) 0x40520224UL)
|
||||
#define CYREG_CANFD0_CH1_TOCC ((volatile un_CANFD_CH_TOCC_t*) 0x40520228UL)
|
||||
#define CYREG_CANFD0_CH1_TOCV ((volatile un_CANFD_CH_TOCV_t*) 0x4052022CUL)
|
||||
#define CYREG_CANFD0_CH1_ECR ((volatile un_CANFD_CH_ECR_t*) 0x40520240UL)
|
||||
#define CYREG_CANFD0_CH1_PSR ((volatile un_CANFD_CH_PSR_t*) 0x40520244UL)
|
||||
#define CYREG_CANFD0_CH1_TDCR ((volatile un_CANFD_CH_TDCR_t*) 0x40520248UL)
|
||||
#define CYREG_CANFD0_CH1_IR ((volatile un_CANFD_CH_IR_t*) 0x40520250UL)
|
||||
#define CYREG_CANFD0_CH1_IE ((volatile un_CANFD_CH_IE_t*) 0x40520254UL)
|
||||
#define CYREG_CANFD0_CH1_ILS ((volatile un_CANFD_CH_ILS_t*) 0x40520258UL)
|
||||
#define CYREG_CANFD0_CH1_ILE ((volatile un_CANFD_CH_ILE_t*) 0x4052025CUL)
|
||||
#define CYREG_CANFD0_CH1_GFC ((volatile un_CANFD_CH_GFC_t*) 0x40520280UL)
|
||||
#define CYREG_CANFD0_CH1_SIDFC ((volatile un_CANFD_CH_SIDFC_t*) 0x40520284UL)
|
||||
#define CYREG_CANFD0_CH1_XIDFC ((volatile un_CANFD_CH_XIDFC_t*) 0x40520288UL)
|
||||
#define CYREG_CANFD0_CH1_XIDAM ((volatile un_CANFD_CH_XIDAM_t*) 0x40520290UL)
|
||||
#define CYREG_CANFD0_CH1_HPMS ((volatile un_CANFD_CH_HPMS_t*) 0x40520294UL)
|
||||
#define CYREG_CANFD0_CH1_NDAT1 ((volatile un_CANFD_CH_NDAT1_t*) 0x40520298UL)
|
||||
#define CYREG_CANFD0_CH1_NDAT2 ((volatile un_CANFD_CH_NDAT2_t*) 0x4052029CUL)
|
||||
#define CYREG_CANFD0_CH1_RXF0C ((volatile un_CANFD_CH_RXF0C_t*) 0x405202A0UL)
|
||||
#define CYREG_CANFD0_CH1_RXF0S ((volatile un_CANFD_CH_RXF0S_t*) 0x405202A4UL)
|
||||
#define CYREG_CANFD0_CH1_RXF0A ((volatile un_CANFD_CH_RXF0A_t*) 0x405202A8UL)
|
||||
#define CYREG_CANFD0_CH1_RXBC ((volatile un_CANFD_CH_RXBC_t*) 0x405202ACUL)
|
||||
#define CYREG_CANFD0_CH1_RXF1C ((volatile un_CANFD_CH_RXF1C_t*) 0x405202B0UL)
|
||||
#define CYREG_CANFD0_CH1_RXF1S ((volatile un_CANFD_CH_RXF1S_t*) 0x405202B4UL)
|
||||
#define CYREG_CANFD0_CH1_RXF1A ((volatile un_CANFD_CH_RXF1A_t*) 0x405202B8UL)
|
||||
#define CYREG_CANFD0_CH1_RXESC ((volatile un_CANFD_CH_RXESC_t*) 0x405202BCUL)
|
||||
#define CYREG_CANFD0_CH1_TXBC ((volatile un_CANFD_CH_TXBC_t*) 0x405202C0UL)
|
||||
#define CYREG_CANFD0_CH1_TXFQS ((volatile un_CANFD_CH_TXFQS_t*) 0x405202C4UL)
|
||||
#define CYREG_CANFD0_CH1_TXESC ((volatile un_CANFD_CH_TXESC_t*) 0x405202C8UL)
|
||||
#define CYREG_CANFD0_CH1_TXBRP ((volatile un_CANFD_CH_TXBRP_t*) 0x405202CCUL)
|
||||
#define CYREG_CANFD0_CH1_TXBAR ((volatile un_CANFD_CH_TXBAR_t*) 0x405202D0UL)
|
||||
#define CYREG_CANFD0_CH1_TXBCR ((volatile un_CANFD_CH_TXBCR_t*) 0x405202D4UL)
|
||||
#define CYREG_CANFD0_CH1_TXBTO ((volatile un_CANFD_CH_TXBTO_t*) 0x405202D8UL)
|
||||
#define CYREG_CANFD0_CH1_TXBCF ((volatile un_CANFD_CH_TXBCF_t*) 0x405202DCUL)
|
||||
#define CYREG_CANFD0_CH1_TXBTIE ((volatile un_CANFD_CH_TXBTIE_t*) 0x405202E0UL)
|
||||
#define CYREG_CANFD0_CH1_TXBCIE ((volatile un_CANFD_CH_TXBCIE_t*) 0x405202E4UL)
|
||||
#define CYREG_CANFD0_CH1_TXEFC ((volatile un_CANFD_CH_TXEFC_t*) 0x405202F0UL)
|
||||
#define CYREG_CANFD0_CH1_TXEFS ((volatile un_CANFD_CH_TXEFS_t*) 0x405202F4UL)
|
||||
#define CYREG_CANFD0_CH1_TXEFA ((volatile un_CANFD_CH_TXEFA_t*) 0x405202F8UL)
|
||||
#define CYREG_CANFD0_CH1_TTTMC ((volatile un_CANFD_CH_TTTMC_t*) 0x40520300UL)
|
||||
#define CYREG_CANFD0_CH1_TTRMC ((volatile un_CANFD_CH_TTRMC_t*) 0x40520304UL)
|
||||
#define CYREG_CANFD0_CH1_TTOCF ((volatile un_CANFD_CH_TTOCF_t*) 0x40520308UL)
|
||||
#define CYREG_CANFD0_CH1_TTMLM ((volatile un_CANFD_CH_TTMLM_t*) 0x4052030CUL)
|
||||
#define CYREG_CANFD0_CH1_TURCF ((volatile un_CANFD_CH_TURCF_t*) 0x40520310UL)
|
||||
#define CYREG_CANFD0_CH1_TTOCN ((volatile un_CANFD_CH_TTOCN_t*) 0x40520314UL)
|
||||
#define CYREG_CANFD0_CH1_TTGTP ((volatile un_CANFD_CH_TTGTP_t*) 0x40520318UL)
|
||||
#define CYREG_CANFD0_CH1_TTTMK ((volatile un_CANFD_CH_TTTMK_t*) 0x4052031CUL)
|
||||
#define CYREG_CANFD0_CH1_TTIR ((volatile un_CANFD_CH_TTIR_t*) 0x40520320UL)
|
||||
#define CYREG_CANFD0_CH1_TTIE ((volatile un_CANFD_CH_TTIE_t*) 0x40520324UL)
|
||||
#define CYREG_CANFD0_CH1_TTILS ((volatile un_CANFD_CH_TTILS_t*) 0x40520328UL)
|
||||
#define CYREG_CANFD0_CH1_TTOST ((volatile un_CANFD_CH_TTOST_t*) 0x4052032CUL)
|
||||
#define CYREG_CANFD0_CH1_TURNA ((volatile un_CANFD_CH_TURNA_t*) 0x40520330UL)
|
||||
#define CYREG_CANFD0_CH1_TTLGT ((volatile un_CANFD_CH_TTLGT_t*) 0x40520334UL)
|
||||
#define CYREG_CANFD0_CH1_TTCTC ((volatile un_CANFD_CH_TTCTC_t*) 0x40520338UL)
|
||||
#define CYREG_CANFD0_CH1_TTCPT ((volatile un_CANFD_CH_TTCPT_t*) 0x4052033CUL)
|
||||
#define CYREG_CANFD0_CH1_TTCSM ((volatile un_CANFD_CH_TTCSM_t*) 0x40520340UL)
|
||||
|
||||
/**
|
||||
* \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH1)
|
||||
*/
|
||||
#define CYREG_CANFD0_CH1_RXFTOP_CTL ((volatile un_CANFD_CH_RXFTOP_CTL_t*) 0x40520380UL)
|
||||
#define CYREG_CANFD0_CH1_RXFTOP0_STAT ((volatile un_CANFD_CH_RXFTOP0_STAT_t*) 0x405203A0UL)
|
||||
#define CYREG_CANFD0_CH1_RXFTOP0_DATA ((volatile un_CANFD_CH_RXFTOP0_DATA_t*) 0x405203A8UL)
|
||||
#define CYREG_CANFD0_CH1_RXFTOP1_STAT ((volatile un_CANFD_CH_RXFTOP1_STAT_t*) 0x405203B0UL)
|
||||
#define CYREG_CANFD0_CH1_RXFTOP1_DATA ((volatile un_CANFD_CH_RXFTOP1_DATA_t*) 0x405203B8UL)
|
||||
|
||||
/**
|
||||
* \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN0)
|
||||
*/
|
||||
#define CYREG_CANFD0_CH2_CREL ((volatile un_CANFD_CH_CREL_t*) 0x40520400UL)
|
||||
#define CYREG_CANFD0_CH2_ENDN ((volatile un_CANFD_CH_ENDN_t*) 0x40520404UL)
|
||||
#define CYREG_CANFD0_CH2_DBTP ((volatile un_CANFD_CH_DBTP_t*) 0x4052040CUL)
|
||||
#define CYREG_CANFD0_CH2_TEST ((volatile un_CANFD_CH_TEST_t*) 0x40520410UL)
|
||||
#define CYREG_CANFD0_CH2_RWD ((volatile un_CANFD_CH_RWD_t*) 0x40520414UL)
|
||||
#define CYREG_CANFD0_CH2_CCCR ((volatile un_CANFD_CH_CCCR_t*) 0x40520418UL)
|
||||
#define CYREG_CANFD0_CH2_NBTP ((volatile un_CANFD_CH_NBTP_t*) 0x4052041CUL)
|
||||
#define CYREG_CANFD0_CH2_TSCC ((volatile un_CANFD_CH_TSCC_t*) 0x40520420UL)
|
||||
#define CYREG_CANFD0_CH2_TSCV ((volatile un_CANFD_CH_TSCV_t*) 0x40520424UL)
|
||||
#define CYREG_CANFD0_CH2_TOCC ((volatile un_CANFD_CH_TOCC_t*) 0x40520428UL)
|
||||
#define CYREG_CANFD0_CH2_TOCV ((volatile un_CANFD_CH_TOCV_t*) 0x4052042CUL)
|
||||
#define CYREG_CANFD0_CH2_ECR ((volatile un_CANFD_CH_ECR_t*) 0x40520440UL)
|
||||
#define CYREG_CANFD0_CH2_PSR ((volatile un_CANFD_CH_PSR_t*) 0x40520444UL)
|
||||
#define CYREG_CANFD0_CH2_TDCR ((volatile un_CANFD_CH_TDCR_t*) 0x40520448UL)
|
||||
#define CYREG_CANFD0_CH2_IR ((volatile un_CANFD_CH_IR_t*) 0x40520450UL)
|
||||
#define CYREG_CANFD0_CH2_IE ((volatile un_CANFD_CH_IE_t*) 0x40520454UL)
|
||||
#define CYREG_CANFD0_CH2_ILS ((volatile un_CANFD_CH_ILS_t*) 0x40520458UL)
|
||||
#define CYREG_CANFD0_CH2_ILE ((volatile un_CANFD_CH_ILE_t*) 0x4052045CUL)
|
||||
#define CYREG_CANFD0_CH2_GFC ((volatile un_CANFD_CH_GFC_t*) 0x40520480UL)
|
||||
#define CYREG_CANFD0_CH2_SIDFC ((volatile un_CANFD_CH_SIDFC_t*) 0x40520484UL)
|
||||
#define CYREG_CANFD0_CH2_XIDFC ((volatile un_CANFD_CH_XIDFC_t*) 0x40520488UL)
|
||||
#define CYREG_CANFD0_CH2_XIDAM ((volatile un_CANFD_CH_XIDAM_t*) 0x40520490UL)
|
||||
#define CYREG_CANFD0_CH2_HPMS ((volatile un_CANFD_CH_HPMS_t*) 0x40520494UL)
|
||||
#define CYREG_CANFD0_CH2_NDAT1 ((volatile un_CANFD_CH_NDAT1_t*) 0x40520498UL)
|
||||
#define CYREG_CANFD0_CH2_NDAT2 ((volatile un_CANFD_CH_NDAT2_t*) 0x4052049CUL)
|
||||
#define CYREG_CANFD0_CH2_RXF0C ((volatile un_CANFD_CH_RXF0C_t*) 0x405204A0UL)
|
||||
#define CYREG_CANFD0_CH2_RXF0S ((volatile un_CANFD_CH_RXF0S_t*) 0x405204A4UL)
|
||||
#define CYREG_CANFD0_CH2_RXF0A ((volatile un_CANFD_CH_RXF0A_t*) 0x405204A8UL)
|
||||
#define CYREG_CANFD0_CH2_RXBC ((volatile un_CANFD_CH_RXBC_t*) 0x405204ACUL)
|
||||
#define CYREG_CANFD0_CH2_RXF1C ((volatile un_CANFD_CH_RXF1C_t*) 0x405204B0UL)
|
||||
#define CYREG_CANFD0_CH2_RXF1S ((volatile un_CANFD_CH_RXF1S_t*) 0x405204B4UL)
|
||||
#define CYREG_CANFD0_CH2_RXF1A ((volatile un_CANFD_CH_RXF1A_t*) 0x405204B8UL)
|
||||
#define CYREG_CANFD0_CH2_RXESC ((volatile un_CANFD_CH_RXESC_t*) 0x405204BCUL)
|
||||
#define CYREG_CANFD0_CH2_TXBC ((volatile un_CANFD_CH_TXBC_t*) 0x405204C0UL)
|
||||
#define CYREG_CANFD0_CH2_TXFQS ((volatile un_CANFD_CH_TXFQS_t*) 0x405204C4UL)
|
||||
#define CYREG_CANFD0_CH2_TXESC ((volatile un_CANFD_CH_TXESC_t*) 0x405204C8UL)
|
||||
#define CYREG_CANFD0_CH2_TXBRP ((volatile un_CANFD_CH_TXBRP_t*) 0x405204CCUL)
|
||||
#define CYREG_CANFD0_CH2_TXBAR ((volatile un_CANFD_CH_TXBAR_t*) 0x405204D0UL)
|
||||
#define CYREG_CANFD0_CH2_TXBCR ((volatile un_CANFD_CH_TXBCR_t*) 0x405204D4UL)
|
||||
#define CYREG_CANFD0_CH2_TXBTO ((volatile un_CANFD_CH_TXBTO_t*) 0x405204D8UL)
|
||||
#define CYREG_CANFD0_CH2_TXBCF ((volatile un_CANFD_CH_TXBCF_t*) 0x405204DCUL)
|
||||
#define CYREG_CANFD0_CH2_TXBTIE ((volatile un_CANFD_CH_TXBTIE_t*) 0x405204E0UL)
|
||||
#define CYREG_CANFD0_CH2_TXBCIE ((volatile un_CANFD_CH_TXBCIE_t*) 0x405204E4UL)
|
||||
#define CYREG_CANFD0_CH2_TXEFC ((volatile un_CANFD_CH_TXEFC_t*) 0x405204F0UL)
|
||||
#define CYREG_CANFD0_CH2_TXEFS ((volatile un_CANFD_CH_TXEFS_t*) 0x405204F4UL)
|
||||
#define CYREG_CANFD0_CH2_TXEFA ((volatile un_CANFD_CH_TXEFA_t*) 0x405204F8UL)
|
||||
#define CYREG_CANFD0_CH2_TTTMC ((volatile un_CANFD_CH_TTTMC_t*) 0x40520500UL)
|
||||
#define CYREG_CANFD0_CH2_TTRMC ((volatile un_CANFD_CH_TTRMC_t*) 0x40520504UL)
|
||||
#define CYREG_CANFD0_CH2_TTOCF ((volatile un_CANFD_CH_TTOCF_t*) 0x40520508UL)
|
||||
#define CYREG_CANFD0_CH2_TTMLM ((volatile un_CANFD_CH_TTMLM_t*) 0x4052050CUL)
|
||||
#define CYREG_CANFD0_CH2_TURCF ((volatile un_CANFD_CH_TURCF_t*) 0x40520510UL)
|
||||
#define CYREG_CANFD0_CH2_TTOCN ((volatile un_CANFD_CH_TTOCN_t*) 0x40520514UL)
|
||||
#define CYREG_CANFD0_CH2_TTGTP ((volatile un_CANFD_CH_TTGTP_t*) 0x40520518UL)
|
||||
#define CYREG_CANFD0_CH2_TTTMK ((volatile un_CANFD_CH_TTTMK_t*) 0x4052051CUL)
|
||||
#define CYREG_CANFD0_CH2_TTIR ((volatile un_CANFD_CH_TTIR_t*) 0x40520520UL)
|
||||
#define CYREG_CANFD0_CH2_TTIE ((volatile un_CANFD_CH_TTIE_t*) 0x40520524UL)
|
||||
#define CYREG_CANFD0_CH2_TTILS ((volatile un_CANFD_CH_TTILS_t*) 0x40520528UL)
|
||||
#define CYREG_CANFD0_CH2_TTOST ((volatile un_CANFD_CH_TTOST_t*) 0x4052052CUL)
|
||||
#define CYREG_CANFD0_CH2_TURNA ((volatile un_CANFD_CH_TURNA_t*) 0x40520530UL)
|
||||
#define CYREG_CANFD0_CH2_TTLGT ((volatile un_CANFD_CH_TTLGT_t*) 0x40520534UL)
|
||||
#define CYREG_CANFD0_CH2_TTCTC ((volatile un_CANFD_CH_TTCTC_t*) 0x40520538UL)
|
||||
#define CYREG_CANFD0_CH2_TTCPT ((volatile un_CANFD_CH_TTCPT_t*) 0x4052053CUL)
|
||||
#define CYREG_CANFD0_CH2_TTCSM ((volatile un_CANFD_CH_TTCSM_t*) 0x40520540UL)
|
||||
|
||||
/**
|
||||
* \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH2)
|
||||
*/
|
||||
#define CYREG_CANFD0_CH2_RXFTOP_CTL ((volatile un_CANFD_CH_RXFTOP_CTL_t*) 0x40520580UL)
|
||||
#define CYREG_CANFD0_CH2_RXFTOP0_STAT ((volatile un_CANFD_CH_RXFTOP0_STAT_t*) 0x405205A0UL)
|
||||
#define CYREG_CANFD0_CH2_RXFTOP0_DATA ((volatile un_CANFD_CH_RXFTOP0_DATA_t*) 0x405205A8UL)
|
||||
#define CYREG_CANFD0_CH2_RXFTOP1_STAT ((volatile un_CANFD_CH_RXFTOP1_STAT_t*) 0x405205B0UL)
|
||||
#define CYREG_CANFD0_CH2_RXFTOP1_DATA ((volatile un_CANFD_CH_RXFTOP1_DATA_t*) 0x405205B8UL)
|
||||
|
||||
/**
|
||||
* \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN0)
|
||||
*/
|
||||
#define CYREG_CANFD0_CH3_CREL ((volatile un_CANFD_CH_CREL_t*) 0x40520600UL)
|
||||
#define CYREG_CANFD0_CH3_ENDN ((volatile un_CANFD_CH_ENDN_t*) 0x40520604UL)
|
||||
#define CYREG_CANFD0_CH3_DBTP ((volatile un_CANFD_CH_DBTP_t*) 0x4052060CUL)
|
||||
#define CYREG_CANFD0_CH3_TEST ((volatile un_CANFD_CH_TEST_t*) 0x40520610UL)
|
||||
#define CYREG_CANFD0_CH3_RWD ((volatile un_CANFD_CH_RWD_t*) 0x40520614UL)
|
||||
#define CYREG_CANFD0_CH3_CCCR ((volatile un_CANFD_CH_CCCR_t*) 0x40520618UL)
|
||||
#define CYREG_CANFD0_CH3_NBTP ((volatile un_CANFD_CH_NBTP_t*) 0x4052061CUL)
|
||||
#define CYREG_CANFD0_CH3_TSCC ((volatile un_CANFD_CH_TSCC_t*) 0x40520620UL)
|
||||
#define CYREG_CANFD0_CH3_TSCV ((volatile un_CANFD_CH_TSCV_t*) 0x40520624UL)
|
||||
#define CYREG_CANFD0_CH3_TOCC ((volatile un_CANFD_CH_TOCC_t*) 0x40520628UL)
|
||||
#define CYREG_CANFD0_CH3_TOCV ((volatile un_CANFD_CH_TOCV_t*) 0x4052062CUL)
|
||||
#define CYREG_CANFD0_CH3_ECR ((volatile un_CANFD_CH_ECR_t*) 0x40520640UL)
|
||||
#define CYREG_CANFD0_CH3_PSR ((volatile un_CANFD_CH_PSR_t*) 0x40520644UL)
|
||||
#define CYREG_CANFD0_CH3_TDCR ((volatile un_CANFD_CH_TDCR_t*) 0x40520648UL)
|
||||
#define CYREG_CANFD0_CH3_IR ((volatile un_CANFD_CH_IR_t*) 0x40520650UL)
|
||||
#define CYREG_CANFD0_CH3_IE ((volatile un_CANFD_CH_IE_t*) 0x40520654UL)
|
||||
#define CYREG_CANFD0_CH3_ILS ((volatile un_CANFD_CH_ILS_t*) 0x40520658UL)
|
||||
#define CYREG_CANFD0_CH3_ILE ((volatile un_CANFD_CH_ILE_t*) 0x4052065CUL)
|
||||
#define CYREG_CANFD0_CH3_GFC ((volatile un_CANFD_CH_GFC_t*) 0x40520680UL)
|
||||
#define CYREG_CANFD0_CH3_SIDFC ((volatile un_CANFD_CH_SIDFC_t*) 0x40520684UL)
|
||||
#define CYREG_CANFD0_CH3_XIDFC ((volatile un_CANFD_CH_XIDFC_t*) 0x40520688UL)
|
||||
#define CYREG_CANFD0_CH3_XIDAM ((volatile un_CANFD_CH_XIDAM_t*) 0x40520690UL)
|
||||
#define CYREG_CANFD0_CH3_HPMS ((volatile un_CANFD_CH_HPMS_t*) 0x40520694UL)
|
||||
#define CYREG_CANFD0_CH3_NDAT1 ((volatile un_CANFD_CH_NDAT1_t*) 0x40520698UL)
|
||||
#define CYREG_CANFD0_CH3_NDAT2 ((volatile un_CANFD_CH_NDAT2_t*) 0x4052069CUL)
|
||||
#define CYREG_CANFD0_CH3_RXF0C ((volatile un_CANFD_CH_RXF0C_t*) 0x405206A0UL)
|
||||
#define CYREG_CANFD0_CH3_RXF0S ((volatile un_CANFD_CH_RXF0S_t*) 0x405206A4UL)
|
||||
#define CYREG_CANFD0_CH3_RXF0A ((volatile un_CANFD_CH_RXF0A_t*) 0x405206A8UL)
|
||||
#define CYREG_CANFD0_CH3_RXBC ((volatile un_CANFD_CH_RXBC_t*) 0x405206ACUL)
|
||||
#define CYREG_CANFD0_CH3_RXF1C ((volatile un_CANFD_CH_RXF1C_t*) 0x405206B0UL)
|
||||
#define CYREG_CANFD0_CH3_RXF1S ((volatile un_CANFD_CH_RXF1S_t*) 0x405206B4UL)
|
||||
#define CYREG_CANFD0_CH3_RXF1A ((volatile un_CANFD_CH_RXF1A_t*) 0x405206B8UL)
|
||||
#define CYREG_CANFD0_CH3_RXESC ((volatile un_CANFD_CH_RXESC_t*) 0x405206BCUL)
|
||||
#define CYREG_CANFD0_CH3_TXBC ((volatile un_CANFD_CH_TXBC_t*) 0x405206C0UL)
|
||||
#define CYREG_CANFD0_CH3_TXFQS ((volatile un_CANFD_CH_TXFQS_t*) 0x405206C4UL)
|
||||
#define CYREG_CANFD0_CH3_TXESC ((volatile un_CANFD_CH_TXESC_t*) 0x405206C8UL)
|
||||
#define CYREG_CANFD0_CH3_TXBRP ((volatile un_CANFD_CH_TXBRP_t*) 0x405206CCUL)
|
||||
#define CYREG_CANFD0_CH3_TXBAR ((volatile un_CANFD_CH_TXBAR_t*) 0x405206D0UL)
|
||||
#define CYREG_CANFD0_CH3_TXBCR ((volatile un_CANFD_CH_TXBCR_t*) 0x405206D4UL)
|
||||
#define CYREG_CANFD0_CH3_TXBTO ((volatile un_CANFD_CH_TXBTO_t*) 0x405206D8UL)
|
||||
#define CYREG_CANFD0_CH3_TXBCF ((volatile un_CANFD_CH_TXBCF_t*) 0x405206DCUL)
|
||||
#define CYREG_CANFD0_CH3_TXBTIE ((volatile un_CANFD_CH_TXBTIE_t*) 0x405206E0UL)
|
||||
#define CYREG_CANFD0_CH3_TXBCIE ((volatile un_CANFD_CH_TXBCIE_t*) 0x405206E4UL)
|
||||
#define CYREG_CANFD0_CH3_TXEFC ((volatile un_CANFD_CH_TXEFC_t*) 0x405206F0UL)
|
||||
#define CYREG_CANFD0_CH3_TXEFS ((volatile un_CANFD_CH_TXEFS_t*) 0x405206F4UL)
|
||||
#define CYREG_CANFD0_CH3_TXEFA ((volatile un_CANFD_CH_TXEFA_t*) 0x405206F8UL)
|
||||
#define CYREG_CANFD0_CH3_TTTMC ((volatile un_CANFD_CH_TTTMC_t*) 0x40520700UL)
|
||||
#define CYREG_CANFD0_CH3_TTRMC ((volatile un_CANFD_CH_TTRMC_t*) 0x40520704UL)
|
||||
#define CYREG_CANFD0_CH3_TTOCF ((volatile un_CANFD_CH_TTOCF_t*) 0x40520708UL)
|
||||
#define CYREG_CANFD0_CH3_TTMLM ((volatile un_CANFD_CH_TTMLM_t*) 0x4052070CUL)
|
||||
#define CYREG_CANFD0_CH3_TURCF ((volatile un_CANFD_CH_TURCF_t*) 0x40520710UL)
|
||||
#define CYREG_CANFD0_CH3_TTOCN ((volatile un_CANFD_CH_TTOCN_t*) 0x40520714UL)
|
||||
#define CYREG_CANFD0_CH3_TTGTP ((volatile un_CANFD_CH_TTGTP_t*) 0x40520718UL)
|
||||
#define CYREG_CANFD0_CH3_TTTMK ((volatile un_CANFD_CH_TTTMK_t*) 0x4052071CUL)
|
||||
#define CYREG_CANFD0_CH3_TTIR ((volatile un_CANFD_CH_TTIR_t*) 0x40520720UL)
|
||||
#define CYREG_CANFD0_CH3_TTIE ((volatile un_CANFD_CH_TTIE_t*) 0x40520724UL)
|
||||
#define CYREG_CANFD0_CH3_TTILS ((volatile un_CANFD_CH_TTILS_t*) 0x40520728UL)
|
||||
#define CYREG_CANFD0_CH3_TTOST ((volatile un_CANFD_CH_TTOST_t*) 0x4052072CUL)
|
||||
#define CYREG_CANFD0_CH3_TURNA ((volatile un_CANFD_CH_TURNA_t*) 0x40520730UL)
|
||||
#define CYREG_CANFD0_CH3_TTLGT ((volatile un_CANFD_CH_TTLGT_t*) 0x40520734UL)
|
||||
#define CYREG_CANFD0_CH3_TTCTC ((volatile un_CANFD_CH_TTCTC_t*) 0x40520738UL)
|
||||
#define CYREG_CANFD0_CH3_TTCPT ((volatile un_CANFD_CH_TTCPT_t*) 0x4052073CUL)
|
||||
#define CYREG_CANFD0_CH3_TTCSM ((volatile un_CANFD_CH_TTCSM_t*) 0x40520740UL)
|
||||
|
||||
/**
|
||||
* \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH3)
|
||||
*/
|
||||
#define CYREG_CANFD0_CH3_RXFTOP_CTL ((volatile un_CANFD_CH_RXFTOP_CTL_t*) 0x40520780UL)
|
||||
#define CYREG_CANFD0_CH3_RXFTOP0_STAT ((volatile un_CANFD_CH_RXFTOP0_STAT_t*) 0x405207A0UL)
|
||||
#define CYREG_CANFD0_CH3_RXFTOP0_DATA ((volatile un_CANFD_CH_RXFTOP0_DATA_t*) 0x405207A8UL)
|
||||
#define CYREG_CANFD0_CH3_RXFTOP1_STAT ((volatile un_CANFD_CH_RXFTOP1_STAT_t*) 0x405207B0UL)
|
||||
#define CYREG_CANFD0_CH3_RXFTOP1_DATA ((volatile un_CANFD_CH_RXFTOP1_DATA_t*) 0x405207B8UL)
|
||||
|
||||
/**
|
||||
* \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN0)
|
||||
*/
|
||||
#define CYREG_CANFD0_CH4_CREL ((volatile un_CANFD_CH_CREL_t*) 0x40520800UL)
|
||||
#define CYREG_CANFD0_CH4_ENDN ((volatile un_CANFD_CH_ENDN_t*) 0x40520804UL)
|
||||
#define CYREG_CANFD0_CH4_DBTP ((volatile un_CANFD_CH_DBTP_t*) 0x4052080CUL)
|
||||
#define CYREG_CANFD0_CH4_TEST ((volatile un_CANFD_CH_TEST_t*) 0x40520810UL)
|
||||
#define CYREG_CANFD0_CH4_RWD ((volatile un_CANFD_CH_RWD_t*) 0x40520814UL)
|
||||
#define CYREG_CANFD0_CH4_CCCR ((volatile un_CANFD_CH_CCCR_t*) 0x40520818UL)
|
||||
#define CYREG_CANFD0_CH4_NBTP ((volatile un_CANFD_CH_NBTP_t*) 0x4052081CUL)
|
||||
#define CYREG_CANFD0_CH4_TSCC ((volatile un_CANFD_CH_TSCC_t*) 0x40520820UL)
|
||||
#define CYREG_CANFD0_CH4_TSCV ((volatile un_CANFD_CH_TSCV_t*) 0x40520824UL)
|
||||
#define CYREG_CANFD0_CH4_TOCC ((volatile un_CANFD_CH_TOCC_t*) 0x40520828UL)
|
||||
#define CYREG_CANFD0_CH4_TOCV ((volatile un_CANFD_CH_TOCV_t*) 0x4052082CUL)
|
||||
#define CYREG_CANFD0_CH4_ECR ((volatile un_CANFD_CH_ECR_t*) 0x40520840UL)
|
||||
#define CYREG_CANFD0_CH4_PSR ((volatile un_CANFD_CH_PSR_t*) 0x40520844UL)
|
||||
#define CYREG_CANFD0_CH4_TDCR ((volatile un_CANFD_CH_TDCR_t*) 0x40520848UL)
|
||||
#define CYREG_CANFD0_CH4_IR ((volatile un_CANFD_CH_IR_t*) 0x40520850UL)
|
||||
#define CYREG_CANFD0_CH4_IE ((volatile un_CANFD_CH_IE_t*) 0x40520854UL)
|
||||
#define CYREG_CANFD0_CH4_ILS ((volatile un_CANFD_CH_ILS_t*) 0x40520858UL)
|
||||
#define CYREG_CANFD0_CH4_ILE ((volatile un_CANFD_CH_ILE_t*) 0x4052085CUL)
|
||||
#define CYREG_CANFD0_CH4_GFC ((volatile un_CANFD_CH_GFC_t*) 0x40520880UL)
|
||||
#define CYREG_CANFD0_CH4_SIDFC ((volatile un_CANFD_CH_SIDFC_t*) 0x40520884UL)
|
||||
#define CYREG_CANFD0_CH4_XIDFC ((volatile un_CANFD_CH_XIDFC_t*) 0x40520888UL)
|
||||
#define CYREG_CANFD0_CH4_XIDAM ((volatile un_CANFD_CH_XIDAM_t*) 0x40520890UL)
|
||||
#define CYREG_CANFD0_CH4_HPMS ((volatile un_CANFD_CH_HPMS_t*) 0x40520894UL)
|
||||
#define CYREG_CANFD0_CH4_NDAT1 ((volatile un_CANFD_CH_NDAT1_t*) 0x40520898UL)
|
||||
#define CYREG_CANFD0_CH4_NDAT2 ((volatile un_CANFD_CH_NDAT2_t*) 0x4052089CUL)
|
||||
#define CYREG_CANFD0_CH4_RXF0C ((volatile un_CANFD_CH_RXF0C_t*) 0x405208A0UL)
|
||||
#define CYREG_CANFD0_CH4_RXF0S ((volatile un_CANFD_CH_RXF0S_t*) 0x405208A4UL)
|
||||
#define CYREG_CANFD0_CH4_RXF0A ((volatile un_CANFD_CH_RXF0A_t*) 0x405208A8UL)
|
||||
#define CYREG_CANFD0_CH4_RXBC ((volatile un_CANFD_CH_RXBC_t*) 0x405208ACUL)
|
||||
#define CYREG_CANFD0_CH4_RXF1C ((volatile un_CANFD_CH_RXF1C_t*) 0x405208B0UL)
|
||||
#define CYREG_CANFD0_CH4_RXF1S ((volatile un_CANFD_CH_RXF1S_t*) 0x405208B4UL)
|
||||
#define CYREG_CANFD0_CH4_RXF1A ((volatile un_CANFD_CH_RXF1A_t*) 0x405208B8UL)
|
||||
#define CYREG_CANFD0_CH4_RXESC ((volatile un_CANFD_CH_RXESC_t*) 0x405208BCUL)
|
||||
#define CYREG_CANFD0_CH4_TXBC ((volatile un_CANFD_CH_TXBC_t*) 0x405208C0UL)
|
||||
#define CYREG_CANFD0_CH4_TXFQS ((volatile un_CANFD_CH_TXFQS_t*) 0x405208C4UL)
|
||||
#define CYREG_CANFD0_CH4_TXESC ((volatile un_CANFD_CH_TXESC_t*) 0x405208C8UL)
|
||||
#define CYREG_CANFD0_CH4_TXBRP ((volatile un_CANFD_CH_TXBRP_t*) 0x405208CCUL)
|
||||
#define CYREG_CANFD0_CH4_TXBAR ((volatile un_CANFD_CH_TXBAR_t*) 0x405208D0UL)
|
||||
#define CYREG_CANFD0_CH4_TXBCR ((volatile un_CANFD_CH_TXBCR_t*) 0x405208D4UL)
|
||||
#define CYREG_CANFD0_CH4_TXBTO ((volatile un_CANFD_CH_TXBTO_t*) 0x405208D8UL)
|
||||
#define CYREG_CANFD0_CH4_TXBCF ((volatile un_CANFD_CH_TXBCF_t*) 0x405208DCUL)
|
||||
#define CYREG_CANFD0_CH4_TXBTIE ((volatile un_CANFD_CH_TXBTIE_t*) 0x405208E0UL)
|
||||
#define CYREG_CANFD0_CH4_TXBCIE ((volatile un_CANFD_CH_TXBCIE_t*) 0x405208E4UL)
|
||||
#define CYREG_CANFD0_CH4_TXEFC ((volatile un_CANFD_CH_TXEFC_t*) 0x405208F0UL)
|
||||
#define CYREG_CANFD0_CH4_TXEFS ((volatile un_CANFD_CH_TXEFS_t*) 0x405208F4UL)
|
||||
#define CYREG_CANFD0_CH4_TXEFA ((volatile un_CANFD_CH_TXEFA_t*) 0x405208F8UL)
|
||||
#define CYREG_CANFD0_CH4_TTTMC ((volatile un_CANFD_CH_TTTMC_t*) 0x40520900UL)
|
||||
#define CYREG_CANFD0_CH4_TTRMC ((volatile un_CANFD_CH_TTRMC_t*) 0x40520904UL)
|
||||
#define CYREG_CANFD0_CH4_TTOCF ((volatile un_CANFD_CH_TTOCF_t*) 0x40520908UL)
|
||||
#define CYREG_CANFD0_CH4_TTMLM ((volatile un_CANFD_CH_TTMLM_t*) 0x4052090CUL)
|
||||
#define CYREG_CANFD0_CH4_TURCF ((volatile un_CANFD_CH_TURCF_t*) 0x40520910UL)
|
||||
#define CYREG_CANFD0_CH4_TTOCN ((volatile un_CANFD_CH_TTOCN_t*) 0x40520914UL)
|
||||
#define CYREG_CANFD0_CH4_TTGTP ((volatile un_CANFD_CH_TTGTP_t*) 0x40520918UL)
|
||||
#define CYREG_CANFD0_CH4_TTTMK ((volatile un_CANFD_CH_TTTMK_t*) 0x4052091CUL)
|
||||
#define CYREG_CANFD0_CH4_TTIR ((volatile un_CANFD_CH_TTIR_t*) 0x40520920UL)
|
||||
#define CYREG_CANFD0_CH4_TTIE ((volatile un_CANFD_CH_TTIE_t*) 0x40520924UL)
|
||||
#define CYREG_CANFD0_CH4_TTILS ((volatile un_CANFD_CH_TTILS_t*) 0x40520928UL)
|
||||
#define CYREG_CANFD0_CH4_TTOST ((volatile un_CANFD_CH_TTOST_t*) 0x4052092CUL)
|
||||
#define CYREG_CANFD0_CH4_TURNA ((volatile un_CANFD_CH_TURNA_t*) 0x40520930UL)
|
||||
#define CYREG_CANFD0_CH4_TTLGT ((volatile un_CANFD_CH_TTLGT_t*) 0x40520934UL)
|
||||
#define CYREG_CANFD0_CH4_TTCTC ((volatile un_CANFD_CH_TTCTC_t*) 0x40520938UL)
|
||||
#define CYREG_CANFD0_CH4_TTCPT ((volatile un_CANFD_CH_TTCPT_t*) 0x4052093CUL)
|
||||
#define CYREG_CANFD0_CH4_TTCSM ((volatile un_CANFD_CH_TTCSM_t*) 0x40520940UL)
|
||||
|
||||
/**
|
||||
* \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH4)
|
||||
*/
|
||||
#define CYREG_CANFD0_CH4_RXFTOP_CTL ((volatile un_CANFD_CH_RXFTOP_CTL_t*) 0x40520980UL)
|
||||
#define CYREG_CANFD0_CH4_RXFTOP0_STAT ((volatile un_CANFD_CH_RXFTOP0_STAT_t*) 0x405209A0UL)
|
||||
#define CYREG_CANFD0_CH4_RXFTOP0_DATA ((volatile un_CANFD_CH_RXFTOP0_DATA_t*) 0x405209A8UL)
|
||||
#define CYREG_CANFD0_CH4_RXFTOP1_STAT ((volatile un_CANFD_CH_RXFTOP1_STAT_t*) 0x405209B0UL)
|
||||
#define CYREG_CANFD0_CH4_RXFTOP1_DATA ((volatile un_CANFD_CH_RXFTOP1_DATA_t*) 0x405209B8UL)
|
||||
|
||||
/**
|
||||
* \brief CAN Controller (CANFD0)
|
||||
*/
|
||||
#define CYREG_CANFD0_CTL ((volatile un_CANFD_CTL_t*) 0x40521000UL)
|
||||
#define CYREG_CANFD0_STATUS ((volatile un_CANFD_STATUS_t*) 0x40521004UL)
|
||||
#define CYREG_CANFD0_INTR0_CAUSE ((volatile un_CANFD_INTR0_CAUSE_t*) 0x40521010UL)
|
||||
#define CYREG_CANFD0_INTR1_CAUSE ((volatile un_CANFD_INTR1_CAUSE_t*) 0x40521014UL)
|
||||
#define CYREG_CANFD0_TS_CTL ((volatile un_CANFD_TS_CTL_t*) 0x40521020UL)
|
||||
#define CYREG_CANFD0_TS_CNT ((volatile un_CANFD_TS_CNT_t*) 0x40521024UL)
|
||||
#define CYREG_CANFD0_ECC_CTL ((volatile un_CANFD_ECC_CTL_t*) 0x40521080UL)
|
||||
#define CYREG_CANFD0_ECC_ERR_INJ ((volatile un_CANFD_ECC_ERR_INJ_t*) 0x40521084UL)
|
||||
|
||||
/**
|
||||
* \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN0)
|
||||
*/
|
||||
#define CYREG_CANFD1_CH0_CREL ((volatile un_CANFD_CH_CREL_t*) 0x40540000UL)
|
||||
#define CYREG_CANFD1_CH0_ENDN ((volatile un_CANFD_CH_ENDN_t*) 0x40540004UL)
|
||||
#define CYREG_CANFD1_CH0_DBTP ((volatile un_CANFD_CH_DBTP_t*) 0x4054000CUL)
|
||||
#define CYREG_CANFD1_CH0_TEST ((volatile un_CANFD_CH_TEST_t*) 0x40540010UL)
|
||||
#define CYREG_CANFD1_CH0_RWD ((volatile un_CANFD_CH_RWD_t*) 0x40540014UL)
|
||||
#define CYREG_CANFD1_CH0_CCCR ((volatile un_CANFD_CH_CCCR_t*) 0x40540018UL)
|
||||
#define CYREG_CANFD1_CH0_NBTP ((volatile un_CANFD_CH_NBTP_t*) 0x4054001CUL)
|
||||
#define CYREG_CANFD1_CH0_TSCC ((volatile un_CANFD_CH_TSCC_t*) 0x40540020UL)
|
||||
#define CYREG_CANFD1_CH0_TSCV ((volatile un_CANFD_CH_TSCV_t*) 0x40540024UL)
|
||||
#define CYREG_CANFD1_CH0_TOCC ((volatile un_CANFD_CH_TOCC_t*) 0x40540028UL)
|
||||
#define CYREG_CANFD1_CH0_TOCV ((volatile un_CANFD_CH_TOCV_t*) 0x4054002CUL)
|
||||
#define CYREG_CANFD1_CH0_ECR ((volatile un_CANFD_CH_ECR_t*) 0x40540040UL)
|
||||
#define CYREG_CANFD1_CH0_PSR ((volatile un_CANFD_CH_PSR_t*) 0x40540044UL)
|
||||
#define CYREG_CANFD1_CH0_TDCR ((volatile un_CANFD_CH_TDCR_t*) 0x40540048UL)
|
||||
#define CYREG_CANFD1_CH0_IR ((volatile un_CANFD_CH_IR_t*) 0x40540050UL)
|
||||
#define CYREG_CANFD1_CH0_IE ((volatile un_CANFD_CH_IE_t*) 0x40540054UL)
|
||||
#define CYREG_CANFD1_CH0_ILS ((volatile un_CANFD_CH_ILS_t*) 0x40540058UL)
|
||||
#define CYREG_CANFD1_CH0_ILE ((volatile un_CANFD_CH_ILE_t*) 0x4054005CUL)
|
||||
#define CYREG_CANFD1_CH0_GFC ((volatile un_CANFD_CH_GFC_t*) 0x40540080UL)
|
||||
#define CYREG_CANFD1_CH0_SIDFC ((volatile un_CANFD_CH_SIDFC_t*) 0x40540084UL)
|
||||
#define CYREG_CANFD1_CH0_XIDFC ((volatile un_CANFD_CH_XIDFC_t*) 0x40540088UL)
|
||||
#define CYREG_CANFD1_CH0_XIDAM ((volatile un_CANFD_CH_XIDAM_t*) 0x40540090UL)
|
||||
#define CYREG_CANFD1_CH0_HPMS ((volatile un_CANFD_CH_HPMS_t*) 0x40540094UL)
|
||||
#define CYREG_CANFD1_CH0_NDAT1 ((volatile un_CANFD_CH_NDAT1_t*) 0x40540098UL)
|
||||
#define CYREG_CANFD1_CH0_NDAT2 ((volatile un_CANFD_CH_NDAT2_t*) 0x4054009CUL)
|
||||
#define CYREG_CANFD1_CH0_RXF0C ((volatile un_CANFD_CH_RXF0C_t*) 0x405400A0UL)
|
||||
#define CYREG_CANFD1_CH0_RXF0S ((volatile un_CANFD_CH_RXF0S_t*) 0x405400A4UL)
|
||||
#define CYREG_CANFD1_CH0_RXF0A ((volatile un_CANFD_CH_RXF0A_t*) 0x405400A8UL)
|
||||
#define CYREG_CANFD1_CH0_RXBC ((volatile un_CANFD_CH_RXBC_t*) 0x405400ACUL)
|
||||
#define CYREG_CANFD1_CH0_RXF1C ((volatile un_CANFD_CH_RXF1C_t*) 0x405400B0UL)
|
||||
#define CYREG_CANFD1_CH0_RXF1S ((volatile un_CANFD_CH_RXF1S_t*) 0x405400B4UL)
|
||||
#define CYREG_CANFD1_CH0_RXF1A ((volatile un_CANFD_CH_RXF1A_t*) 0x405400B8UL)
|
||||
#define CYREG_CANFD1_CH0_RXESC ((volatile un_CANFD_CH_RXESC_t*) 0x405400BCUL)
|
||||
#define CYREG_CANFD1_CH0_TXBC ((volatile un_CANFD_CH_TXBC_t*) 0x405400C0UL)
|
||||
#define CYREG_CANFD1_CH0_TXFQS ((volatile un_CANFD_CH_TXFQS_t*) 0x405400C4UL)
|
||||
#define CYREG_CANFD1_CH0_TXESC ((volatile un_CANFD_CH_TXESC_t*) 0x405400C8UL)
|
||||
#define CYREG_CANFD1_CH0_TXBRP ((volatile un_CANFD_CH_TXBRP_t*) 0x405400CCUL)
|
||||
#define CYREG_CANFD1_CH0_TXBAR ((volatile un_CANFD_CH_TXBAR_t*) 0x405400D0UL)
|
||||
#define CYREG_CANFD1_CH0_TXBCR ((volatile un_CANFD_CH_TXBCR_t*) 0x405400D4UL)
|
||||
#define CYREG_CANFD1_CH0_TXBTO ((volatile un_CANFD_CH_TXBTO_t*) 0x405400D8UL)
|
||||
#define CYREG_CANFD1_CH0_TXBCF ((volatile un_CANFD_CH_TXBCF_t*) 0x405400DCUL)
|
||||
#define CYREG_CANFD1_CH0_TXBTIE ((volatile un_CANFD_CH_TXBTIE_t*) 0x405400E0UL)
|
||||
#define CYREG_CANFD1_CH0_TXBCIE ((volatile un_CANFD_CH_TXBCIE_t*) 0x405400E4UL)
|
||||
#define CYREG_CANFD1_CH0_TXEFC ((volatile un_CANFD_CH_TXEFC_t*) 0x405400F0UL)
|
||||
#define CYREG_CANFD1_CH0_TXEFS ((volatile un_CANFD_CH_TXEFS_t*) 0x405400F4UL)
|
||||
#define CYREG_CANFD1_CH0_TXEFA ((volatile un_CANFD_CH_TXEFA_t*) 0x405400F8UL)
|
||||
#define CYREG_CANFD1_CH0_TTTMC ((volatile un_CANFD_CH_TTTMC_t*) 0x40540100UL)
|
||||
#define CYREG_CANFD1_CH0_TTRMC ((volatile un_CANFD_CH_TTRMC_t*) 0x40540104UL)
|
||||
#define CYREG_CANFD1_CH0_TTOCF ((volatile un_CANFD_CH_TTOCF_t*) 0x40540108UL)
|
||||
#define CYREG_CANFD1_CH0_TTMLM ((volatile un_CANFD_CH_TTMLM_t*) 0x4054010CUL)
|
||||
#define CYREG_CANFD1_CH0_TURCF ((volatile un_CANFD_CH_TURCF_t*) 0x40540110UL)
|
||||
#define CYREG_CANFD1_CH0_TTOCN ((volatile un_CANFD_CH_TTOCN_t*) 0x40540114UL)
|
||||
#define CYREG_CANFD1_CH0_TTGTP ((volatile un_CANFD_CH_TTGTP_t*) 0x40540118UL)
|
||||
#define CYREG_CANFD1_CH0_TTTMK ((volatile un_CANFD_CH_TTTMK_t*) 0x4054011CUL)
|
||||
#define CYREG_CANFD1_CH0_TTIR ((volatile un_CANFD_CH_TTIR_t*) 0x40540120UL)
|
||||
#define CYREG_CANFD1_CH0_TTIE ((volatile un_CANFD_CH_TTIE_t*) 0x40540124UL)
|
||||
#define CYREG_CANFD1_CH0_TTILS ((volatile un_CANFD_CH_TTILS_t*) 0x40540128UL)
|
||||
#define CYREG_CANFD1_CH0_TTOST ((volatile un_CANFD_CH_TTOST_t*) 0x4054012CUL)
|
||||
#define CYREG_CANFD1_CH0_TURNA ((volatile un_CANFD_CH_TURNA_t*) 0x40540130UL)
|
||||
#define CYREG_CANFD1_CH0_TTLGT ((volatile un_CANFD_CH_TTLGT_t*) 0x40540134UL)
|
||||
#define CYREG_CANFD1_CH0_TTCTC ((volatile un_CANFD_CH_TTCTC_t*) 0x40540138UL)
|
||||
#define CYREG_CANFD1_CH0_TTCPT ((volatile un_CANFD_CH_TTCPT_t*) 0x4054013CUL)
|
||||
#define CYREG_CANFD1_CH0_TTCSM ((volatile un_CANFD_CH_TTCSM_t*) 0x40540140UL)
|
||||
|
||||
/**
|
||||
* \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH0)
|
||||
*/
|
||||
#define CYREG_CANFD1_CH0_RXFTOP_CTL ((volatile un_CANFD_CH_RXFTOP_CTL_t*) 0x40540180UL)
|
||||
#define CYREG_CANFD1_CH0_RXFTOP0_STAT ((volatile un_CANFD_CH_RXFTOP0_STAT_t*) 0x405401A0UL)
|
||||
#define CYREG_CANFD1_CH0_RXFTOP0_DATA ((volatile un_CANFD_CH_RXFTOP0_DATA_t*) 0x405401A8UL)
|
||||
#define CYREG_CANFD1_CH0_RXFTOP1_STAT ((volatile un_CANFD_CH_RXFTOP1_STAT_t*) 0x405401B0UL)
|
||||
#define CYREG_CANFD1_CH0_RXFTOP1_DATA ((volatile un_CANFD_CH_RXFTOP1_DATA_t*) 0x405401B8UL)
|
||||
|
||||
/**
|
||||
* \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN0)
|
||||
*/
|
||||
#define CYREG_CANFD1_CH1_CREL ((volatile un_CANFD_CH_CREL_t*) 0x40540200UL)
|
||||
#define CYREG_CANFD1_CH1_ENDN ((volatile un_CANFD_CH_ENDN_t*) 0x40540204UL)
|
||||
#define CYREG_CANFD1_CH1_DBTP ((volatile un_CANFD_CH_DBTP_t*) 0x4054020CUL)
|
||||
#define CYREG_CANFD1_CH1_TEST ((volatile un_CANFD_CH_TEST_t*) 0x40540210UL)
|
||||
#define CYREG_CANFD1_CH1_RWD ((volatile un_CANFD_CH_RWD_t*) 0x40540214UL)
|
||||
#define CYREG_CANFD1_CH1_CCCR ((volatile un_CANFD_CH_CCCR_t*) 0x40540218UL)
|
||||
#define CYREG_CANFD1_CH1_NBTP ((volatile un_CANFD_CH_NBTP_t*) 0x4054021CUL)
|
||||
#define CYREG_CANFD1_CH1_TSCC ((volatile un_CANFD_CH_TSCC_t*) 0x40540220UL)
|
||||
#define CYREG_CANFD1_CH1_TSCV ((volatile un_CANFD_CH_TSCV_t*) 0x40540224UL)
|
||||
#define CYREG_CANFD1_CH1_TOCC ((volatile un_CANFD_CH_TOCC_t*) 0x40540228UL)
|
||||
#define CYREG_CANFD1_CH1_TOCV ((volatile un_CANFD_CH_TOCV_t*) 0x4054022CUL)
|
||||
#define CYREG_CANFD1_CH1_ECR ((volatile un_CANFD_CH_ECR_t*) 0x40540240UL)
|
||||
#define CYREG_CANFD1_CH1_PSR ((volatile un_CANFD_CH_PSR_t*) 0x40540244UL)
|
||||
#define CYREG_CANFD1_CH1_TDCR ((volatile un_CANFD_CH_TDCR_t*) 0x40540248UL)
|
||||
#define CYREG_CANFD1_CH1_IR ((volatile un_CANFD_CH_IR_t*) 0x40540250UL)
|
||||
#define CYREG_CANFD1_CH1_IE ((volatile un_CANFD_CH_IE_t*) 0x40540254UL)
|
||||
#define CYREG_CANFD1_CH1_ILS ((volatile un_CANFD_CH_ILS_t*) 0x40540258UL)
|
||||
#define CYREG_CANFD1_CH1_ILE ((volatile un_CANFD_CH_ILE_t*) 0x4054025CUL)
|
||||
#define CYREG_CANFD1_CH1_GFC ((volatile un_CANFD_CH_GFC_t*) 0x40540280UL)
|
||||
#define CYREG_CANFD1_CH1_SIDFC ((volatile un_CANFD_CH_SIDFC_t*) 0x40540284UL)
|
||||
#define CYREG_CANFD1_CH1_XIDFC ((volatile un_CANFD_CH_XIDFC_t*) 0x40540288UL)
|
||||
#define CYREG_CANFD1_CH1_XIDAM ((volatile un_CANFD_CH_XIDAM_t*) 0x40540290UL)
|
||||
#define CYREG_CANFD1_CH1_HPMS ((volatile un_CANFD_CH_HPMS_t*) 0x40540294UL)
|
||||
#define CYREG_CANFD1_CH1_NDAT1 ((volatile un_CANFD_CH_NDAT1_t*) 0x40540298UL)
|
||||
#define CYREG_CANFD1_CH1_NDAT2 ((volatile un_CANFD_CH_NDAT2_t*) 0x4054029CUL)
|
||||
#define CYREG_CANFD1_CH1_RXF0C ((volatile un_CANFD_CH_RXF0C_t*) 0x405402A0UL)
|
||||
#define CYREG_CANFD1_CH1_RXF0S ((volatile un_CANFD_CH_RXF0S_t*) 0x405402A4UL)
|
||||
#define CYREG_CANFD1_CH1_RXF0A ((volatile un_CANFD_CH_RXF0A_t*) 0x405402A8UL)
|
||||
#define CYREG_CANFD1_CH1_RXBC ((volatile un_CANFD_CH_RXBC_t*) 0x405402ACUL)
|
||||
#define CYREG_CANFD1_CH1_RXF1C ((volatile un_CANFD_CH_RXF1C_t*) 0x405402B0UL)
|
||||
#define CYREG_CANFD1_CH1_RXF1S ((volatile un_CANFD_CH_RXF1S_t*) 0x405402B4UL)
|
||||
#define CYREG_CANFD1_CH1_RXF1A ((volatile un_CANFD_CH_RXF1A_t*) 0x405402B8UL)
|
||||
#define CYREG_CANFD1_CH1_RXESC ((volatile un_CANFD_CH_RXESC_t*) 0x405402BCUL)
|
||||
#define CYREG_CANFD1_CH1_TXBC ((volatile un_CANFD_CH_TXBC_t*) 0x405402C0UL)
|
||||
#define CYREG_CANFD1_CH1_TXFQS ((volatile un_CANFD_CH_TXFQS_t*) 0x405402C4UL)
|
||||
#define CYREG_CANFD1_CH1_TXESC ((volatile un_CANFD_CH_TXESC_t*) 0x405402C8UL)
|
||||
#define CYREG_CANFD1_CH1_TXBRP ((volatile un_CANFD_CH_TXBRP_t*) 0x405402CCUL)
|
||||
#define CYREG_CANFD1_CH1_TXBAR ((volatile un_CANFD_CH_TXBAR_t*) 0x405402D0UL)
|
||||
#define CYREG_CANFD1_CH1_TXBCR ((volatile un_CANFD_CH_TXBCR_t*) 0x405402D4UL)
|
||||
#define CYREG_CANFD1_CH1_TXBTO ((volatile un_CANFD_CH_TXBTO_t*) 0x405402D8UL)
|
||||
#define CYREG_CANFD1_CH1_TXBCF ((volatile un_CANFD_CH_TXBCF_t*) 0x405402DCUL)
|
||||
#define CYREG_CANFD1_CH1_TXBTIE ((volatile un_CANFD_CH_TXBTIE_t*) 0x405402E0UL)
|
||||
#define CYREG_CANFD1_CH1_TXBCIE ((volatile un_CANFD_CH_TXBCIE_t*) 0x405402E4UL)
|
||||
#define CYREG_CANFD1_CH1_TXEFC ((volatile un_CANFD_CH_TXEFC_t*) 0x405402F0UL)
|
||||
#define CYREG_CANFD1_CH1_TXEFS ((volatile un_CANFD_CH_TXEFS_t*) 0x405402F4UL)
|
||||
#define CYREG_CANFD1_CH1_TXEFA ((volatile un_CANFD_CH_TXEFA_t*) 0x405402F8UL)
|
||||
#define CYREG_CANFD1_CH1_TTTMC ((volatile un_CANFD_CH_TTTMC_t*) 0x40540300UL)
|
||||
#define CYREG_CANFD1_CH1_TTRMC ((volatile un_CANFD_CH_TTRMC_t*) 0x40540304UL)
|
||||
#define CYREG_CANFD1_CH1_TTOCF ((volatile un_CANFD_CH_TTOCF_t*) 0x40540308UL)
|
||||
#define CYREG_CANFD1_CH1_TTMLM ((volatile un_CANFD_CH_TTMLM_t*) 0x4054030CUL)
|
||||
#define CYREG_CANFD1_CH1_TURCF ((volatile un_CANFD_CH_TURCF_t*) 0x40540310UL)
|
||||
#define CYREG_CANFD1_CH1_TTOCN ((volatile un_CANFD_CH_TTOCN_t*) 0x40540314UL)
|
||||
#define CYREG_CANFD1_CH1_TTGTP ((volatile un_CANFD_CH_TTGTP_t*) 0x40540318UL)
|
||||
#define CYREG_CANFD1_CH1_TTTMK ((volatile un_CANFD_CH_TTTMK_t*) 0x4054031CUL)
|
||||
#define CYREG_CANFD1_CH1_TTIR ((volatile un_CANFD_CH_TTIR_t*) 0x40540320UL)
|
||||
#define CYREG_CANFD1_CH1_TTIE ((volatile un_CANFD_CH_TTIE_t*) 0x40540324UL)
|
||||
#define CYREG_CANFD1_CH1_TTILS ((volatile un_CANFD_CH_TTILS_t*) 0x40540328UL)
|
||||
#define CYREG_CANFD1_CH1_TTOST ((volatile un_CANFD_CH_TTOST_t*) 0x4054032CUL)
|
||||
#define CYREG_CANFD1_CH1_TURNA ((volatile un_CANFD_CH_TURNA_t*) 0x40540330UL)
|
||||
#define CYREG_CANFD1_CH1_TTLGT ((volatile un_CANFD_CH_TTLGT_t*) 0x40540334UL)
|
||||
#define CYREG_CANFD1_CH1_TTCTC ((volatile un_CANFD_CH_TTCTC_t*) 0x40540338UL)
|
||||
#define CYREG_CANFD1_CH1_TTCPT ((volatile un_CANFD_CH_TTCPT_t*) 0x4054033CUL)
|
||||
#define CYREG_CANFD1_CH1_TTCSM ((volatile un_CANFD_CH_TTCSM_t*) 0x40540340UL)
|
||||
|
||||
/**
|
||||
* \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH1)
|
||||
*/
|
||||
#define CYREG_CANFD1_CH1_RXFTOP_CTL ((volatile un_CANFD_CH_RXFTOP_CTL_t*) 0x40540380UL)
|
||||
#define CYREG_CANFD1_CH1_RXFTOP0_STAT ((volatile un_CANFD_CH_RXFTOP0_STAT_t*) 0x405403A0UL)
|
||||
#define CYREG_CANFD1_CH1_RXFTOP0_DATA ((volatile un_CANFD_CH_RXFTOP0_DATA_t*) 0x405403A8UL)
|
||||
#define CYREG_CANFD1_CH1_RXFTOP1_STAT ((volatile un_CANFD_CH_RXFTOP1_STAT_t*) 0x405403B0UL)
|
||||
#define CYREG_CANFD1_CH1_RXFTOP1_DATA ((volatile un_CANFD_CH_RXFTOP1_DATA_t*) 0x405403B8UL)
|
||||
|
||||
/**
|
||||
* \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN0)
|
||||
*/
|
||||
#define CYREG_CANFD1_CH2_CREL ((volatile un_CANFD_CH_CREL_t*) 0x40540400UL)
|
||||
#define CYREG_CANFD1_CH2_ENDN ((volatile un_CANFD_CH_ENDN_t*) 0x40540404UL)
|
||||
#define CYREG_CANFD1_CH2_DBTP ((volatile un_CANFD_CH_DBTP_t*) 0x4054040CUL)
|
||||
#define CYREG_CANFD1_CH2_TEST ((volatile un_CANFD_CH_TEST_t*) 0x40540410UL)
|
||||
#define CYREG_CANFD1_CH2_RWD ((volatile un_CANFD_CH_RWD_t*) 0x40540414UL)
|
||||
#define CYREG_CANFD1_CH2_CCCR ((volatile un_CANFD_CH_CCCR_t*) 0x40540418UL)
|
||||
#define CYREG_CANFD1_CH2_NBTP ((volatile un_CANFD_CH_NBTP_t*) 0x4054041CUL)
|
||||
#define CYREG_CANFD1_CH2_TSCC ((volatile un_CANFD_CH_TSCC_t*) 0x40540420UL)
|
||||
#define CYREG_CANFD1_CH2_TSCV ((volatile un_CANFD_CH_TSCV_t*) 0x40540424UL)
|
||||
#define CYREG_CANFD1_CH2_TOCC ((volatile un_CANFD_CH_TOCC_t*) 0x40540428UL)
|
||||
#define CYREG_CANFD1_CH2_TOCV ((volatile un_CANFD_CH_TOCV_t*) 0x4054042CUL)
|
||||
#define CYREG_CANFD1_CH2_ECR ((volatile un_CANFD_CH_ECR_t*) 0x40540440UL)
|
||||
#define CYREG_CANFD1_CH2_PSR ((volatile un_CANFD_CH_PSR_t*) 0x40540444UL)
|
||||
#define CYREG_CANFD1_CH2_TDCR ((volatile un_CANFD_CH_TDCR_t*) 0x40540448UL)
|
||||
#define CYREG_CANFD1_CH2_IR ((volatile un_CANFD_CH_IR_t*) 0x40540450UL)
|
||||
#define CYREG_CANFD1_CH2_IE ((volatile un_CANFD_CH_IE_t*) 0x40540454UL)
|
||||
#define CYREG_CANFD1_CH2_ILS ((volatile un_CANFD_CH_ILS_t*) 0x40540458UL)
|
||||
#define CYREG_CANFD1_CH2_ILE ((volatile un_CANFD_CH_ILE_t*) 0x4054045CUL)
|
||||
#define CYREG_CANFD1_CH2_GFC ((volatile un_CANFD_CH_GFC_t*) 0x40540480UL)
|
||||
#define CYREG_CANFD1_CH2_SIDFC ((volatile un_CANFD_CH_SIDFC_t*) 0x40540484UL)
|
||||
#define CYREG_CANFD1_CH2_XIDFC ((volatile un_CANFD_CH_XIDFC_t*) 0x40540488UL)
|
||||
#define CYREG_CANFD1_CH2_XIDAM ((volatile un_CANFD_CH_XIDAM_t*) 0x40540490UL)
|
||||
#define CYREG_CANFD1_CH2_HPMS ((volatile un_CANFD_CH_HPMS_t*) 0x40540494UL)
|
||||
#define CYREG_CANFD1_CH2_NDAT1 ((volatile un_CANFD_CH_NDAT1_t*) 0x40540498UL)
|
||||
#define CYREG_CANFD1_CH2_NDAT2 ((volatile un_CANFD_CH_NDAT2_t*) 0x4054049CUL)
|
||||
#define CYREG_CANFD1_CH2_RXF0C ((volatile un_CANFD_CH_RXF0C_t*) 0x405404A0UL)
|
||||
#define CYREG_CANFD1_CH2_RXF0S ((volatile un_CANFD_CH_RXF0S_t*) 0x405404A4UL)
|
||||
#define CYREG_CANFD1_CH2_RXF0A ((volatile un_CANFD_CH_RXF0A_t*) 0x405404A8UL)
|
||||
#define CYREG_CANFD1_CH2_RXBC ((volatile un_CANFD_CH_RXBC_t*) 0x405404ACUL)
|
||||
#define CYREG_CANFD1_CH2_RXF1C ((volatile un_CANFD_CH_RXF1C_t*) 0x405404B0UL)
|
||||
#define CYREG_CANFD1_CH2_RXF1S ((volatile un_CANFD_CH_RXF1S_t*) 0x405404B4UL)
|
||||
#define CYREG_CANFD1_CH2_RXF1A ((volatile un_CANFD_CH_RXF1A_t*) 0x405404B8UL)
|
||||
#define CYREG_CANFD1_CH2_RXESC ((volatile un_CANFD_CH_RXESC_t*) 0x405404BCUL)
|
||||
#define CYREG_CANFD1_CH2_TXBC ((volatile un_CANFD_CH_TXBC_t*) 0x405404C0UL)
|
||||
#define CYREG_CANFD1_CH2_TXFQS ((volatile un_CANFD_CH_TXFQS_t*) 0x405404C4UL)
|
||||
#define CYREG_CANFD1_CH2_TXESC ((volatile un_CANFD_CH_TXESC_t*) 0x405404C8UL)
|
||||
#define CYREG_CANFD1_CH2_TXBRP ((volatile un_CANFD_CH_TXBRP_t*) 0x405404CCUL)
|
||||
#define CYREG_CANFD1_CH2_TXBAR ((volatile un_CANFD_CH_TXBAR_t*) 0x405404D0UL)
|
||||
#define CYREG_CANFD1_CH2_TXBCR ((volatile un_CANFD_CH_TXBCR_t*) 0x405404D4UL)
|
||||
#define CYREG_CANFD1_CH2_TXBTO ((volatile un_CANFD_CH_TXBTO_t*) 0x405404D8UL)
|
||||
#define CYREG_CANFD1_CH2_TXBCF ((volatile un_CANFD_CH_TXBCF_t*) 0x405404DCUL)
|
||||
#define CYREG_CANFD1_CH2_TXBTIE ((volatile un_CANFD_CH_TXBTIE_t*) 0x405404E0UL)
|
||||
#define CYREG_CANFD1_CH2_TXBCIE ((volatile un_CANFD_CH_TXBCIE_t*) 0x405404E4UL)
|
||||
#define CYREG_CANFD1_CH2_TXEFC ((volatile un_CANFD_CH_TXEFC_t*) 0x405404F0UL)
|
||||
#define CYREG_CANFD1_CH2_TXEFS ((volatile un_CANFD_CH_TXEFS_t*) 0x405404F4UL)
|
||||
#define CYREG_CANFD1_CH2_TXEFA ((volatile un_CANFD_CH_TXEFA_t*) 0x405404F8UL)
|
||||
#define CYREG_CANFD1_CH2_TTTMC ((volatile un_CANFD_CH_TTTMC_t*) 0x40540500UL)
|
||||
#define CYREG_CANFD1_CH2_TTRMC ((volatile un_CANFD_CH_TTRMC_t*) 0x40540504UL)
|
||||
#define CYREG_CANFD1_CH2_TTOCF ((volatile un_CANFD_CH_TTOCF_t*) 0x40540508UL)
|
||||
#define CYREG_CANFD1_CH2_TTMLM ((volatile un_CANFD_CH_TTMLM_t*) 0x4054050CUL)
|
||||
#define CYREG_CANFD1_CH2_TURCF ((volatile un_CANFD_CH_TURCF_t*) 0x40540510UL)
|
||||
#define CYREG_CANFD1_CH2_TTOCN ((volatile un_CANFD_CH_TTOCN_t*) 0x40540514UL)
|
||||
#define CYREG_CANFD1_CH2_TTGTP ((volatile un_CANFD_CH_TTGTP_t*) 0x40540518UL)
|
||||
#define CYREG_CANFD1_CH2_TTTMK ((volatile un_CANFD_CH_TTTMK_t*) 0x4054051CUL)
|
||||
#define CYREG_CANFD1_CH2_TTIR ((volatile un_CANFD_CH_TTIR_t*) 0x40540520UL)
|
||||
#define CYREG_CANFD1_CH2_TTIE ((volatile un_CANFD_CH_TTIE_t*) 0x40540524UL)
|
||||
#define CYREG_CANFD1_CH2_TTILS ((volatile un_CANFD_CH_TTILS_t*) 0x40540528UL)
|
||||
#define CYREG_CANFD1_CH2_TTOST ((volatile un_CANFD_CH_TTOST_t*) 0x4054052CUL)
|
||||
#define CYREG_CANFD1_CH2_TURNA ((volatile un_CANFD_CH_TURNA_t*) 0x40540530UL)
|
||||
#define CYREG_CANFD1_CH2_TTLGT ((volatile un_CANFD_CH_TTLGT_t*) 0x40540534UL)
|
||||
#define CYREG_CANFD1_CH2_TTCTC ((volatile un_CANFD_CH_TTCTC_t*) 0x40540538UL)
|
||||
#define CYREG_CANFD1_CH2_TTCPT ((volatile un_CANFD_CH_TTCPT_t*) 0x4054053CUL)
|
||||
#define CYREG_CANFD1_CH2_TTCSM ((volatile un_CANFD_CH_TTCSM_t*) 0x40540540UL)
|
||||
|
||||
/**
|
||||
* \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH2)
|
||||
*/
|
||||
#define CYREG_CANFD1_CH2_RXFTOP_CTL ((volatile un_CANFD_CH_RXFTOP_CTL_t*) 0x40540580UL)
|
||||
#define CYREG_CANFD1_CH2_RXFTOP0_STAT ((volatile un_CANFD_CH_RXFTOP0_STAT_t*) 0x405405A0UL)
|
||||
#define CYREG_CANFD1_CH2_RXFTOP0_DATA ((volatile un_CANFD_CH_RXFTOP0_DATA_t*) 0x405405A8UL)
|
||||
#define CYREG_CANFD1_CH2_RXFTOP1_STAT ((volatile un_CANFD_CH_RXFTOP1_STAT_t*) 0x405405B0UL)
|
||||
#define CYREG_CANFD1_CH2_RXFTOP1_DATA ((volatile un_CANFD_CH_RXFTOP1_DATA_t*) 0x405405B8UL)
|
||||
|
||||
/**
|
||||
* \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN0)
|
||||
*/
|
||||
#define CYREG_CANFD1_CH3_CREL ((volatile un_CANFD_CH_CREL_t*) 0x40540600UL)
|
||||
#define CYREG_CANFD1_CH3_ENDN ((volatile un_CANFD_CH_ENDN_t*) 0x40540604UL)
|
||||
#define CYREG_CANFD1_CH3_DBTP ((volatile un_CANFD_CH_DBTP_t*) 0x4054060CUL)
|
||||
#define CYREG_CANFD1_CH3_TEST ((volatile un_CANFD_CH_TEST_t*) 0x40540610UL)
|
||||
#define CYREG_CANFD1_CH3_RWD ((volatile un_CANFD_CH_RWD_t*) 0x40540614UL)
|
||||
#define CYREG_CANFD1_CH3_CCCR ((volatile un_CANFD_CH_CCCR_t*) 0x40540618UL)
|
||||
#define CYREG_CANFD1_CH3_NBTP ((volatile un_CANFD_CH_NBTP_t*) 0x4054061CUL)
|
||||
#define CYREG_CANFD1_CH3_TSCC ((volatile un_CANFD_CH_TSCC_t*) 0x40540620UL)
|
||||
#define CYREG_CANFD1_CH3_TSCV ((volatile un_CANFD_CH_TSCV_t*) 0x40540624UL)
|
||||
#define CYREG_CANFD1_CH3_TOCC ((volatile un_CANFD_CH_TOCC_t*) 0x40540628UL)
|
||||
#define CYREG_CANFD1_CH3_TOCV ((volatile un_CANFD_CH_TOCV_t*) 0x4054062CUL)
|
||||
#define CYREG_CANFD1_CH3_ECR ((volatile un_CANFD_CH_ECR_t*) 0x40540640UL)
|
||||
#define CYREG_CANFD1_CH3_PSR ((volatile un_CANFD_CH_PSR_t*) 0x40540644UL)
|
||||
#define CYREG_CANFD1_CH3_TDCR ((volatile un_CANFD_CH_TDCR_t*) 0x40540648UL)
|
||||
#define CYREG_CANFD1_CH3_IR ((volatile un_CANFD_CH_IR_t*) 0x40540650UL)
|
||||
#define CYREG_CANFD1_CH3_IE ((volatile un_CANFD_CH_IE_t*) 0x40540654UL)
|
||||
#define CYREG_CANFD1_CH3_ILS ((volatile un_CANFD_CH_ILS_t*) 0x40540658UL)
|
||||
#define CYREG_CANFD1_CH3_ILE ((volatile un_CANFD_CH_ILE_t*) 0x4054065CUL)
|
||||
#define CYREG_CANFD1_CH3_GFC ((volatile un_CANFD_CH_GFC_t*) 0x40540680UL)
|
||||
#define CYREG_CANFD1_CH3_SIDFC ((volatile un_CANFD_CH_SIDFC_t*) 0x40540684UL)
|
||||
#define CYREG_CANFD1_CH3_XIDFC ((volatile un_CANFD_CH_XIDFC_t*) 0x40540688UL)
|
||||
#define CYREG_CANFD1_CH3_XIDAM ((volatile un_CANFD_CH_XIDAM_t*) 0x40540690UL)
|
||||
#define CYREG_CANFD1_CH3_HPMS ((volatile un_CANFD_CH_HPMS_t*) 0x40540694UL)
|
||||
#define CYREG_CANFD1_CH3_NDAT1 ((volatile un_CANFD_CH_NDAT1_t*) 0x40540698UL)
|
||||
#define CYREG_CANFD1_CH3_NDAT2 ((volatile un_CANFD_CH_NDAT2_t*) 0x4054069CUL)
|
||||
#define CYREG_CANFD1_CH3_RXF0C ((volatile un_CANFD_CH_RXF0C_t*) 0x405406A0UL)
|
||||
#define CYREG_CANFD1_CH3_RXF0S ((volatile un_CANFD_CH_RXF0S_t*) 0x405406A4UL)
|
||||
#define CYREG_CANFD1_CH3_RXF0A ((volatile un_CANFD_CH_RXF0A_t*) 0x405406A8UL)
|
||||
#define CYREG_CANFD1_CH3_RXBC ((volatile un_CANFD_CH_RXBC_t*) 0x405406ACUL)
|
||||
#define CYREG_CANFD1_CH3_RXF1C ((volatile un_CANFD_CH_RXF1C_t*) 0x405406B0UL)
|
||||
#define CYREG_CANFD1_CH3_RXF1S ((volatile un_CANFD_CH_RXF1S_t*) 0x405406B4UL)
|
||||
#define CYREG_CANFD1_CH3_RXF1A ((volatile un_CANFD_CH_RXF1A_t*) 0x405406B8UL)
|
||||
#define CYREG_CANFD1_CH3_RXESC ((volatile un_CANFD_CH_RXESC_t*) 0x405406BCUL)
|
||||
#define CYREG_CANFD1_CH3_TXBC ((volatile un_CANFD_CH_TXBC_t*) 0x405406C0UL)
|
||||
#define CYREG_CANFD1_CH3_TXFQS ((volatile un_CANFD_CH_TXFQS_t*) 0x405406C4UL)
|
||||
#define CYREG_CANFD1_CH3_TXESC ((volatile un_CANFD_CH_TXESC_t*) 0x405406C8UL)
|
||||
#define CYREG_CANFD1_CH3_TXBRP ((volatile un_CANFD_CH_TXBRP_t*) 0x405406CCUL)
|
||||
#define CYREG_CANFD1_CH3_TXBAR ((volatile un_CANFD_CH_TXBAR_t*) 0x405406D0UL)
|
||||
#define CYREG_CANFD1_CH3_TXBCR ((volatile un_CANFD_CH_TXBCR_t*) 0x405406D4UL)
|
||||
#define CYREG_CANFD1_CH3_TXBTO ((volatile un_CANFD_CH_TXBTO_t*) 0x405406D8UL)
|
||||
#define CYREG_CANFD1_CH3_TXBCF ((volatile un_CANFD_CH_TXBCF_t*) 0x405406DCUL)
|
||||
#define CYREG_CANFD1_CH3_TXBTIE ((volatile un_CANFD_CH_TXBTIE_t*) 0x405406E0UL)
|
||||
#define CYREG_CANFD1_CH3_TXBCIE ((volatile un_CANFD_CH_TXBCIE_t*) 0x405406E4UL)
|
||||
#define CYREG_CANFD1_CH3_TXEFC ((volatile un_CANFD_CH_TXEFC_t*) 0x405406F0UL)
|
||||
#define CYREG_CANFD1_CH3_TXEFS ((volatile un_CANFD_CH_TXEFS_t*) 0x405406F4UL)
|
||||
#define CYREG_CANFD1_CH3_TXEFA ((volatile un_CANFD_CH_TXEFA_t*) 0x405406F8UL)
|
||||
#define CYREG_CANFD1_CH3_TTTMC ((volatile un_CANFD_CH_TTTMC_t*) 0x40540700UL)
|
||||
#define CYREG_CANFD1_CH3_TTRMC ((volatile un_CANFD_CH_TTRMC_t*) 0x40540704UL)
|
||||
#define CYREG_CANFD1_CH3_TTOCF ((volatile un_CANFD_CH_TTOCF_t*) 0x40540708UL)
|
||||
#define CYREG_CANFD1_CH3_TTMLM ((volatile un_CANFD_CH_TTMLM_t*) 0x4054070CUL)
|
||||
#define CYREG_CANFD1_CH3_TURCF ((volatile un_CANFD_CH_TURCF_t*) 0x40540710UL)
|
||||
#define CYREG_CANFD1_CH3_TTOCN ((volatile un_CANFD_CH_TTOCN_t*) 0x40540714UL)
|
||||
#define CYREG_CANFD1_CH3_TTGTP ((volatile un_CANFD_CH_TTGTP_t*) 0x40540718UL)
|
||||
#define CYREG_CANFD1_CH3_TTTMK ((volatile un_CANFD_CH_TTTMK_t*) 0x4054071CUL)
|
||||
#define CYREG_CANFD1_CH3_TTIR ((volatile un_CANFD_CH_TTIR_t*) 0x40540720UL)
|
||||
#define CYREG_CANFD1_CH3_TTIE ((volatile un_CANFD_CH_TTIE_t*) 0x40540724UL)
|
||||
#define CYREG_CANFD1_CH3_TTILS ((volatile un_CANFD_CH_TTILS_t*) 0x40540728UL)
|
||||
#define CYREG_CANFD1_CH3_TTOST ((volatile un_CANFD_CH_TTOST_t*) 0x4054072CUL)
|
||||
#define CYREG_CANFD1_CH3_TURNA ((volatile un_CANFD_CH_TURNA_t*) 0x40540730UL)
|
||||
#define CYREG_CANFD1_CH3_TTLGT ((volatile un_CANFD_CH_TTLGT_t*) 0x40540734UL)
|
||||
#define CYREG_CANFD1_CH3_TTCTC ((volatile un_CANFD_CH_TTCTC_t*) 0x40540738UL)
|
||||
#define CYREG_CANFD1_CH3_TTCPT ((volatile un_CANFD_CH_TTCPT_t*) 0x4054073CUL)
|
||||
#define CYREG_CANFD1_CH3_TTCSM ((volatile un_CANFD_CH_TTCSM_t*) 0x40540740UL)
|
||||
|
||||
/**
|
||||
* \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH3)
|
||||
*/
|
||||
#define CYREG_CANFD1_CH3_RXFTOP_CTL ((volatile un_CANFD_CH_RXFTOP_CTL_t*) 0x40540780UL)
|
||||
#define CYREG_CANFD1_CH3_RXFTOP0_STAT ((volatile un_CANFD_CH_RXFTOP0_STAT_t*) 0x405407A0UL)
|
||||
#define CYREG_CANFD1_CH3_RXFTOP0_DATA ((volatile un_CANFD_CH_RXFTOP0_DATA_t*) 0x405407A8UL)
|
||||
#define CYREG_CANFD1_CH3_RXFTOP1_STAT ((volatile un_CANFD_CH_RXFTOP1_STAT_t*) 0x405407B0UL)
|
||||
#define CYREG_CANFD1_CH3_RXFTOP1_DATA ((volatile un_CANFD_CH_RXFTOP1_DATA_t*) 0x405407B8UL)
|
||||
|
||||
/**
|
||||
* \brief TTCAN 3PIP, includes FD (CANFD_CH_M_TTCAN0)
|
||||
*/
|
||||
#define CYREG_CANFD1_CH4_CREL ((volatile un_CANFD_CH_CREL_t*) 0x40540800UL)
|
||||
#define CYREG_CANFD1_CH4_ENDN ((volatile un_CANFD_CH_ENDN_t*) 0x40540804UL)
|
||||
#define CYREG_CANFD1_CH4_DBTP ((volatile un_CANFD_CH_DBTP_t*) 0x4054080CUL)
|
||||
#define CYREG_CANFD1_CH4_TEST ((volatile un_CANFD_CH_TEST_t*) 0x40540810UL)
|
||||
#define CYREG_CANFD1_CH4_RWD ((volatile un_CANFD_CH_RWD_t*) 0x40540814UL)
|
||||
#define CYREG_CANFD1_CH4_CCCR ((volatile un_CANFD_CH_CCCR_t*) 0x40540818UL)
|
||||
#define CYREG_CANFD1_CH4_NBTP ((volatile un_CANFD_CH_NBTP_t*) 0x4054081CUL)
|
||||
#define CYREG_CANFD1_CH4_TSCC ((volatile un_CANFD_CH_TSCC_t*) 0x40540820UL)
|
||||
#define CYREG_CANFD1_CH4_TSCV ((volatile un_CANFD_CH_TSCV_t*) 0x40540824UL)
|
||||
#define CYREG_CANFD1_CH4_TOCC ((volatile un_CANFD_CH_TOCC_t*) 0x40540828UL)
|
||||
#define CYREG_CANFD1_CH4_TOCV ((volatile un_CANFD_CH_TOCV_t*) 0x4054082CUL)
|
||||
#define CYREG_CANFD1_CH4_ECR ((volatile un_CANFD_CH_ECR_t*) 0x40540840UL)
|
||||
#define CYREG_CANFD1_CH4_PSR ((volatile un_CANFD_CH_PSR_t*) 0x40540844UL)
|
||||
#define CYREG_CANFD1_CH4_TDCR ((volatile un_CANFD_CH_TDCR_t*) 0x40540848UL)
|
||||
#define CYREG_CANFD1_CH4_IR ((volatile un_CANFD_CH_IR_t*) 0x40540850UL)
|
||||
#define CYREG_CANFD1_CH4_IE ((volatile un_CANFD_CH_IE_t*) 0x40540854UL)
|
||||
#define CYREG_CANFD1_CH4_ILS ((volatile un_CANFD_CH_ILS_t*) 0x40540858UL)
|
||||
#define CYREG_CANFD1_CH4_ILE ((volatile un_CANFD_CH_ILE_t*) 0x4054085CUL)
|
||||
#define CYREG_CANFD1_CH4_GFC ((volatile un_CANFD_CH_GFC_t*) 0x40540880UL)
|
||||
#define CYREG_CANFD1_CH4_SIDFC ((volatile un_CANFD_CH_SIDFC_t*) 0x40540884UL)
|
||||
#define CYREG_CANFD1_CH4_XIDFC ((volatile un_CANFD_CH_XIDFC_t*) 0x40540888UL)
|
||||
#define CYREG_CANFD1_CH4_XIDAM ((volatile un_CANFD_CH_XIDAM_t*) 0x40540890UL)
|
||||
#define CYREG_CANFD1_CH4_HPMS ((volatile un_CANFD_CH_HPMS_t*) 0x40540894UL)
|
||||
#define CYREG_CANFD1_CH4_NDAT1 ((volatile un_CANFD_CH_NDAT1_t*) 0x40540898UL)
|
||||
#define CYREG_CANFD1_CH4_NDAT2 ((volatile un_CANFD_CH_NDAT2_t*) 0x4054089CUL)
|
||||
#define CYREG_CANFD1_CH4_RXF0C ((volatile un_CANFD_CH_RXF0C_t*) 0x405408A0UL)
|
||||
#define CYREG_CANFD1_CH4_RXF0S ((volatile un_CANFD_CH_RXF0S_t*) 0x405408A4UL)
|
||||
#define CYREG_CANFD1_CH4_RXF0A ((volatile un_CANFD_CH_RXF0A_t*) 0x405408A8UL)
|
||||
#define CYREG_CANFD1_CH4_RXBC ((volatile un_CANFD_CH_RXBC_t*) 0x405408ACUL)
|
||||
#define CYREG_CANFD1_CH4_RXF1C ((volatile un_CANFD_CH_RXF1C_t*) 0x405408B0UL)
|
||||
#define CYREG_CANFD1_CH4_RXF1S ((volatile un_CANFD_CH_RXF1S_t*) 0x405408B4UL)
|
||||
#define CYREG_CANFD1_CH4_RXF1A ((volatile un_CANFD_CH_RXF1A_t*) 0x405408B8UL)
|
||||
#define CYREG_CANFD1_CH4_RXESC ((volatile un_CANFD_CH_RXESC_t*) 0x405408BCUL)
|
||||
#define CYREG_CANFD1_CH4_TXBC ((volatile un_CANFD_CH_TXBC_t*) 0x405408C0UL)
|
||||
#define CYREG_CANFD1_CH4_TXFQS ((volatile un_CANFD_CH_TXFQS_t*) 0x405408C4UL)
|
||||
#define CYREG_CANFD1_CH4_TXESC ((volatile un_CANFD_CH_TXESC_t*) 0x405408C8UL)
|
||||
#define CYREG_CANFD1_CH4_TXBRP ((volatile un_CANFD_CH_TXBRP_t*) 0x405408CCUL)
|
||||
#define CYREG_CANFD1_CH4_TXBAR ((volatile un_CANFD_CH_TXBAR_t*) 0x405408D0UL)
|
||||
#define CYREG_CANFD1_CH4_TXBCR ((volatile un_CANFD_CH_TXBCR_t*) 0x405408D4UL)
|
||||
#define CYREG_CANFD1_CH4_TXBTO ((volatile un_CANFD_CH_TXBTO_t*) 0x405408D8UL)
|
||||
#define CYREG_CANFD1_CH4_TXBCF ((volatile un_CANFD_CH_TXBCF_t*) 0x405408DCUL)
|
||||
#define CYREG_CANFD1_CH4_TXBTIE ((volatile un_CANFD_CH_TXBTIE_t*) 0x405408E0UL)
|
||||
#define CYREG_CANFD1_CH4_TXBCIE ((volatile un_CANFD_CH_TXBCIE_t*) 0x405408E4UL)
|
||||
#define CYREG_CANFD1_CH4_TXEFC ((volatile un_CANFD_CH_TXEFC_t*) 0x405408F0UL)
|
||||
#define CYREG_CANFD1_CH4_TXEFS ((volatile un_CANFD_CH_TXEFS_t*) 0x405408F4UL)
|
||||
#define CYREG_CANFD1_CH4_TXEFA ((volatile un_CANFD_CH_TXEFA_t*) 0x405408F8UL)
|
||||
#define CYREG_CANFD1_CH4_TTTMC ((volatile un_CANFD_CH_TTTMC_t*) 0x40540900UL)
|
||||
#define CYREG_CANFD1_CH4_TTRMC ((volatile un_CANFD_CH_TTRMC_t*) 0x40540904UL)
|
||||
#define CYREG_CANFD1_CH4_TTOCF ((volatile un_CANFD_CH_TTOCF_t*) 0x40540908UL)
|
||||
#define CYREG_CANFD1_CH4_TTMLM ((volatile un_CANFD_CH_TTMLM_t*) 0x4054090CUL)
|
||||
#define CYREG_CANFD1_CH4_TURCF ((volatile un_CANFD_CH_TURCF_t*) 0x40540910UL)
|
||||
#define CYREG_CANFD1_CH4_TTOCN ((volatile un_CANFD_CH_TTOCN_t*) 0x40540914UL)
|
||||
#define CYREG_CANFD1_CH4_TTGTP ((volatile un_CANFD_CH_TTGTP_t*) 0x40540918UL)
|
||||
#define CYREG_CANFD1_CH4_TTTMK ((volatile un_CANFD_CH_TTTMK_t*) 0x4054091CUL)
|
||||
#define CYREG_CANFD1_CH4_TTIR ((volatile un_CANFD_CH_TTIR_t*) 0x40540920UL)
|
||||
#define CYREG_CANFD1_CH4_TTIE ((volatile un_CANFD_CH_TTIE_t*) 0x40540924UL)
|
||||
#define CYREG_CANFD1_CH4_TTILS ((volatile un_CANFD_CH_TTILS_t*) 0x40540928UL)
|
||||
#define CYREG_CANFD1_CH4_TTOST ((volatile un_CANFD_CH_TTOST_t*) 0x4054092CUL)
|
||||
#define CYREG_CANFD1_CH4_TURNA ((volatile un_CANFD_CH_TURNA_t*) 0x40540930UL)
|
||||
#define CYREG_CANFD1_CH4_TTLGT ((volatile un_CANFD_CH_TTLGT_t*) 0x40540934UL)
|
||||
#define CYREG_CANFD1_CH4_TTCTC ((volatile un_CANFD_CH_TTCTC_t*) 0x40540938UL)
|
||||
#define CYREG_CANFD1_CH4_TTCPT ((volatile un_CANFD_CH_TTCPT_t*) 0x4054093CUL)
|
||||
#define CYREG_CANFD1_CH4_TTCSM ((volatile un_CANFD_CH_TTCSM_t*) 0x40540940UL)
|
||||
|
||||
/**
|
||||
* \brief FIFO wrapper around M_TTCAN 3PIP, to enable DMA (CANFD_CH4)
|
||||
*/
|
||||
#define CYREG_CANFD1_CH4_RXFTOP_CTL ((volatile un_CANFD_CH_RXFTOP_CTL_t*) 0x40540980UL)
|
||||
#define CYREG_CANFD1_CH4_RXFTOP0_STAT ((volatile un_CANFD_CH_RXFTOP0_STAT_t*) 0x405409A0UL)
|
||||
#define CYREG_CANFD1_CH4_RXFTOP0_DATA ((volatile un_CANFD_CH_RXFTOP0_DATA_t*) 0x405409A8UL)
|
||||
#define CYREG_CANFD1_CH4_RXFTOP1_STAT ((volatile un_CANFD_CH_RXFTOP1_STAT_t*) 0x405409B0UL)
|
||||
#define CYREG_CANFD1_CH4_RXFTOP1_DATA ((volatile un_CANFD_CH_RXFTOP1_DATA_t*) 0x405409B8UL)
|
||||
|
||||
/**
|
||||
* \brief CAN Controller (CANFD1)
|
||||
*/
|
||||
#define CYREG_CANFD1_CTL ((volatile un_CANFD_CTL_t*) 0x40541000UL)
|
||||
#define CYREG_CANFD1_STATUS ((volatile un_CANFD_STATUS_t*) 0x40541004UL)
|
||||
#define CYREG_CANFD1_INTR0_CAUSE ((volatile un_CANFD_INTR0_CAUSE_t*) 0x40541010UL)
|
||||
#define CYREG_CANFD1_INTR1_CAUSE ((volatile un_CANFD_INTR1_CAUSE_t*) 0x40541014UL)
|
||||
#define CYREG_CANFD1_ECC_CTL ((volatile un_CANFD_ECC_CTL_t*) 0x40541080UL)
|
||||
#define CYREG_CANFD1_ECC_ERR_INJ ((volatile un_CANFD_ECC_ERR_INJ_t*) 0x40541084UL)
|
||||
|
||||
#endif /* _CYREG_CANFD_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,217 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_dmac.h
|
||||
*
|
||||
* \brief
|
||||
* DMAC register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_DMAC_H_
|
||||
#define _CYREG_DMAC_H_
|
||||
|
||||
#include "cyip_dmac.h"
|
||||
|
||||
/**
|
||||
* \brief DMA controller channel (DMAC_CH0)
|
||||
*/
|
||||
#define CYREG_DMAC_CH0_CTL ((volatile un_DMAC_CH_CTL_t*) 0x402A1000UL)
|
||||
#define CYREG_DMAC_CH0_IDX ((volatile un_DMAC_CH_IDX_t*) 0x402A1010UL)
|
||||
#define CYREG_DMAC_CH0_SRC ((volatile un_DMAC_CH_SRC_t*) 0x402A1014UL)
|
||||
#define CYREG_DMAC_CH0_DST ((volatile un_DMAC_CH_DST_t*) 0x402A1018UL)
|
||||
#define CYREG_DMAC_CH0_CURR ((volatile un_DMAC_CH_CURR_t*) 0x402A1020UL)
|
||||
#define CYREG_DMAC_CH0_TR_CMD ((volatile un_DMAC_CH_TR_CMD_t*) 0x402A1028UL)
|
||||
#define CYREG_DMAC_CH0_DESCR_STATUS ((volatile un_DMAC_CH_DESCR_STATUS_t*) 0x402A1040UL)
|
||||
#define CYREG_DMAC_CH0_DESCR_CTL ((volatile un_DMAC_CH_DESCR_CTL_t*) 0x402A1060UL)
|
||||
#define CYREG_DMAC_CH0_DESCR_SRC ((volatile un_DMAC_CH_DESCR_SRC_t*) 0x402A1064UL)
|
||||
#define CYREG_DMAC_CH0_DESCR_DST ((volatile un_DMAC_CH_DESCR_DST_t*) 0x402A1068UL)
|
||||
#define CYREG_DMAC_CH0_DESCR_X_SIZE ((volatile un_DMAC_CH_DESCR_X_SIZE_t*) 0x402A106CUL)
|
||||
#define CYREG_DMAC_CH0_DESCR_X_INCR ((volatile un_DMAC_CH_DESCR_X_INCR_t*) 0x402A1070UL)
|
||||
#define CYREG_DMAC_CH0_DESCR_Y_SIZE ((volatile un_DMAC_CH_DESCR_Y_SIZE_t*) 0x402A1074UL)
|
||||
#define CYREG_DMAC_CH0_DESCR_Y_INCR ((volatile un_DMAC_CH_DESCR_Y_INCR_t*) 0x402A1078UL)
|
||||
#define CYREG_DMAC_CH0_DESCR_NEXT ((volatile un_DMAC_CH_DESCR_NEXT_t*) 0x402A107CUL)
|
||||
#define CYREG_DMAC_CH0_INTR ((volatile un_DMAC_CH_INTR_t*) 0x402A1080UL)
|
||||
#define CYREG_DMAC_CH0_INTR_SET ((volatile un_DMAC_CH_INTR_SET_t*) 0x402A1084UL)
|
||||
#define CYREG_DMAC_CH0_INTR_MASK ((volatile un_DMAC_CH_INTR_MASK_t*) 0x402A1088UL)
|
||||
#define CYREG_DMAC_CH0_INTR_MASKED ((volatile un_DMAC_CH_INTR_MASKED_t*) 0x402A108CUL)
|
||||
|
||||
/**
|
||||
* \brief DMA controller channel (DMAC_CH1)
|
||||
*/
|
||||
#define CYREG_DMAC_CH1_CTL ((volatile un_DMAC_CH_CTL_t*) 0x402A1100UL)
|
||||
#define CYREG_DMAC_CH1_IDX ((volatile un_DMAC_CH_IDX_t*) 0x402A1110UL)
|
||||
#define CYREG_DMAC_CH1_SRC ((volatile un_DMAC_CH_SRC_t*) 0x402A1114UL)
|
||||
#define CYREG_DMAC_CH1_DST ((volatile un_DMAC_CH_DST_t*) 0x402A1118UL)
|
||||
#define CYREG_DMAC_CH1_CURR ((volatile un_DMAC_CH_CURR_t*) 0x402A1120UL)
|
||||
#define CYREG_DMAC_CH1_TR_CMD ((volatile un_DMAC_CH_TR_CMD_t*) 0x402A1128UL)
|
||||
#define CYREG_DMAC_CH1_DESCR_STATUS ((volatile un_DMAC_CH_DESCR_STATUS_t*) 0x402A1140UL)
|
||||
#define CYREG_DMAC_CH1_DESCR_CTL ((volatile un_DMAC_CH_DESCR_CTL_t*) 0x402A1160UL)
|
||||
#define CYREG_DMAC_CH1_DESCR_SRC ((volatile un_DMAC_CH_DESCR_SRC_t*) 0x402A1164UL)
|
||||
#define CYREG_DMAC_CH1_DESCR_DST ((volatile un_DMAC_CH_DESCR_DST_t*) 0x402A1168UL)
|
||||
#define CYREG_DMAC_CH1_DESCR_X_SIZE ((volatile un_DMAC_CH_DESCR_X_SIZE_t*) 0x402A116CUL)
|
||||
#define CYREG_DMAC_CH1_DESCR_X_INCR ((volatile un_DMAC_CH_DESCR_X_INCR_t*) 0x402A1170UL)
|
||||
#define CYREG_DMAC_CH1_DESCR_Y_SIZE ((volatile un_DMAC_CH_DESCR_Y_SIZE_t*) 0x402A1174UL)
|
||||
#define CYREG_DMAC_CH1_DESCR_Y_INCR ((volatile un_DMAC_CH_DESCR_Y_INCR_t*) 0x402A1178UL)
|
||||
#define CYREG_DMAC_CH1_DESCR_NEXT ((volatile un_DMAC_CH_DESCR_NEXT_t*) 0x402A117CUL)
|
||||
#define CYREG_DMAC_CH1_INTR ((volatile un_DMAC_CH_INTR_t*) 0x402A1180UL)
|
||||
#define CYREG_DMAC_CH1_INTR_SET ((volatile un_DMAC_CH_INTR_SET_t*) 0x402A1184UL)
|
||||
#define CYREG_DMAC_CH1_INTR_MASK ((volatile un_DMAC_CH_INTR_MASK_t*) 0x402A1188UL)
|
||||
#define CYREG_DMAC_CH1_INTR_MASKED ((volatile un_DMAC_CH_INTR_MASKED_t*) 0x402A118CUL)
|
||||
|
||||
/**
|
||||
* \brief DMA controller channel (DMAC_CH2)
|
||||
*/
|
||||
#define CYREG_DMAC_CH2_CTL ((volatile un_DMAC_CH_CTL_t*) 0x402A1200UL)
|
||||
#define CYREG_DMAC_CH2_IDX ((volatile un_DMAC_CH_IDX_t*) 0x402A1210UL)
|
||||
#define CYREG_DMAC_CH2_SRC ((volatile un_DMAC_CH_SRC_t*) 0x402A1214UL)
|
||||
#define CYREG_DMAC_CH2_DST ((volatile un_DMAC_CH_DST_t*) 0x402A1218UL)
|
||||
#define CYREG_DMAC_CH2_CURR ((volatile un_DMAC_CH_CURR_t*) 0x402A1220UL)
|
||||
#define CYREG_DMAC_CH2_TR_CMD ((volatile un_DMAC_CH_TR_CMD_t*) 0x402A1228UL)
|
||||
#define CYREG_DMAC_CH2_DESCR_STATUS ((volatile un_DMAC_CH_DESCR_STATUS_t*) 0x402A1240UL)
|
||||
#define CYREG_DMAC_CH2_DESCR_CTL ((volatile un_DMAC_CH_DESCR_CTL_t*) 0x402A1260UL)
|
||||
#define CYREG_DMAC_CH2_DESCR_SRC ((volatile un_DMAC_CH_DESCR_SRC_t*) 0x402A1264UL)
|
||||
#define CYREG_DMAC_CH2_DESCR_DST ((volatile un_DMAC_CH_DESCR_DST_t*) 0x402A1268UL)
|
||||
#define CYREG_DMAC_CH2_DESCR_X_SIZE ((volatile un_DMAC_CH_DESCR_X_SIZE_t*) 0x402A126CUL)
|
||||
#define CYREG_DMAC_CH2_DESCR_X_INCR ((volatile un_DMAC_CH_DESCR_X_INCR_t*) 0x402A1270UL)
|
||||
#define CYREG_DMAC_CH2_DESCR_Y_SIZE ((volatile un_DMAC_CH_DESCR_Y_SIZE_t*) 0x402A1274UL)
|
||||
#define CYREG_DMAC_CH2_DESCR_Y_INCR ((volatile un_DMAC_CH_DESCR_Y_INCR_t*) 0x402A1278UL)
|
||||
#define CYREG_DMAC_CH2_DESCR_NEXT ((volatile un_DMAC_CH_DESCR_NEXT_t*) 0x402A127CUL)
|
||||
#define CYREG_DMAC_CH2_INTR ((volatile un_DMAC_CH_INTR_t*) 0x402A1280UL)
|
||||
#define CYREG_DMAC_CH2_INTR_SET ((volatile un_DMAC_CH_INTR_SET_t*) 0x402A1284UL)
|
||||
#define CYREG_DMAC_CH2_INTR_MASK ((volatile un_DMAC_CH_INTR_MASK_t*) 0x402A1288UL)
|
||||
#define CYREG_DMAC_CH2_INTR_MASKED ((volatile un_DMAC_CH_INTR_MASKED_t*) 0x402A128CUL)
|
||||
|
||||
/**
|
||||
* \brief DMA controller channel (DMAC_CH3)
|
||||
*/
|
||||
#define CYREG_DMAC_CH3_CTL ((volatile un_DMAC_CH_CTL_t*) 0x402A1300UL)
|
||||
#define CYREG_DMAC_CH3_IDX ((volatile un_DMAC_CH_IDX_t*) 0x402A1310UL)
|
||||
#define CYREG_DMAC_CH3_SRC ((volatile un_DMAC_CH_SRC_t*) 0x402A1314UL)
|
||||
#define CYREG_DMAC_CH3_DST ((volatile un_DMAC_CH_DST_t*) 0x402A1318UL)
|
||||
#define CYREG_DMAC_CH3_CURR ((volatile un_DMAC_CH_CURR_t*) 0x402A1320UL)
|
||||
#define CYREG_DMAC_CH3_TR_CMD ((volatile un_DMAC_CH_TR_CMD_t*) 0x402A1328UL)
|
||||
#define CYREG_DMAC_CH3_DESCR_STATUS ((volatile un_DMAC_CH_DESCR_STATUS_t*) 0x402A1340UL)
|
||||
#define CYREG_DMAC_CH3_DESCR_CTL ((volatile un_DMAC_CH_DESCR_CTL_t*) 0x402A1360UL)
|
||||
#define CYREG_DMAC_CH3_DESCR_SRC ((volatile un_DMAC_CH_DESCR_SRC_t*) 0x402A1364UL)
|
||||
#define CYREG_DMAC_CH3_DESCR_DST ((volatile un_DMAC_CH_DESCR_DST_t*) 0x402A1368UL)
|
||||
#define CYREG_DMAC_CH3_DESCR_X_SIZE ((volatile un_DMAC_CH_DESCR_X_SIZE_t*) 0x402A136CUL)
|
||||
#define CYREG_DMAC_CH3_DESCR_X_INCR ((volatile un_DMAC_CH_DESCR_X_INCR_t*) 0x402A1370UL)
|
||||
#define CYREG_DMAC_CH3_DESCR_Y_SIZE ((volatile un_DMAC_CH_DESCR_Y_SIZE_t*) 0x402A1374UL)
|
||||
#define CYREG_DMAC_CH3_DESCR_Y_INCR ((volatile un_DMAC_CH_DESCR_Y_INCR_t*) 0x402A1378UL)
|
||||
#define CYREG_DMAC_CH3_DESCR_NEXT ((volatile un_DMAC_CH_DESCR_NEXT_t*) 0x402A137CUL)
|
||||
#define CYREG_DMAC_CH3_INTR ((volatile un_DMAC_CH_INTR_t*) 0x402A1380UL)
|
||||
#define CYREG_DMAC_CH3_INTR_SET ((volatile un_DMAC_CH_INTR_SET_t*) 0x402A1384UL)
|
||||
#define CYREG_DMAC_CH3_INTR_MASK ((volatile un_DMAC_CH_INTR_MASK_t*) 0x402A1388UL)
|
||||
#define CYREG_DMAC_CH3_INTR_MASKED ((volatile un_DMAC_CH_INTR_MASKED_t*) 0x402A138CUL)
|
||||
|
||||
/**
|
||||
* \brief DMA controller channel (DMAC_CH4)
|
||||
*/
|
||||
#define CYREG_DMAC_CH4_CTL ((volatile un_DMAC_CH_CTL_t*) 0x402A1400UL)
|
||||
#define CYREG_DMAC_CH4_IDX ((volatile un_DMAC_CH_IDX_t*) 0x402A1410UL)
|
||||
#define CYREG_DMAC_CH4_SRC ((volatile un_DMAC_CH_SRC_t*) 0x402A1414UL)
|
||||
#define CYREG_DMAC_CH4_DST ((volatile un_DMAC_CH_DST_t*) 0x402A1418UL)
|
||||
#define CYREG_DMAC_CH4_CURR ((volatile un_DMAC_CH_CURR_t*) 0x402A1420UL)
|
||||
#define CYREG_DMAC_CH4_TR_CMD ((volatile un_DMAC_CH_TR_CMD_t*) 0x402A1428UL)
|
||||
#define CYREG_DMAC_CH4_DESCR_STATUS ((volatile un_DMAC_CH_DESCR_STATUS_t*) 0x402A1440UL)
|
||||
#define CYREG_DMAC_CH4_DESCR_CTL ((volatile un_DMAC_CH_DESCR_CTL_t*) 0x402A1460UL)
|
||||
#define CYREG_DMAC_CH4_DESCR_SRC ((volatile un_DMAC_CH_DESCR_SRC_t*) 0x402A1464UL)
|
||||
#define CYREG_DMAC_CH4_DESCR_DST ((volatile un_DMAC_CH_DESCR_DST_t*) 0x402A1468UL)
|
||||
#define CYREG_DMAC_CH4_DESCR_X_SIZE ((volatile un_DMAC_CH_DESCR_X_SIZE_t*) 0x402A146CUL)
|
||||
#define CYREG_DMAC_CH4_DESCR_X_INCR ((volatile un_DMAC_CH_DESCR_X_INCR_t*) 0x402A1470UL)
|
||||
#define CYREG_DMAC_CH4_DESCR_Y_SIZE ((volatile un_DMAC_CH_DESCR_Y_SIZE_t*) 0x402A1474UL)
|
||||
#define CYREG_DMAC_CH4_DESCR_Y_INCR ((volatile un_DMAC_CH_DESCR_Y_INCR_t*) 0x402A1478UL)
|
||||
#define CYREG_DMAC_CH4_DESCR_NEXT ((volatile un_DMAC_CH_DESCR_NEXT_t*) 0x402A147CUL)
|
||||
#define CYREG_DMAC_CH4_INTR ((volatile un_DMAC_CH_INTR_t*) 0x402A1480UL)
|
||||
#define CYREG_DMAC_CH4_INTR_SET ((volatile un_DMAC_CH_INTR_SET_t*) 0x402A1484UL)
|
||||
#define CYREG_DMAC_CH4_INTR_MASK ((volatile un_DMAC_CH_INTR_MASK_t*) 0x402A1488UL)
|
||||
#define CYREG_DMAC_CH4_INTR_MASKED ((volatile un_DMAC_CH_INTR_MASKED_t*) 0x402A148CUL)
|
||||
|
||||
/**
|
||||
* \brief DMA controller channel (DMAC_CH5)
|
||||
*/
|
||||
#define CYREG_DMAC_CH5_CTL ((volatile un_DMAC_CH_CTL_t*) 0x402A1500UL)
|
||||
#define CYREG_DMAC_CH5_IDX ((volatile un_DMAC_CH_IDX_t*) 0x402A1510UL)
|
||||
#define CYREG_DMAC_CH5_SRC ((volatile un_DMAC_CH_SRC_t*) 0x402A1514UL)
|
||||
#define CYREG_DMAC_CH5_DST ((volatile un_DMAC_CH_DST_t*) 0x402A1518UL)
|
||||
#define CYREG_DMAC_CH5_CURR ((volatile un_DMAC_CH_CURR_t*) 0x402A1520UL)
|
||||
#define CYREG_DMAC_CH5_TR_CMD ((volatile un_DMAC_CH_TR_CMD_t*) 0x402A1528UL)
|
||||
#define CYREG_DMAC_CH5_DESCR_STATUS ((volatile un_DMAC_CH_DESCR_STATUS_t*) 0x402A1540UL)
|
||||
#define CYREG_DMAC_CH5_DESCR_CTL ((volatile un_DMAC_CH_DESCR_CTL_t*) 0x402A1560UL)
|
||||
#define CYREG_DMAC_CH5_DESCR_SRC ((volatile un_DMAC_CH_DESCR_SRC_t*) 0x402A1564UL)
|
||||
#define CYREG_DMAC_CH5_DESCR_DST ((volatile un_DMAC_CH_DESCR_DST_t*) 0x402A1568UL)
|
||||
#define CYREG_DMAC_CH5_DESCR_X_SIZE ((volatile un_DMAC_CH_DESCR_X_SIZE_t*) 0x402A156CUL)
|
||||
#define CYREG_DMAC_CH5_DESCR_X_INCR ((volatile un_DMAC_CH_DESCR_X_INCR_t*) 0x402A1570UL)
|
||||
#define CYREG_DMAC_CH5_DESCR_Y_SIZE ((volatile un_DMAC_CH_DESCR_Y_SIZE_t*) 0x402A1574UL)
|
||||
#define CYREG_DMAC_CH5_DESCR_Y_INCR ((volatile un_DMAC_CH_DESCR_Y_INCR_t*) 0x402A1578UL)
|
||||
#define CYREG_DMAC_CH5_DESCR_NEXT ((volatile un_DMAC_CH_DESCR_NEXT_t*) 0x402A157CUL)
|
||||
#define CYREG_DMAC_CH5_INTR ((volatile un_DMAC_CH_INTR_t*) 0x402A1580UL)
|
||||
#define CYREG_DMAC_CH5_INTR_SET ((volatile un_DMAC_CH_INTR_SET_t*) 0x402A1584UL)
|
||||
#define CYREG_DMAC_CH5_INTR_MASK ((volatile un_DMAC_CH_INTR_MASK_t*) 0x402A1588UL)
|
||||
#define CYREG_DMAC_CH5_INTR_MASKED ((volatile un_DMAC_CH_INTR_MASKED_t*) 0x402A158CUL)
|
||||
|
||||
/**
|
||||
* \brief DMA controller channel (DMAC_CH6)
|
||||
*/
|
||||
#define CYREG_DMAC_CH6_CTL ((volatile un_DMAC_CH_CTL_t*) 0x402A1600UL)
|
||||
#define CYREG_DMAC_CH6_IDX ((volatile un_DMAC_CH_IDX_t*) 0x402A1610UL)
|
||||
#define CYREG_DMAC_CH6_SRC ((volatile un_DMAC_CH_SRC_t*) 0x402A1614UL)
|
||||
#define CYREG_DMAC_CH6_DST ((volatile un_DMAC_CH_DST_t*) 0x402A1618UL)
|
||||
#define CYREG_DMAC_CH6_CURR ((volatile un_DMAC_CH_CURR_t*) 0x402A1620UL)
|
||||
#define CYREG_DMAC_CH6_TR_CMD ((volatile un_DMAC_CH_TR_CMD_t*) 0x402A1628UL)
|
||||
#define CYREG_DMAC_CH6_DESCR_STATUS ((volatile un_DMAC_CH_DESCR_STATUS_t*) 0x402A1640UL)
|
||||
#define CYREG_DMAC_CH6_DESCR_CTL ((volatile un_DMAC_CH_DESCR_CTL_t*) 0x402A1660UL)
|
||||
#define CYREG_DMAC_CH6_DESCR_SRC ((volatile un_DMAC_CH_DESCR_SRC_t*) 0x402A1664UL)
|
||||
#define CYREG_DMAC_CH6_DESCR_DST ((volatile un_DMAC_CH_DESCR_DST_t*) 0x402A1668UL)
|
||||
#define CYREG_DMAC_CH6_DESCR_X_SIZE ((volatile un_DMAC_CH_DESCR_X_SIZE_t*) 0x402A166CUL)
|
||||
#define CYREG_DMAC_CH6_DESCR_X_INCR ((volatile un_DMAC_CH_DESCR_X_INCR_t*) 0x402A1670UL)
|
||||
#define CYREG_DMAC_CH6_DESCR_Y_SIZE ((volatile un_DMAC_CH_DESCR_Y_SIZE_t*) 0x402A1674UL)
|
||||
#define CYREG_DMAC_CH6_DESCR_Y_INCR ((volatile un_DMAC_CH_DESCR_Y_INCR_t*) 0x402A1678UL)
|
||||
#define CYREG_DMAC_CH6_DESCR_NEXT ((volatile un_DMAC_CH_DESCR_NEXT_t*) 0x402A167CUL)
|
||||
#define CYREG_DMAC_CH6_INTR ((volatile un_DMAC_CH_INTR_t*) 0x402A1680UL)
|
||||
#define CYREG_DMAC_CH6_INTR_SET ((volatile un_DMAC_CH_INTR_SET_t*) 0x402A1684UL)
|
||||
#define CYREG_DMAC_CH6_INTR_MASK ((volatile un_DMAC_CH_INTR_MASK_t*) 0x402A1688UL)
|
||||
#define CYREG_DMAC_CH6_INTR_MASKED ((volatile un_DMAC_CH_INTR_MASKED_t*) 0x402A168CUL)
|
||||
|
||||
/**
|
||||
* \brief DMA controller channel (DMAC_CH7)
|
||||
*/
|
||||
#define CYREG_DMAC_CH7_CTL ((volatile un_DMAC_CH_CTL_t*) 0x402A1700UL)
|
||||
#define CYREG_DMAC_CH7_IDX ((volatile un_DMAC_CH_IDX_t*) 0x402A1710UL)
|
||||
#define CYREG_DMAC_CH7_SRC ((volatile un_DMAC_CH_SRC_t*) 0x402A1714UL)
|
||||
#define CYREG_DMAC_CH7_DST ((volatile un_DMAC_CH_DST_t*) 0x402A1718UL)
|
||||
#define CYREG_DMAC_CH7_CURR ((volatile un_DMAC_CH_CURR_t*) 0x402A1720UL)
|
||||
#define CYREG_DMAC_CH7_TR_CMD ((volatile un_DMAC_CH_TR_CMD_t*) 0x402A1728UL)
|
||||
#define CYREG_DMAC_CH7_DESCR_STATUS ((volatile un_DMAC_CH_DESCR_STATUS_t*) 0x402A1740UL)
|
||||
#define CYREG_DMAC_CH7_DESCR_CTL ((volatile un_DMAC_CH_DESCR_CTL_t*) 0x402A1760UL)
|
||||
#define CYREG_DMAC_CH7_DESCR_SRC ((volatile un_DMAC_CH_DESCR_SRC_t*) 0x402A1764UL)
|
||||
#define CYREG_DMAC_CH7_DESCR_DST ((volatile un_DMAC_CH_DESCR_DST_t*) 0x402A1768UL)
|
||||
#define CYREG_DMAC_CH7_DESCR_X_SIZE ((volatile un_DMAC_CH_DESCR_X_SIZE_t*) 0x402A176CUL)
|
||||
#define CYREG_DMAC_CH7_DESCR_X_INCR ((volatile un_DMAC_CH_DESCR_X_INCR_t*) 0x402A1770UL)
|
||||
#define CYREG_DMAC_CH7_DESCR_Y_SIZE ((volatile un_DMAC_CH_DESCR_Y_SIZE_t*) 0x402A1774UL)
|
||||
#define CYREG_DMAC_CH7_DESCR_Y_INCR ((volatile un_DMAC_CH_DESCR_Y_INCR_t*) 0x402A1778UL)
|
||||
#define CYREG_DMAC_CH7_DESCR_NEXT ((volatile un_DMAC_CH_DESCR_NEXT_t*) 0x402A177CUL)
|
||||
#define CYREG_DMAC_CH7_INTR ((volatile un_DMAC_CH_INTR_t*) 0x402A1780UL)
|
||||
#define CYREG_DMAC_CH7_INTR_SET ((volatile un_DMAC_CH_INTR_SET_t*) 0x402A1784UL)
|
||||
#define CYREG_DMAC_CH7_INTR_MASK ((volatile un_DMAC_CH_INTR_MASK_t*) 0x402A1788UL)
|
||||
#define CYREG_DMAC_CH7_INTR_MASKED ((volatile un_DMAC_CH_INTR_MASKED_t*) 0x402A178CUL)
|
||||
|
||||
/**
|
||||
* \brief DMAC (DMAC0)
|
||||
*/
|
||||
#define CYREG_DMAC_CTL ((volatile un_DMAC_CTL_t*) 0x402A0000UL)
|
||||
#define CYREG_DMAC_ACTIVE ((volatile un_DMAC_ACTIVE_t*) 0x402A0008UL)
|
||||
|
||||
#endif /* _CYREG_DMAC_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,47 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_efuse.h
|
||||
*
|
||||
* \brief
|
||||
* EFUSE register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_EFUSE_H_
|
||||
#define _CYREG_EFUSE_H_
|
||||
|
||||
#include "cyip_efuse_v2.h"
|
||||
|
||||
/**
|
||||
* \brief EFUSE MXS40 registers (EFUSE)
|
||||
*/
|
||||
#define CYREG_EFUSE_CTL ((volatile un_EFUSE_CTL_t*) 0x402C0000UL)
|
||||
#define CYREG_EFUSE_TEST ((volatile un_EFUSE_TEST_t*) 0x402C0004UL)
|
||||
#define CYREG_EFUSE_CMD ((volatile un_EFUSE_CMD_t*) 0x402C0010UL)
|
||||
#define CYREG_EFUSE_SEQ_DEFAULT ((volatile un_EFUSE_SEQ_DEFAULT_t*) 0x402C0020UL)
|
||||
#define CYREG_EFUSE_SEQ_READ_CTL_0 ((volatile un_EFUSE_SEQ_READ_CTL_0_t*) 0x402C0040UL)
|
||||
#define CYREG_EFUSE_SEQ_READ_CTL_1 ((volatile un_EFUSE_SEQ_READ_CTL_1_t*) 0x402C0044UL)
|
||||
#define CYREG_EFUSE_SEQ_READ_CTL_2 ((volatile un_EFUSE_SEQ_READ_CTL_2_t*) 0x402C0048UL)
|
||||
#define CYREG_EFUSE_SEQ_READ_CTL_3 ((volatile un_EFUSE_SEQ_READ_CTL_3_t*) 0x402C004CUL)
|
||||
#define CYREG_EFUSE_SEQ_READ_CTL_4 ((volatile un_EFUSE_SEQ_READ_CTL_4_t*) 0x402C0050UL)
|
||||
#define CYREG_EFUSE_SEQ_READ_CTL_5 ((volatile un_EFUSE_SEQ_READ_CTL_5_t*) 0x402C0054UL)
|
||||
#define CYREG_EFUSE_SEQ_PROGRAM_CTL_0 ((volatile un_EFUSE_SEQ_PROGRAM_CTL_0_t*) 0x402C0060UL)
|
||||
#define CYREG_EFUSE_SEQ_PROGRAM_CTL_1 ((volatile un_EFUSE_SEQ_PROGRAM_CTL_1_t*) 0x402C0064UL)
|
||||
#define CYREG_EFUSE_SEQ_PROGRAM_CTL_2 ((volatile un_EFUSE_SEQ_PROGRAM_CTL_2_t*) 0x402C0068UL)
|
||||
#define CYREG_EFUSE_SEQ_PROGRAM_CTL_3 ((volatile un_EFUSE_SEQ_PROGRAM_CTL_3_t*) 0x402C006CUL)
|
||||
#define CYREG_EFUSE_SEQ_PROGRAM_CTL_4 ((volatile un_EFUSE_SEQ_PROGRAM_CTL_4_t*) 0x402C0070UL)
|
||||
#define CYREG_EFUSE_SEQ_PROGRAM_CTL_5 ((volatile un_EFUSE_SEQ_PROGRAM_CTL_5_t*) 0x402C0074UL)
|
||||
|
||||
#endif /* _CYREG_EFUSE_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,43 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_efuse_data.h
|
||||
*
|
||||
* \brief
|
||||
* EFUSE_DATA register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_EFUSE_DATA_H_
|
||||
#define _CYREG_EFUSE_DATA_H_
|
||||
|
||||
#include "cyip_efuse_data_v2.h"
|
||||
|
||||
/**
|
||||
* \brief eFUSE memory (EFUSE_DATA)
|
||||
*/
|
||||
#define CYREG_EFUSE_DATA_SECURE_HASH_WORD0 ((volatile un_EFUSE_DATA_SECURE_HASH_WORD0_t*) 0x402C082CUL)
|
||||
#define CYREG_EFUSE_DATA_SECURE_HASH_WORD1 ((volatile un_EFUSE_DATA_SECURE_HASH_WORD1_t*) 0x402C0830UL)
|
||||
#define CYREG_EFUSE_DATA_SECURE_HASH_WORD2 ((volatile un_EFUSE_DATA_SECURE_HASH_WORD2_t*) 0x402C0834UL)
|
||||
#define CYREG_EFUSE_DATA_SECURE_HASH_WORD3 ((volatile un_EFUSE_DATA_SECURE_HASH_WORD3_t*) 0x402C0838UL)
|
||||
#define CYREG_EFUSE_DATA_SECURE_ACCESS_RESTRICT ((volatile un_EFUSE_DATA_SECURE_ACCESS_RESTRICT_t*) 0x402C083CUL)
|
||||
#define CYREG_EFUSE_DATA_SECURE_DEAD_ACCESS_RESTRICT_ZEROS ((volatile un_EFUSE_DATA_SECURE_DEAD_ACCESS_RESTRICT_ZEROS_t*) 0x402C0840UL)
|
||||
#define CYREG_EFUSE_DATA_CUSTOMER_DATA0 ((volatile un_EFUSE_DATA_CUSTOMER_DATA_t*) 0x402C0868UL)
|
||||
#define CYREG_EFUSE_DATA_CUSTOMER_DATA1 ((volatile un_EFUSE_DATA_CUSTOMER_DATA_t*) 0x402C086CUL)
|
||||
#define CYREG_EFUSE_DATA_CUSTOMER_DATA2 ((volatile un_EFUSE_DATA_CUSTOMER_DATA_t*) 0x402C0870UL)
|
||||
#define CYREG_EFUSE_DATA_CUSTOMER_DATA3 ((volatile un_EFUSE_DATA_CUSTOMER_DATA_t*) 0x402C0874UL)
|
||||
#define CYREG_EFUSE_DATA_CUSTOMER_DATA4 ((volatile un_EFUSE_DATA_CUSTOMER_DATA_t*) 0x402C0878UL)
|
||||
#define CYREG_EFUSE_DATA_CUSTOMER_DATA5 ((volatile un_EFUSE_DATA_CUSTOMER_DATA_t*) 0x402C087CUL)
|
||||
|
||||
#endif /* _CYREG_EFUSE_DATA_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,659 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_eth.h
|
||||
*
|
||||
* \brief
|
||||
* ETH register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_ETH_H_
|
||||
#define _CYREG_ETH_H_
|
||||
|
||||
#include "cyip_eth.h"
|
||||
|
||||
/**
|
||||
* \brief Ethernet Interface (ETH0)
|
||||
*/
|
||||
#define CYREG_ETH0_CTL ((volatile un_ETH_CTL_t*) 0x40480000UL)
|
||||
#define CYREG_ETH0_STATUS ((volatile un_ETH_STATUS_t*) 0x40480004UL)
|
||||
#define CYREG_ETH0_NETWORK_CONTROL ((volatile un_ETH_NETWORK_CONTROL_t*) 0x40481000UL)
|
||||
#define CYREG_ETH0_NETWORK_CONFIG ((volatile un_ETH_NETWORK_CONFIG_t*) 0x40481004UL)
|
||||
#define CYREG_ETH0_NETWORK_STATUS ((volatile un_ETH_NETWORK_STATUS_t*) 0x40481008UL)
|
||||
#define CYREG_ETH0_USER_IO_REGISTER ((volatile un_ETH_USER_IO_REGISTER_t*) 0x4048100CUL)
|
||||
#define CYREG_ETH0_DMA_CONFIG ((volatile un_ETH_DMA_CONFIG_t*) 0x40481010UL)
|
||||
#define CYREG_ETH0_TRANSMIT_STATUS ((volatile un_ETH_TRANSMIT_STATUS_t*) 0x40481014UL)
|
||||
#define CYREG_ETH0_RECEIVE_Q_PTR ((volatile un_ETH_RECEIVE_Q_PTR_t*) 0x40481018UL)
|
||||
#define CYREG_ETH0_TRANSMIT_Q_PTR ((volatile un_ETH_TRANSMIT_Q_PTR_t*) 0x4048101CUL)
|
||||
#define CYREG_ETH0_RECEIVE_STATUS ((volatile un_ETH_RECEIVE_STATUS_t*) 0x40481020UL)
|
||||
#define CYREG_ETH0_INT_STATUS ((volatile un_ETH_INT_STATUS_t*) 0x40481024UL)
|
||||
#define CYREG_ETH0_INT_ENABLE ((volatile un_ETH_INT_ENABLE_t*) 0x40481028UL)
|
||||
#define CYREG_ETH0_INT_DISABLE ((volatile un_ETH_INT_DISABLE_t*) 0x4048102CUL)
|
||||
#define CYREG_ETH0_INT_MASK ((volatile un_ETH_INT_MASK_t*) 0x40481030UL)
|
||||
#define CYREG_ETH0_PHY_MANAGEMENT ((volatile un_ETH_PHY_MANAGEMENT_t*) 0x40481034UL)
|
||||
#define CYREG_ETH0_PAUSE_TIME ((volatile un_ETH_PAUSE_TIME_t*) 0x40481038UL)
|
||||
#define CYREG_ETH0_TX_PAUSE_QUANTUM ((volatile un_ETH_TX_PAUSE_QUANTUM_t*) 0x4048103CUL)
|
||||
#define CYREG_ETH0_PBUF_TXCUTTHRU ((volatile un_ETH_PBUF_TXCUTTHRU_t*) 0x40481040UL)
|
||||
#define CYREG_ETH0_PBUF_RXCUTTHRU ((volatile un_ETH_PBUF_RXCUTTHRU_t*) 0x40481044UL)
|
||||
#define CYREG_ETH0_JUMBO_MAX_LENGTH ((volatile un_ETH_JUMBO_MAX_LENGTH_t*) 0x40481048UL)
|
||||
#define CYREG_ETH0_EXTERNAL_FIFO_INTERFACE ((volatile un_ETH_EXTERNAL_FIFO_INTERFACE_t*) 0x4048104CUL)
|
||||
#define CYREG_ETH0_AXI_MAX_PIPELINE ((volatile un_ETH_AXI_MAX_PIPELINE_t*) 0x40481054UL)
|
||||
#define CYREG_ETH0_RSC_CONTROL ((volatile un_ETH_RSC_CONTROL_t*) 0x40481058UL)
|
||||
#define CYREG_ETH0_INT_MODERATION ((volatile un_ETH_INT_MODERATION_t*) 0x4048105CUL)
|
||||
#define CYREG_ETH0_SYS_WAKE_TIME ((volatile un_ETH_SYS_WAKE_TIME_t*) 0x40481060UL)
|
||||
#define CYREG_ETH0_HASH_BOTTOM ((volatile un_ETH_HASH_BOTTOM_t*) 0x40481080UL)
|
||||
#define CYREG_ETH0_HASH_TOP ((volatile un_ETH_HASH_TOP_t*) 0x40481084UL)
|
||||
#define CYREG_ETH0_SPEC_ADD1_BOTTOM ((volatile un_ETH_SPEC_ADD1_BOTTOM_t*) 0x40481088UL)
|
||||
#define CYREG_ETH0_SPEC_ADD1_TOP ((volatile un_ETH_SPEC_ADD1_TOP_t*) 0x4048108CUL)
|
||||
#define CYREG_ETH0_SPEC_ADD2_BOTTOM ((volatile un_ETH_SPEC_ADD2_BOTTOM_t*) 0x40481090UL)
|
||||
#define CYREG_ETH0_SPEC_ADD2_TOP ((volatile un_ETH_SPEC_ADD2_TOP_t*) 0x40481094UL)
|
||||
#define CYREG_ETH0_SPEC_ADD3_BOTTOM ((volatile un_ETH_SPEC_ADD3_BOTTOM_t*) 0x40481098UL)
|
||||
#define CYREG_ETH0_SPEC_ADD3_TOP ((volatile un_ETH_SPEC_ADD3_TOP_t*) 0x4048109CUL)
|
||||
#define CYREG_ETH0_SPEC_ADD4_BOTTOM ((volatile un_ETH_SPEC_ADD4_BOTTOM_t*) 0x404810A0UL)
|
||||
#define CYREG_ETH0_SPEC_ADD4_TOP ((volatile un_ETH_SPEC_ADD4_TOP_t*) 0x404810A4UL)
|
||||
#define CYREG_ETH0_SPEC_TYPE1 ((volatile un_ETH_SPEC_TYPE1_t*) 0x404810A8UL)
|
||||
#define CYREG_ETH0_SPEC_TYPE2 ((volatile un_ETH_SPEC_TYPE2_t*) 0x404810ACUL)
|
||||
#define CYREG_ETH0_SPEC_TYPE3 ((volatile un_ETH_SPEC_TYPE3_t*) 0x404810B0UL)
|
||||
#define CYREG_ETH0_SPEC_TYPE4 ((volatile un_ETH_SPEC_TYPE4_t*) 0x404810B4UL)
|
||||
#define CYREG_ETH0_WOL_REGISTER ((volatile un_ETH_WOL_REGISTER_t*) 0x404810B8UL)
|
||||
#define CYREG_ETH0_STRETCH_RATIO ((volatile un_ETH_STRETCH_RATIO_t*) 0x404810BCUL)
|
||||
#define CYREG_ETH0_STACKED_VLAN ((volatile un_ETH_STACKED_VLAN_t*) 0x404810C0UL)
|
||||
#define CYREG_ETH0_TX_PFC_PAUSE ((volatile un_ETH_TX_PFC_PAUSE_t*) 0x404810C4UL)
|
||||
#define CYREG_ETH0_MASK_ADD1_BOTTOM ((volatile un_ETH_MASK_ADD1_BOTTOM_t*) 0x404810C8UL)
|
||||
#define CYREG_ETH0_MASK_ADD1_TOP ((volatile un_ETH_MASK_ADD1_TOP_t*) 0x404810CCUL)
|
||||
#define CYREG_ETH0_DMA_ADDR_OR_MASK ((volatile un_ETH_DMA_ADDR_OR_MASK_t*) 0x404810D0UL)
|
||||
#define CYREG_ETH0_RX_PTP_UNICAST ((volatile un_ETH_RX_PTP_UNICAST_t*) 0x404810D4UL)
|
||||
#define CYREG_ETH0_TX_PTP_UNICAST ((volatile un_ETH_TX_PTP_UNICAST_t*) 0x404810D8UL)
|
||||
#define CYREG_ETH0_TSU_NSEC_CMP ((volatile un_ETH_TSU_NSEC_CMP_t*) 0x404810DCUL)
|
||||
#define CYREG_ETH0_TSU_SEC_CMP ((volatile un_ETH_TSU_SEC_CMP_t*) 0x404810E0UL)
|
||||
#define CYREG_ETH0_TSU_MSB_SEC_CMP ((volatile un_ETH_TSU_MSB_SEC_CMP_t*) 0x404810E4UL)
|
||||
#define CYREG_ETH0_TSU_PTP_TX_MSB_SEC ((volatile un_ETH_TSU_PTP_TX_MSB_SEC_t*) 0x404810E8UL)
|
||||
#define CYREG_ETH0_TSU_PTP_RX_MSB_SEC ((volatile un_ETH_TSU_PTP_RX_MSB_SEC_t*) 0x404810ECUL)
|
||||
#define CYREG_ETH0_TSU_PEER_TX_MSB_SEC ((volatile un_ETH_TSU_PEER_TX_MSB_SEC_t*) 0x404810F0UL)
|
||||
#define CYREG_ETH0_TSU_PEER_RX_MSB_SEC ((volatile un_ETH_TSU_PEER_RX_MSB_SEC_t*) 0x404810F4UL)
|
||||
#define CYREG_ETH0_DPRAM_FILL_DBG ((volatile un_ETH_DPRAM_FILL_DBG_t*) 0x404810F8UL)
|
||||
#define CYREG_ETH0_REVISION_REG ((volatile un_ETH_REVISION_REG_t*) 0x404810FCUL)
|
||||
#define CYREG_ETH0_OCTETS_TXED_BOTTOM ((volatile un_ETH_OCTETS_TXED_BOTTOM_t*) 0x40481100UL)
|
||||
#define CYREG_ETH0_OCTETS_TXED_TOP ((volatile un_ETH_OCTETS_TXED_TOP_t*) 0x40481104UL)
|
||||
#define CYREG_ETH0_FRAMES_TXED_OK ((volatile un_ETH_FRAMES_TXED_OK_t*) 0x40481108UL)
|
||||
#define CYREG_ETH0_BROADCAST_TXED ((volatile un_ETH_BROADCAST_TXED_t*) 0x4048110CUL)
|
||||
#define CYREG_ETH0_MULTICAST_TXED ((volatile un_ETH_MULTICAST_TXED_t*) 0x40481110UL)
|
||||
#define CYREG_ETH0_PAUSE_FRAMES_TXED ((volatile un_ETH_PAUSE_FRAMES_TXED_t*) 0x40481114UL)
|
||||
#define CYREG_ETH0_FRAMES_TXED_64 ((volatile un_ETH_FRAMES_TXED_64_t*) 0x40481118UL)
|
||||
#define CYREG_ETH0_FRAMES_TXED_65 ((volatile un_ETH_FRAMES_TXED_65_t*) 0x4048111CUL)
|
||||
#define CYREG_ETH0_FRAMES_TXED_128 ((volatile un_ETH_FRAMES_TXED_128_t*) 0x40481120UL)
|
||||
#define CYREG_ETH0_FRAMES_TXED_256 ((volatile un_ETH_FRAMES_TXED_256_t*) 0x40481124UL)
|
||||
#define CYREG_ETH0_FRAMES_TXED_512 ((volatile un_ETH_FRAMES_TXED_512_t*) 0x40481128UL)
|
||||
#define CYREG_ETH0_FRAMES_TXED_1024 ((volatile un_ETH_FRAMES_TXED_1024_t*) 0x4048112CUL)
|
||||
#define CYREG_ETH0_FRAMES_TXED_1519 ((volatile un_ETH_FRAMES_TXED_1519_t*) 0x40481130UL)
|
||||
#define CYREG_ETH0_TX_UNDERRUNS ((volatile un_ETH_TX_UNDERRUNS_t*) 0x40481134UL)
|
||||
#define CYREG_ETH0_SINGLE_COLLISIONS ((volatile un_ETH_SINGLE_COLLISIONS_t*) 0x40481138UL)
|
||||
#define CYREG_ETH0_MULTIPLE_COLLISIONS ((volatile un_ETH_MULTIPLE_COLLISIONS_t*) 0x4048113CUL)
|
||||
#define CYREG_ETH0_EXCESSIVE_COLLISIONS ((volatile un_ETH_EXCESSIVE_COLLISIONS_t*) 0x40481140UL)
|
||||
#define CYREG_ETH0_LATE_COLLISIONS ((volatile un_ETH_LATE_COLLISIONS_t*) 0x40481144UL)
|
||||
#define CYREG_ETH0_DEFERRED_FRAMES ((volatile un_ETH_DEFERRED_FRAMES_t*) 0x40481148UL)
|
||||
#define CYREG_ETH0_CRS_ERRORS ((volatile un_ETH_CRS_ERRORS_t*) 0x4048114CUL)
|
||||
#define CYREG_ETH0_OCTETS_RXED_BOTTOM ((volatile un_ETH_OCTETS_RXED_BOTTOM_t*) 0x40481150UL)
|
||||
#define CYREG_ETH0_OCTETS_RXED_TOP ((volatile un_ETH_OCTETS_RXED_TOP_t*) 0x40481154UL)
|
||||
#define CYREG_ETH0_FRAMES_RXED_OK ((volatile un_ETH_FRAMES_RXED_OK_t*) 0x40481158UL)
|
||||
#define CYREG_ETH0_BROADCAST_RXED ((volatile un_ETH_BROADCAST_RXED_t*) 0x4048115CUL)
|
||||
#define CYREG_ETH0_MULTICAST_RXED ((volatile un_ETH_MULTICAST_RXED_t*) 0x40481160UL)
|
||||
#define CYREG_ETH0_PAUSE_FRAMES_RXED ((volatile un_ETH_PAUSE_FRAMES_RXED_t*) 0x40481164UL)
|
||||
#define CYREG_ETH0_FRAMES_RXED_64 ((volatile un_ETH_FRAMES_RXED_64_t*) 0x40481168UL)
|
||||
#define CYREG_ETH0_FRAMES_RXED_65 ((volatile un_ETH_FRAMES_RXED_65_t*) 0x4048116CUL)
|
||||
#define CYREG_ETH0_FRAMES_RXED_128 ((volatile un_ETH_FRAMES_RXED_128_t*) 0x40481170UL)
|
||||
#define CYREG_ETH0_FRAMES_RXED_256 ((volatile un_ETH_FRAMES_RXED_256_t*) 0x40481174UL)
|
||||
#define CYREG_ETH0_FRAMES_RXED_512 ((volatile un_ETH_FRAMES_RXED_512_t*) 0x40481178UL)
|
||||
#define CYREG_ETH0_FRAMES_RXED_1024 ((volatile un_ETH_FRAMES_RXED_1024_t*) 0x4048117CUL)
|
||||
#define CYREG_ETH0_FRAMES_RXED_1519 ((volatile un_ETH_FRAMES_RXED_1519_t*) 0x40481180UL)
|
||||
#define CYREG_ETH0_UNDERSIZE_FRAMES ((volatile un_ETH_UNDERSIZE_FRAMES_t*) 0x40481184UL)
|
||||
#define CYREG_ETH0_EXCESSIVE_RX_LENGTH ((volatile un_ETH_EXCESSIVE_RX_LENGTH_t*) 0x40481188UL)
|
||||
#define CYREG_ETH0_RX_JABBERS ((volatile un_ETH_RX_JABBERS_t*) 0x4048118CUL)
|
||||
#define CYREG_ETH0_FCS_ERRORS ((volatile un_ETH_FCS_ERRORS_t*) 0x40481190UL)
|
||||
#define CYREG_ETH0_RX_LENGTH_ERRORS ((volatile un_ETH_RX_LENGTH_ERRORS_t*) 0x40481194UL)
|
||||
#define CYREG_ETH0_RX_SYMBOL_ERRORS ((volatile un_ETH_RX_SYMBOL_ERRORS_t*) 0x40481198UL)
|
||||
#define CYREG_ETH0_ALIGNMENT_ERRORS ((volatile un_ETH_ALIGNMENT_ERRORS_t*) 0x4048119CUL)
|
||||
#define CYREG_ETH0_RX_RESOURCE_ERRORS ((volatile un_ETH_RX_RESOURCE_ERRORS_t*) 0x404811A0UL)
|
||||
#define CYREG_ETH0_RX_OVERRUNS ((volatile un_ETH_RX_OVERRUNS_t*) 0x404811A4UL)
|
||||
#define CYREG_ETH0_RX_IP_CK_ERRORS ((volatile un_ETH_RX_IP_CK_ERRORS_t*) 0x404811A8UL)
|
||||
#define CYREG_ETH0_RX_TCP_CK_ERRORS ((volatile un_ETH_RX_TCP_CK_ERRORS_t*) 0x404811ACUL)
|
||||
#define CYREG_ETH0_RX_UDP_CK_ERRORS ((volatile un_ETH_RX_UDP_CK_ERRORS_t*) 0x404811B0UL)
|
||||
#define CYREG_ETH0_AUTO_FLUSHED_PKTS ((volatile un_ETH_AUTO_FLUSHED_PKTS_t*) 0x404811B4UL)
|
||||
#define CYREG_ETH0_TSU_TIMER_INCR_SUB_NSEC ((volatile un_ETH_TSU_TIMER_INCR_SUB_NSEC_t*) 0x404811BCUL)
|
||||
#define CYREG_ETH0_TSU_TIMER_MSB_SEC ((volatile un_ETH_TSU_TIMER_MSB_SEC_t*) 0x404811C0UL)
|
||||
#define CYREG_ETH0_TSU_STROBE_MSB_SEC ((volatile un_ETH_TSU_STROBE_MSB_SEC_t*) 0x404811C4UL)
|
||||
#define CYREG_ETH0_TSU_STROBE_SEC ((volatile un_ETH_TSU_STROBE_SEC_t*) 0x404811C8UL)
|
||||
#define CYREG_ETH0_TSU_STROBE_NSEC ((volatile un_ETH_TSU_STROBE_NSEC_t*) 0x404811CCUL)
|
||||
#define CYREG_ETH0_TSU_TIMER_SEC ((volatile un_ETH_TSU_TIMER_SEC_t*) 0x404811D0UL)
|
||||
#define CYREG_ETH0_TSU_TIMER_NSEC ((volatile un_ETH_TSU_TIMER_NSEC_t*) 0x404811D4UL)
|
||||
#define CYREG_ETH0_TSU_TIMER_ADJUST ((volatile un_ETH_TSU_TIMER_ADJUST_t*) 0x404811D8UL)
|
||||
#define CYREG_ETH0_TSU_TIMER_INCR ((volatile un_ETH_TSU_TIMER_INCR_t*) 0x404811DCUL)
|
||||
#define CYREG_ETH0_TSU_PTP_TX_SEC ((volatile un_ETH_TSU_PTP_TX_SEC_t*) 0x404811E0UL)
|
||||
#define CYREG_ETH0_TSU_PTP_TX_NSEC ((volatile un_ETH_TSU_PTP_TX_NSEC_t*) 0x404811E4UL)
|
||||
#define CYREG_ETH0_TSU_PTP_RX_SEC ((volatile un_ETH_TSU_PTP_RX_SEC_t*) 0x404811E8UL)
|
||||
#define CYREG_ETH0_TSU_PTP_RX_NSEC ((volatile un_ETH_TSU_PTP_RX_NSEC_t*) 0x404811ECUL)
|
||||
#define CYREG_ETH0_TSU_PEER_TX_SEC ((volatile un_ETH_TSU_PEER_TX_SEC_t*) 0x404811F0UL)
|
||||
#define CYREG_ETH0_TSU_PEER_TX_NSEC ((volatile un_ETH_TSU_PEER_TX_NSEC_t*) 0x404811F4UL)
|
||||
#define CYREG_ETH0_TSU_PEER_RX_SEC ((volatile un_ETH_TSU_PEER_RX_SEC_t*) 0x404811F8UL)
|
||||
#define CYREG_ETH0_TSU_PEER_RX_NSEC ((volatile un_ETH_TSU_PEER_RX_NSEC_t*) 0x404811FCUL)
|
||||
#define CYREG_ETH0_PCS_CONTROL ((volatile un_ETH_PCS_CONTROL_t*) 0x40481200UL)
|
||||
#define CYREG_ETH0_PCS_STATUS ((volatile un_ETH_PCS_STATUS_t*) 0x40481204UL)
|
||||
#define CYREG_ETH0_PCS_AN_ADV ((volatile un_ETH_PCS_AN_ADV_t*) 0x40481210UL)
|
||||
#define CYREG_ETH0_PCS_AN_LP_BASE ((volatile un_ETH_PCS_AN_LP_BASE_t*) 0x40481214UL)
|
||||
#define CYREG_ETH0_PCS_AN_EXP ((volatile un_ETH_PCS_AN_EXP_t*) 0x40481218UL)
|
||||
#define CYREG_ETH0_PCS_AN_NP_TX ((volatile un_ETH_PCS_AN_NP_TX_t*) 0x4048121CUL)
|
||||
#define CYREG_ETH0_PCS_AN_LP_NP ((volatile un_ETH_PCS_AN_LP_NP_t*) 0x40481220UL)
|
||||
#define CYREG_ETH0_PCS_AN_EXT_STATUS ((volatile un_ETH_PCS_AN_EXT_STATUS_t*) 0x4048123CUL)
|
||||
#define CYREG_ETH0_TX_PAUSE_QUANTUM1 ((volatile un_ETH_TX_PAUSE_QUANTUM1_t*) 0x40481260UL)
|
||||
#define CYREG_ETH0_TX_PAUSE_QUANTUM2 ((volatile un_ETH_TX_PAUSE_QUANTUM2_t*) 0x40481264UL)
|
||||
#define CYREG_ETH0_TX_PAUSE_QUANTUM3 ((volatile un_ETH_TX_PAUSE_QUANTUM3_t*) 0x40481268UL)
|
||||
#define CYREG_ETH0_RX_LPI ((volatile un_ETH_RX_LPI_t*) 0x40481270UL)
|
||||
#define CYREG_ETH0_RX_LPI_TIME ((volatile un_ETH_RX_LPI_TIME_t*) 0x40481274UL)
|
||||
#define CYREG_ETH0_TX_LPI ((volatile un_ETH_TX_LPI_t*) 0x40481278UL)
|
||||
#define CYREG_ETH0_TX_LPI_TIME ((volatile un_ETH_TX_LPI_TIME_t*) 0x4048127CUL)
|
||||
#define CYREG_ETH0_DESIGNCFG_DEBUG1 ((volatile un_ETH_DESIGNCFG_DEBUG1_t*) 0x40481280UL)
|
||||
#define CYREG_ETH0_DESIGNCFG_DEBUG2 ((volatile un_ETH_DESIGNCFG_DEBUG2_t*) 0x40481284UL)
|
||||
#define CYREG_ETH0_DESIGNCFG_DEBUG3 ((volatile un_ETH_DESIGNCFG_DEBUG3_t*) 0x40481288UL)
|
||||
#define CYREG_ETH0_DESIGNCFG_DEBUG4 ((volatile un_ETH_DESIGNCFG_DEBUG4_t*) 0x4048128CUL)
|
||||
#define CYREG_ETH0_DESIGNCFG_DEBUG5 ((volatile un_ETH_DESIGNCFG_DEBUG5_t*) 0x40481290UL)
|
||||
#define CYREG_ETH0_DESIGNCFG_DEBUG6 ((volatile un_ETH_DESIGNCFG_DEBUG6_t*) 0x40481294UL)
|
||||
#define CYREG_ETH0_DESIGNCFG_DEBUG7 ((volatile un_ETH_DESIGNCFG_DEBUG7_t*) 0x40481298UL)
|
||||
#define CYREG_ETH0_DESIGNCFG_DEBUG8 ((volatile un_ETH_DESIGNCFG_DEBUG8_t*) 0x4048129CUL)
|
||||
#define CYREG_ETH0_DESIGNCFG_DEBUG9 ((volatile un_ETH_DESIGNCFG_DEBUG9_t*) 0x404812A0UL)
|
||||
#define CYREG_ETH0_DESIGNCFG_DEBUG10 ((volatile un_ETH_DESIGNCFG_DEBUG10_t*) 0x404812A4UL)
|
||||
#define CYREG_ETH0_SPEC_ADD5_BOTTOM ((volatile un_ETH_SPEC_ADD5_BOTTOM_t*) 0x40481300UL)
|
||||
#define CYREG_ETH0_SPEC_ADD5_TOP ((volatile un_ETH_SPEC_ADD5_TOP_t*) 0x40481304UL)
|
||||
#define CYREG_ETH0_SPEC_ADD36_BOTTOM ((volatile un_ETH_SPEC_ADD36_BOTTOM_t*) 0x404813F8UL)
|
||||
#define CYREG_ETH0_SPEC_ADD36_TOP ((volatile un_ETH_SPEC_ADD36_TOP_t*) 0x404813FCUL)
|
||||
#define CYREG_ETH0_INT_Q1_STATUS ((volatile un_ETH_INT_Q1_STATUS_t*) 0x40481400UL)
|
||||
#define CYREG_ETH0_INT_Q2_STATUS ((volatile un_ETH_INT_Q2_STATUS_t*) 0x40481404UL)
|
||||
#define CYREG_ETH0_INT_Q3_STATUS ((volatile un_ETH_INT_Q3_STATUS_t*) 0x40481408UL)
|
||||
#define CYREG_ETH0_INT_Q15_STATUS ((volatile un_ETH_INT_Q15_STATUS_t*) 0x40481438UL)
|
||||
#define CYREG_ETH0_TRANSMIT_Q1_PTR ((volatile un_ETH_TRANSMIT_Q1_PTR_t*) 0x40481440UL)
|
||||
#define CYREG_ETH0_TRANSMIT_Q2_PTR ((volatile un_ETH_TRANSMIT_Q2_PTR_t*) 0x40481444UL)
|
||||
#define CYREG_ETH0_TRANSMIT_Q3_PTR ((volatile un_ETH_TRANSMIT_Q3_PTR_t*) 0x40481448UL)
|
||||
#define CYREG_ETH0_TRANSMIT_Q15_PTR ((volatile un_ETH_TRANSMIT_Q15_PTR_t*) 0x40481478UL)
|
||||
#define CYREG_ETH0_RECEIVE_Q1_PTR ((volatile un_ETH_RECEIVE_Q1_PTR_t*) 0x40481480UL)
|
||||
#define CYREG_ETH0_RECEIVE_Q2_PTR ((volatile un_ETH_RECEIVE_Q2_PTR_t*) 0x40481484UL)
|
||||
#define CYREG_ETH0_RECEIVE_Q3_PTR ((volatile un_ETH_RECEIVE_Q3_PTR_t*) 0x40481488UL)
|
||||
#define CYREG_ETH0_RECEIVE_Q7_PTR ((volatile un_ETH_RECEIVE_Q7_PTR_t*) 0x40481498UL)
|
||||
#define CYREG_ETH0_DMA_RXBUF_SIZE_Q1 ((volatile un_ETH_DMA_RXBUF_SIZE_Q1_t*) 0x404814A0UL)
|
||||
#define CYREG_ETH0_DMA_RXBUF_SIZE_Q2 ((volatile un_ETH_DMA_RXBUF_SIZE_Q2_t*) 0x404814A4UL)
|
||||
#define CYREG_ETH0_DMA_RXBUF_SIZE_Q3 ((volatile un_ETH_DMA_RXBUF_SIZE_Q3_t*) 0x404814A8UL)
|
||||
#define CYREG_ETH0_DMA_RXBUF_SIZE_Q7 ((volatile un_ETH_DMA_RXBUF_SIZE_Q7_t*) 0x404814B8UL)
|
||||
#define CYREG_ETH0_CBS_CONTROL ((volatile un_ETH_CBS_CONTROL_t*) 0x404814BCUL)
|
||||
#define CYREG_ETH0_CBS_IDLESLOPE_Q_A ((volatile un_ETH_CBS_IDLESLOPE_Q_A_t*) 0x404814C0UL)
|
||||
#define CYREG_ETH0_CBS_IDLESLOPE_Q_B ((volatile un_ETH_CBS_IDLESLOPE_Q_B_t*) 0x404814C4UL)
|
||||
#define CYREG_ETH0_UPPER_TX_Q_BASE_ADDR ((volatile un_ETH_UPPER_TX_Q_BASE_ADDR_t*) 0x404814C8UL)
|
||||
#define CYREG_ETH0_TX_BD_CONTROL ((volatile un_ETH_TX_BD_CONTROL_t*) 0x404814CCUL)
|
||||
#define CYREG_ETH0_RX_BD_CONTROL ((volatile un_ETH_RX_BD_CONTROL_t*) 0x404814D0UL)
|
||||
#define CYREG_ETH0_UPPER_RX_Q_BASE_ADDR ((volatile un_ETH_UPPER_RX_Q_BASE_ADDR_t*) 0x404814D4UL)
|
||||
#define CYREG_ETH0_HIDDEN_REG0 ((volatile un_ETH_HIDDEN_REG0_t*) 0x404814E0UL)
|
||||
#define CYREG_ETH0_HIDDEN_REG1 ((volatile un_ETH_HIDDEN_REG1_t*) 0x404814E4UL)
|
||||
#define CYREG_ETH0_HIDDEN_REG2 ((volatile un_ETH_HIDDEN_REG2_t*) 0x404814E8UL)
|
||||
#define CYREG_ETH0_HIDDEN_REG3 ((volatile un_ETH_HIDDEN_REG3_t*) 0x404814ECUL)
|
||||
#define CYREG_ETH0_HIDDEN_REG4 ((volatile un_ETH_HIDDEN_REG4_t*) 0x404814F8UL)
|
||||
#define CYREG_ETH0_HIDDEN_REG5 ((volatile un_ETH_HIDDEN_REG5_t*) 0x404814FCUL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_0 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_0_t*) 0x40481500UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_1 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_1_t*) 0x40481504UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_2 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_2_t*) 0x40481508UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_3 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_3_t*) 0x4048150CUL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_4 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_4_t*) 0x40481510UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_5 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_5_t*) 0x40481514UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_6 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_6_t*) 0x40481518UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_7 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_7_t*) 0x4048151CUL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_8 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_8_t*) 0x40481520UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_9 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_9_t*) 0x40481524UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_10 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_10_t*) 0x40481528UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_11 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_11_t*) 0x4048152CUL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_12 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_12_t*) 0x40481530UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_13 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_13_t*) 0x40481534UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_14 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_14_t*) 0x40481538UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_1_REGISTER_15 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_15_t*) 0x4048153CUL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_0 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_0_t*) 0x40481540UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_1 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_1_t*) 0x40481544UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_2 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_2_t*) 0x40481548UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_3 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_3_t*) 0x4048154CUL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_4 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_4_t*) 0x40481550UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_5 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_5_t*) 0x40481554UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_6 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_6_t*) 0x40481558UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_7 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_7_t*) 0x4048155CUL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_8 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_8_t*) 0x40481560UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_9 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_9_t*) 0x40481564UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_10 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_10_t*) 0x40481568UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_11 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_11_t*) 0x4048156CUL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_12 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_12_t*) 0x40481570UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_13 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_13_t*) 0x40481574UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_14 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_14_t*) 0x40481578UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_REGISTER_15 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_15_t*) 0x4048157CUL)
|
||||
#define CYREG_ETH0_TX_SCHED_CTRL ((volatile un_ETH_TX_SCHED_CTRL_t*) 0x40481580UL)
|
||||
#define CYREG_ETH0_BW_RATE_LIMIT_Q0TO3 ((volatile un_ETH_BW_RATE_LIMIT_Q0TO3_t*) 0x40481590UL)
|
||||
#define CYREG_ETH0_BW_RATE_LIMIT_Q4TO7 ((volatile un_ETH_BW_RATE_LIMIT_Q4TO7_t*) 0x40481594UL)
|
||||
#define CYREG_ETH0_BW_RATE_LIMIT_Q8TO11 ((volatile un_ETH_BW_RATE_LIMIT_Q8TO11_t*) 0x40481598UL)
|
||||
#define CYREG_ETH0_BW_RATE_LIMIT_Q12TO15 ((volatile un_ETH_BW_RATE_LIMIT_Q12TO15_t*) 0x4048159CUL)
|
||||
#define CYREG_ETH0_TX_Q_SEG_ALLOC_Q0TO7 ((volatile un_ETH_TX_Q_SEG_ALLOC_Q0TO7_t*) 0x404815A0UL)
|
||||
#define CYREG_ETH0_TX_Q_SEG_ALLOC_Q8TO15 ((volatile un_ETH_TX_Q_SEG_ALLOC_Q8TO15_t*) 0x404815A4UL)
|
||||
#define CYREG_ETH0_RECEIVE_Q8_PTR ((volatile un_ETH_RECEIVE_Q8_PTR_t*) 0x404815C0UL)
|
||||
#define CYREG_ETH0_RECEIVE_Q15_PTR ((volatile un_ETH_RECEIVE_Q15_PTR_t*) 0x404815DCUL)
|
||||
#define CYREG_ETH0_DMA_RXBUF_SIZE_Q8 ((volatile un_ETH_DMA_RXBUF_SIZE_Q8_t*) 0x404815E0UL)
|
||||
#define CYREG_ETH0_DMA_RXBUF_SIZE_Q15 ((volatile un_ETH_DMA_RXBUF_SIZE_Q15_t*) 0x404815FCUL)
|
||||
#define CYREG_ETH0_INT_Q1_ENABLE ((volatile un_ETH_INT_Q1_ENABLE_t*) 0x40481600UL)
|
||||
#define CYREG_ETH0_INT_Q2_ENABLE ((volatile un_ETH_INT_Q2_ENABLE_t*) 0x40481604UL)
|
||||
#define CYREG_ETH0_INT_Q3_ENABLE ((volatile un_ETH_INT_Q3_ENABLE_t*) 0x40481608UL)
|
||||
#define CYREG_ETH0_INT_Q7_ENABLE ((volatile un_ETH_INT_Q7_ENABLE_t*) 0x40481618UL)
|
||||
#define CYREG_ETH0_INT_Q1_DISABLE ((volatile un_ETH_INT_Q1_DISABLE_t*) 0x40481620UL)
|
||||
#define CYREG_ETH0_INT_Q2_DISABLE ((volatile un_ETH_INT_Q2_DISABLE_t*) 0x40481624UL)
|
||||
#define CYREG_ETH0_INT_Q3_DISABLE ((volatile un_ETH_INT_Q3_DISABLE_t*) 0x40481628UL)
|
||||
#define CYREG_ETH0_INT_Q7_DISABLE ((volatile un_ETH_INT_Q7_DISABLE_t*) 0x40481638UL)
|
||||
#define CYREG_ETH0_INT_Q1_MASK ((volatile un_ETH_INT_Q1_MASK_t*) 0x40481640UL)
|
||||
#define CYREG_ETH0_INT_Q2_MASK ((volatile un_ETH_INT_Q2_MASK_t*) 0x40481644UL)
|
||||
#define CYREG_ETH0_INT_Q3_MASK ((volatile un_ETH_INT_Q3_MASK_t*) 0x40481648UL)
|
||||
#define CYREG_ETH0_INT_Q7_MASK ((volatile un_ETH_INT_Q7_MASK_t*) 0x40481658UL)
|
||||
#define CYREG_ETH0_INT_Q8_ENABLE ((volatile un_ETH_INT_Q8_ENABLE_t*) 0x40481660UL)
|
||||
#define CYREG_ETH0_INT_Q15_ENABLE ((volatile un_ETH_INT_Q15_ENABLE_t*) 0x4048167CUL)
|
||||
#define CYREG_ETH0_INT_Q8_DISABLE ((volatile un_ETH_INT_Q8_DISABLE_t*) 0x40481680UL)
|
||||
#define CYREG_ETH0_INT_Q15_DISABLE ((volatile un_ETH_INT_Q15_DISABLE_t*) 0x4048169CUL)
|
||||
#define CYREG_ETH0_INT_Q8_MASK ((volatile un_ETH_INT_Q8_MASK_t*) 0x404816A0UL)
|
||||
#define CYREG_ETH0_INT_Q15_MASK ((volatile un_ETH_INT_Q15_MASK_t*) 0x404816BCUL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_ETHERTYPE_REG_0 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_0_t*) 0x404816E0UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_ETHERTYPE_REG_1 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_1_t*) 0x404816E4UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_ETHERTYPE_REG_2 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_2_t*) 0x404816E8UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_ETHERTYPE_REG_3 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_3_t*) 0x404816ECUL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_ETHERTYPE_REG_4 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_4_t*) 0x404816F0UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_ETHERTYPE_REG_5 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_5_t*) 0x404816F4UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_ETHERTYPE_REG_6 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_6_t*) 0x404816F8UL)
|
||||
#define CYREG_ETH0_SCREENING_TYPE_2_ETHERTYPE_REG_7 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_7_t*) 0x404816FCUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_0_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_0_WORD_0_t*) 0x40481700UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_0_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_0_WORD_1_t*) 0x40481704UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_1_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_1_WORD_0_t*) 0x40481708UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_1_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_1_WORD_1_t*) 0x4048170CUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_2_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_2_WORD_0_t*) 0x40481710UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_2_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_2_WORD_1_t*) 0x40481714UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_3_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_3_WORD_0_t*) 0x40481718UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_3_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_3_WORD_1_t*) 0x4048171CUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_4_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_4_WORD_0_t*) 0x40481720UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_4_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_4_WORD_1_t*) 0x40481724UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_5_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_5_WORD_0_t*) 0x40481728UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_5_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_5_WORD_1_t*) 0x4048172CUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_6_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_6_WORD_0_t*) 0x40481730UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_6_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_6_WORD_1_t*) 0x40481734UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_7_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_7_WORD_0_t*) 0x40481738UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_7_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_7_WORD_1_t*) 0x4048173CUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_8_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_8_WORD_0_t*) 0x40481740UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_8_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_8_WORD_1_t*) 0x40481744UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_9_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_9_WORD_0_t*) 0x40481748UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_9_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_9_WORD_1_t*) 0x4048174CUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_10_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_10_WORD_0_t*) 0x40481750UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_10_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_10_WORD_1_t*) 0x40481754UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_11_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_11_WORD_0_t*) 0x40481758UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_11_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_11_WORD_1_t*) 0x4048175CUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_12_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_12_WORD_0_t*) 0x40481760UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_12_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_12_WORD_1_t*) 0x40481764UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_13_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_13_WORD_0_t*) 0x40481768UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_13_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_13_WORD_1_t*) 0x4048176CUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_14_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_14_WORD_0_t*) 0x40481770UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_14_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_14_WORD_1_t*) 0x40481774UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_15_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_15_WORD_0_t*) 0x40481778UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_15_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_15_WORD_1_t*) 0x4048177CUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_16_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_16_WORD_0_t*) 0x40481780UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_16_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_16_WORD_1_t*) 0x40481784UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_17_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_17_WORD_0_t*) 0x40481788UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_17_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_17_WORD_1_t*) 0x4048178CUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_18_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_18_WORD_0_t*) 0x40481790UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_18_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_18_WORD_1_t*) 0x40481794UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_19_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_19_WORD_0_t*) 0x40481798UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_19_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_19_WORD_1_t*) 0x4048179CUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_20_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_20_WORD_0_t*) 0x404817A0UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_20_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_20_WORD_1_t*) 0x404817A4UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_21_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_21_WORD_0_t*) 0x404817A8UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_21_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_21_WORD_1_t*) 0x404817ACUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_22_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_22_WORD_0_t*) 0x404817B0UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_22_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_22_WORD_1_t*) 0x404817B4UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_23_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_23_WORD_0_t*) 0x404817B8UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_23_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_23_WORD_1_t*) 0x404817BCUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_24_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_24_WORD_0_t*) 0x404817C0UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_24_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_24_WORD_1_t*) 0x404817C4UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_25_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_25_WORD_0_t*) 0x404817C8UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_25_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_25_WORD_1_t*) 0x404817CCUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_26_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_26_WORD_0_t*) 0x404817D0UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_26_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_26_WORD_1_t*) 0x404817D4UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_27_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_27_WORD_0_t*) 0x404817D8UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_27_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_27_WORD_1_t*) 0x404817DCUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_28_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_28_WORD_0_t*) 0x404817E0UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_28_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_28_WORD_1_t*) 0x404817E4UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_29_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_29_WORD_0_t*) 0x404817E8UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_29_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_29_WORD_1_t*) 0x404817ECUL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_30_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_30_WORD_0_t*) 0x404817F0UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_30_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_30_WORD_1_t*) 0x404817F4UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_31_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_31_WORD_0_t*) 0x404817F8UL)
|
||||
#define CYREG_ETH0_TYPE2_COMPARE_31_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_31_WORD_1_t*) 0x404817FCUL)
|
||||
|
||||
/**
|
||||
* \brief Ethernet Interface (ETH1)
|
||||
*/
|
||||
#define CYREG_ETH1_CTL ((volatile un_ETH_CTL_t*) 0x40490000UL)
|
||||
#define CYREG_ETH1_STATUS ((volatile un_ETH_STATUS_t*) 0x40490004UL)
|
||||
#define CYREG_ETH1_NETWORK_CONTROL ((volatile un_ETH_NETWORK_CONTROL_t*) 0x40491000UL)
|
||||
#define CYREG_ETH1_NETWORK_CONFIG ((volatile un_ETH_NETWORK_CONFIG_t*) 0x40491004UL)
|
||||
#define CYREG_ETH1_NETWORK_STATUS ((volatile un_ETH_NETWORK_STATUS_t*) 0x40491008UL)
|
||||
#define CYREG_ETH1_USER_IO_REGISTER ((volatile un_ETH_USER_IO_REGISTER_t*) 0x4049100CUL)
|
||||
#define CYREG_ETH1_DMA_CONFIG ((volatile un_ETH_DMA_CONFIG_t*) 0x40491010UL)
|
||||
#define CYREG_ETH1_TRANSMIT_STATUS ((volatile un_ETH_TRANSMIT_STATUS_t*) 0x40491014UL)
|
||||
#define CYREG_ETH1_RECEIVE_Q_PTR ((volatile un_ETH_RECEIVE_Q_PTR_t*) 0x40491018UL)
|
||||
#define CYREG_ETH1_TRANSMIT_Q_PTR ((volatile un_ETH_TRANSMIT_Q_PTR_t*) 0x4049101CUL)
|
||||
#define CYREG_ETH1_RECEIVE_STATUS ((volatile un_ETH_RECEIVE_STATUS_t*) 0x40491020UL)
|
||||
#define CYREG_ETH1_INT_STATUS ((volatile un_ETH_INT_STATUS_t*) 0x40491024UL)
|
||||
#define CYREG_ETH1_INT_ENABLE ((volatile un_ETH_INT_ENABLE_t*) 0x40491028UL)
|
||||
#define CYREG_ETH1_INT_DISABLE ((volatile un_ETH_INT_DISABLE_t*) 0x4049102CUL)
|
||||
#define CYREG_ETH1_INT_MASK ((volatile un_ETH_INT_MASK_t*) 0x40491030UL)
|
||||
#define CYREG_ETH1_PHY_MANAGEMENT ((volatile un_ETH_PHY_MANAGEMENT_t*) 0x40491034UL)
|
||||
#define CYREG_ETH1_PAUSE_TIME ((volatile un_ETH_PAUSE_TIME_t*) 0x40491038UL)
|
||||
#define CYREG_ETH1_TX_PAUSE_QUANTUM ((volatile un_ETH_TX_PAUSE_QUANTUM_t*) 0x4049103CUL)
|
||||
#define CYREG_ETH1_PBUF_TXCUTTHRU ((volatile un_ETH_PBUF_TXCUTTHRU_t*) 0x40491040UL)
|
||||
#define CYREG_ETH1_PBUF_RXCUTTHRU ((volatile un_ETH_PBUF_RXCUTTHRU_t*) 0x40491044UL)
|
||||
#define CYREG_ETH1_JUMBO_MAX_LENGTH ((volatile un_ETH_JUMBO_MAX_LENGTH_t*) 0x40491048UL)
|
||||
#define CYREG_ETH1_EXTERNAL_FIFO_INTERFACE ((volatile un_ETH_EXTERNAL_FIFO_INTERFACE_t*) 0x4049104CUL)
|
||||
#define CYREG_ETH1_AXI_MAX_PIPELINE ((volatile un_ETH_AXI_MAX_PIPELINE_t*) 0x40491054UL)
|
||||
#define CYREG_ETH1_RSC_CONTROL ((volatile un_ETH_RSC_CONTROL_t*) 0x40491058UL)
|
||||
#define CYREG_ETH1_INT_MODERATION ((volatile un_ETH_INT_MODERATION_t*) 0x4049105CUL)
|
||||
#define CYREG_ETH1_SYS_WAKE_TIME ((volatile un_ETH_SYS_WAKE_TIME_t*) 0x40491060UL)
|
||||
#define CYREG_ETH1_HASH_BOTTOM ((volatile un_ETH_HASH_BOTTOM_t*) 0x40491080UL)
|
||||
#define CYREG_ETH1_HASH_TOP ((volatile un_ETH_HASH_TOP_t*) 0x40491084UL)
|
||||
#define CYREG_ETH1_SPEC_ADD1_BOTTOM ((volatile un_ETH_SPEC_ADD1_BOTTOM_t*) 0x40491088UL)
|
||||
#define CYREG_ETH1_SPEC_ADD1_TOP ((volatile un_ETH_SPEC_ADD1_TOP_t*) 0x4049108CUL)
|
||||
#define CYREG_ETH1_SPEC_ADD2_BOTTOM ((volatile un_ETH_SPEC_ADD2_BOTTOM_t*) 0x40491090UL)
|
||||
#define CYREG_ETH1_SPEC_ADD2_TOP ((volatile un_ETH_SPEC_ADD2_TOP_t*) 0x40491094UL)
|
||||
#define CYREG_ETH1_SPEC_ADD3_BOTTOM ((volatile un_ETH_SPEC_ADD3_BOTTOM_t*) 0x40491098UL)
|
||||
#define CYREG_ETH1_SPEC_ADD3_TOP ((volatile un_ETH_SPEC_ADD3_TOP_t*) 0x4049109CUL)
|
||||
#define CYREG_ETH1_SPEC_ADD4_BOTTOM ((volatile un_ETH_SPEC_ADD4_BOTTOM_t*) 0x404910A0UL)
|
||||
#define CYREG_ETH1_SPEC_ADD4_TOP ((volatile un_ETH_SPEC_ADD4_TOP_t*) 0x404910A4UL)
|
||||
#define CYREG_ETH1_SPEC_TYPE1 ((volatile un_ETH_SPEC_TYPE1_t*) 0x404910A8UL)
|
||||
#define CYREG_ETH1_SPEC_TYPE2 ((volatile un_ETH_SPEC_TYPE2_t*) 0x404910ACUL)
|
||||
#define CYREG_ETH1_SPEC_TYPE3 ((volatile un_ETH_SPEC_TYPE3_t*) 0x404910B0UL)
|
||||
#define CYREG_ETH1_SPEC_TYPE4 ((volatile un_ETH_SPEC_TYPE4_t*) 0x404910B4UL)
|
||||
#define CYREG_ETH1_WOL_REGISTER ((volatile un_ETH_WOL_REGISTER_t*) 0x404910B8UL)
|
||||
#define CYREG_ETH1_STRETCH_RATIO ((volatile un_ETH_STRETCH_RATIO_t*) 0x404910BCUL)
|
||||
#define CYREG_ETH1_STACKED_VLAN ((volatile un_ETH_STACKED_VLAN_t*) 0x404910C0UL)
|
||||
#define CYREG_ETH1_TX_PFC_PAUSE ((volatile un_ETH_TX_PFC_PAUSE_t*) 0x404910C4UL)
|
||||
#define CYREG_ETH1_MASK_ADD1_BOTTOM ((volatile un_ETH_MASK_ADD1_BOTTOM_t*) 0x404910C8UL)
|
||||
#define CYREG_ETH1_MASK_ADD1_TOP ((volatile un_ETH_MASK_ADD1_TOP_t*) 0x404910CCUL)
|
||||
#define CYREG_ETH1_DMA_ADDR_OR_MASK ((volatile un_ETH_DMA_ADDR_OR_MASK_t*) 0x404910D0UL)
|
||||
#define CYREG_ETH1_RX_PTP_UNICAST ((volatile un_ETH_RX_PTP_UNICAST_t*) 0x404910D4UL)
|
||||
#define CYREG_ETH1_TX_PTP_UNICAST ((volatile un_ETH_TX_PTP_UNICAST_t*) 0x404910D8UL)
|
||||
#define CYREG_ETH1_TSU_NSEC_CMP ((volatile un_ETH_TSU_NSEC_CMP_t*) 0x404910DCUL)
|
||||
#define CYREG_ETH1_TSU_SEC_CMP ((volatile un_ETH_TSU_SEC_CMP_t*) 0x404910E0UL)
|
||||
#define CYREG_ETH1_TSU_MSB_SEC_CMP ((volatile un_ETH_TSU_MSB_SEC_CMP_t*) 0x404910E4UL)
|
||||
#define CYREG_ETH1_TSU_PTP_TX_MSB_SEC ((volatile un_ETH_TSU_PTP_TX_MSB_SEC_t*) 0x404910E8UL)
|
||||
#define CYREG_ETH1_TSU_PTP_RX_MSB_SEC ((volatile un_ETH_TSU_PTP_RX_MSB_SEC_t*) 0x404910ECUL)
|
||||
#define CYREG_ETH1_TSU_PEER_TX_MSB_SEC ((volatile un_ETH_TSU_PEER_TX_MSB_SEC_t*) 0x404910F0UL)
|
||||
#define CYREG_ETH1_TSU_PEER_RX_MSB_SEC ((volatile un_ETH_TSU_PEER_RX_MSB_SEC_t*) 0x404910F4UL)
|
||||
#define CYREG_ETH1_DPRAM_FILL_DBG ((volatile un_ETH_DPRAM_FILL_DBG_t*) 0x404910F8UL)
|
||||
#define CYREG_ETH1_REVISION_REG ((volatile un_ETH_REVISION_REG_t*) 0x404910FCUL)
|
||||
#define CYREG_ETH1_OCTETS_TXED_BOTTOM ((volatile un_ETH_OCTETS_TXED_BOTTOM_t*) 0x40491100UL)
|
||||
#define CYREG_ETH1_OCTETS_TXED_TOP ((volatile un_ETH_OCTETS_TXED_TOP_t*) 0x40491104UL)
|
||||
#define CYREG_ETH1_FRAMES_TXED_OK ((volatile un_ETH_FRAMES_TXED_OK_t*) 0x40491108UL)
|
||||
#define CYREG_ETH1_BROADCAST_TXED ((volatile un_ETH_BROADCAST_TXED_t*) 0x4049110CUL)
|
||||
#define CYREG_ETH1_MULTICAST_TXED ((volatile un_ETH_MULTICAST_TXED_t*) 0x40491110UL)
|
||||
#define CYREG_ETH1_PAUSE_FRAMES_TXED ((volatile un_ETH_PAUSE_FRAMES_TXED_t*) 0x40491114UL)
|
||||
#define CYREG_ETH1_FRAMES_TXED_64 ((volatile un_ETH_FRAMES_TXED_64_t*) 0x40491118UL)
|
||||
#define CYREG_ETH1_FRAMES_TXED_65 ((volatile un_ETH_FRAMES_TXED_65_t*) 0x4049111CUL)
|
||||
#define CYREG_ETH1_FRAMES_TXED_128 ((volatile un_ETH_FRAMES_TXED_128_t*) 0x40491120UL)
|
||||
#define CYREG_ETH1_FRAMES_TXED_256 ((volatile un_ETH_FRAMES_TXED_256_t*) 0x40491124UL)
|
||||
#define CYREG_ETH1_FRAMES_TXED_512 ((volatile un_ETH_FRAMES_TXED_512_t*) 0x40491128UL)
|
||||
#define CYREG_ETH1_FRAMES_TXED_1024 ((volatile un_ETH_FRAMES_TXED_1024_t*) 0x4049112CUL)
|
||||
#define CYREG_ETH1_FRAMES_TXED_1519 ((volatile un_ETH_FRAMES_TXED_1519_t*) 0x40491130UL)
|
||||
#define CYREG_ETH1_TX_UNDERRUNS ((volatile un_ETH_TX_UNDERRUNS_t*) 0x40491134UL)
|
||||
#define CYREG_ETH1_SINGLE_COLLISIONS ((volatile un_ETH_SINGLE_COLLISIONS_t*) 0x40491138UL)
|
||||
#define CYREG_ETH1_MULTIPLE_COLLISIONS ((volatile un_ETH_MULTIPLE_COLLISIONS_t*) 0x4049113CUL)
|
||||
#define CYREG_ETH1_EXCESSIVE_COLLISIONS ((volatile un_ETH_EXCESSIVE_COLLISIONS_t*) 0x40491140UL)
|
||||
#define CYREG_ETH1_LATE_COLLISIONS ((volatile un_ETH_LATE_COLLISIONS_t*) 0x40491144UL)
|
||||
#define CYREG_ETH1_DEFERRED_FRAMES ((volatile un_ETH_DEFERRED_FRAMES_t*) 0x40491148UL)
|
||||
#define CYREG_ETH1_CRS_ERRORS ((volatile un_ETH_CRS_ERRORS_t*) 0x4049114CUL)
|
||||
#define CYREG_ETH1_OCTETS_RXED_BOTTOM ((volatile un_ETH_OCTETS_RXED_BOTTOM_t*) 0x40491150UL)
|
||||
#define CYREG_ETH1_OCTETS_RXED_TOP ((volatile un_ETH_OCTETS_RXED_TOP_t*) 0x40491154UL)
|
||||
#define CYREG_ETH1_FRAMES_RXED_OK ((volatile un_ETH_FRAMES_RXED_OK_t*) 0x40491158UL)
|
||||
#define CYREG_ETH1_BROADCAST_RXED ((volatile un_ETH_BROADCAST_RXED_t*) 0x4049115CUL)
|
||||
#define CYREG_ETH1_MULTICAST_RXED ((volatile un_ETH_MULTICAST_RXED_t*) 0x40491160UL)
|
||||
#define CYREG_ETH1_PAUSE_FRAMES_RXED ((volatile un_ETH_PAUSE_FRAMES_RXED_t*) 0x40491164UL)
|
||||
#define CYREG_ETH1_FRAMES_RXED_64 ((volatile un_ETH_FRAMES_RXED_64_t*) 0x40491168UL)
|
||||
#define CYREG_ETH1_FRAMES_RXED_65 ((volatile un_ETH_FRAMES_RXED_65_t*) 0x4049116CUL)
|
||||
#define CYREG_ETH1_FRAMES_RXED_128 ((volatile un_ETH_FRAMES_RXED_128_t*) 0x40491170UL)
|
||||
#define CYREG_ETH1_FRAMES_RXED_256 ((volatile un_ETH_FRAMES_RXED_256_t*) 0x40491174UL)
|
||||
#define CYREG_ETH1_FRAMES_RXED_512 ((volatile un_ETH_FRAMES_RXED_512_t*) 0x40491178UL)
|
||||
#define CYREG_ETH1_FRAMES_RXED_1024 ((volatile un_ETH_FRAMES_RXED_1024_t*) 0x4049117CUL)
|
||||
#define CYREG_ETH1_FRAMES_RXED_1519 ((volatile un_ETH_FRAMES_RXED_1519_t*) 0x40491180UL)
|
||||
#define CYREG_ETH1_UNDERSIZE_FRAMES ((volatile un_ETH_UNDERSIZE_FRAMES_t*) 0x40491184UL)
|
||||
#define CYREG_ETH1_EXCESSIVE_RX_LENGTH ((volatile un_ETH_EXCESSIVE_RX_LENGTH_t*) 0x40491188UL)
|
||||
#define CYREG_ETH1_RX_JABBERS ((volatile un_ETH_RX_JABBERS_t*) 0x4049118CUL)
|
||||
#define CYREG_ETH1_FCS_ERRORS ((volatile un_ETH_FCS_ERRORS_t*) 0x40491190UL)
|
||||
#define CYREG_ETH1_RX_LENGTH_ERRORS ((volatile un_ETH_RX_LENGTH_ERRORS_t*) 0x40491194UL)
|
||||
#define CYREG_ETH1_RX_SYMBOL_ERRORS ((volatile un_ETH_RX_SYMBOL_ERRORS_t*) 0x40491198UL)
|
||||
#define CYREG_ETH1_ALIGNMENT_ERRORS ((volatile un_ETH_ALIGNMENT_ERRORS_t*) 0x4049119CUL)
|
||||
#define CYREG_ETH1_RX_RESOURCE_ERRORS ((volatile un_ETH_RX_RESOURCE_ERRORS_t*) 0x404911A0UL)
|
||||
#define CYREG_ETH1_RX_OVERRUNS ((volatile un_ETH_RX_OVERRUNS_t*) 0x404911A4UL)
|
||||
#define CYREG_ETH1_RX_IP_CK_ERRORS ((volatile un_ETH_RX_IP_CK_ERRORS_t*) 0x404911A8UL)
|
||||
#define CYREG_ETH1_RX_TCP_CK_ERRORS ((volatile un_ETH_RX_TCP_CK_ERRORS_t*) 0x404911ACUL)
|
||||
#define CYREG_ETH1_RX_UDP_CK_ERRORS ((volatile un_ETH_RX_UDP_CK_ERRORS_t*) 0x404911B0UL)
|
||||
#define CYREG_ETH1_AUTO_FLUSHED_PKTS ((volatile un_ETH_AUTO_FLUSHED_PKTS_t*) 0x404911B4UL)
|
||||
#define CYREG_ETH1_TSU_TIMER_INCR_SUB_NSEC ((volatile un_ETH_TSU_TIMER_INCR_SUB_NSEC_t*) 0x404911BCUL)
|
||||
#define CYREG_ETH1_TSU_TIMER_MSB_SEC ((volatile un_ETH_TSU_TIMER_MSB_SEC_t*) 0x404911C0UL)
|
||||
#define CYREG_ETH1_TSU_STROBE_MSB_SEC ((volatile un_ETH_TSU_STROBE_MSB_SEC_t*) 0x404911C4UL)
|
||||
#define CYREG_ETH1_TSU_STROBE_SEC ((volatile un_ETH_TSU_STROBE_SEC_t*) 0x404911C8UL)
|
||||
#define CYREG_ETH1_TSU_STROBE_NSEC ((volatile un_ETH_TSU_STROBE_NSEC_t*) 0x404911CCUL)
|
||||
#define CYREG_ETH1_TSU_TIMER_SEC ((volatile un_ETH_TSU_TIMER_SEC_t*) 0x404911D0UL)
|
||||
#define CYREG_ETH1_TSU_TIMER_NSEC ((volatile un_ETH_TSU_TIMER_NSEC_t*) 0x404911D4UL)
|
||||
#define CYREG_ETH1_TSU_TIMER_ADJUST ((volatile un_ETH_TSU_TIMER_ADJUST_t*) 0x404911D8UL)
|
||||
#define CYREG_ETH1_TSU_TIMER_INCR ((volatile un_ETH_TSU_TIMER_INCR_t*) 0x404911DCUL)
|
||||
#define CYREG_ETH1_TSU_PTP_TX_SEC ((volatile un_ETH_TSU_PTP_TX_SEC_t*) 0x404911E0UL)
|
||||
#define CYREG_ETH1_TSU_PTP_TX_NSEC ((volatile un_ETH_TSU_PTP_TX_NSEC_t*) 0x404911E4UL)
|
||||
#define CYREG_ETH1_TSU_PTP_RX_SEC ((volatile un_ETH_TSU_PTP_RX_SEC_t*) 0x404911E8UL)
|
||||
#define CYREG_ETH1_TSU_PTP_RX_NSEC ((volatile un_ETH_TSU_PTP_RX_NSEC_t*) 0x404911ECUL)
|
||||
#define CYREG_ETH1_TSU_PEER_TX_SEC ((volatile un_ETH_TSU_PEER_TX_SEC_t*) 0x404911F0UL)
|
||||
#define CYREG_ETH1_TSU_PEER_TX_NSEC ((volatile un_ETH_TSU_PEER_TX_NSEC_t*) 0x404911F4UL)
|
||||
#define CYREG_ETH1_TSU_PEER_RX_SEC ((volatile un_ETH_TSU_PEER_RX_SEC_t*) 0x404911F8UL)
|
||||
#define CYREG_ETH1_TSU_PEER_RX_NSEC ((volatile un_ETH_TSU_PEER_RX_NSEC_t*) 0x404911FCUL)
|
||||
#define CYREG_ETH1_PCS_CONTROL ((volatile un_ETH_PCS_CONTROL_t*) 0x40491200UL)
|
||||
#define CYREG_ETH1_PCS_STATUS ((volatile un_ETH_PCS_STATUS_t*) 0x40491204UL)
|
||||
#define CYREG_ETH1_PCS_AN_ADV ((volatile un_ETH_PCS_AN_ADV_t*) 0x40491210UL)
|
||||
#define CYREG_ETH1_PCS_AN_LP_BASE ((volatile un_ETH_PCS_AN_LP_BASE_t*) 0x40491214UL)
|
||||
#define CYREG_ETH1_PCS_AN_EXP ((volatile un_ETH_PCS_AN_EXP_t*) 0x40491218UL)
|
||||
#define CYREG_ETH1_PCS_AN_NP_TX ((volatile un_ETH_PCS_AN_NP_TX_t*) 0x4049121CUL)
|
||||
#define CYREG_ETH1_PCS_AN_LP_NP ((volatile un_ETH_PCS_AN_LP_NP_t*) 0x40491220UL)
|
||||
#define CYREG_ETH1_PCS_AN_EXT_STATUS ((volatile un_ETH_PCS_AN_EXT_STATUS_t*) 0x4049123CUL)
|
||||
#define CYREG_ETH1_TX_PAUSE_QUANTUM1 ((volatile un_ETH_TX_PAUSE_QUANTUM1_t*) 0x40491260UL)
|
||||
#define CYREG_ETH1_TX_PAUSE_QUANTUM2 ((volatile un_ETH_TX_PAUSE_QUANTUM2_t*) 0x40491264UL)
|
||||
#define CYREG_ETH1_TX_PAUSE_QUANTUM3 ((volatile un_ETH_TX_PAUSE_QUANTUM3_t*) 0x40491268UL)
|
||||
#define CYREG_ETH1_RX_LPI ((volatile un_ETH_RX_LPI_t*) 0x40491270UL)
|
||||
#define CYREG_ETH1_RX_LPI_TIME ((volatile un_ETH_RX_LPI_TIME_t*) 0x40491274UL)
|
||||
#define CYREG_ETH1_TX_LPI ((volatile un_ETH_TX_LPI_t*) 0x40491278UL)
|
||||
#define CYREG_ETH1_TX_LPI_TIME ((volatile un_ETH_TX_LPI_TIME_t*) 0x4049127CUL)
|
||||
#define CYREG_ETH1_DESIGNCFG_DEBUG1 ((volatile un_ETH_DESIGNCFG_DEBUG1_t*) 0x40491280UL)
|
||||
#define CYREG_ETH1_DESIGNCFG_DEBUG2 ((volatile un_ETH_DESIGNCFG_DEBUG2_t*) 0x40491284UL)
|
||||
#define CYREG_ETH1_DESIGNCFG_DEBUG3 ((volatile un_ETH_DESIGNCFG_DEBUG3_t*) 0x40491288UL)
|
||||
#define CYREG_ETH1_DESIGNCFG_DEBUG4 ((volatile un_ETH_DESIGNCFG_DEBUG4_t*) 0x4049128CUL)
|
||||
#define CYREG_ETH1_DESIGNCFG_DEBUG5 ((volatile un_ETH_DESIGNCFG_DEBUG5_t*) 0x40491290UL)
|
||||
#define CYREG_ETH1_DESIGNCFG_DEBUG6 ((volatile un_ETH_DESIGNCFG_DEBUG6_t*) 0x40491294UL)
|
||||
#define CYREG_ETH1_DESIGNCFG_DEBUG7 ((volatile un_ETH_DESIGNCFG_DEBUG7_t*) 0x40491298UL)
|
||||
#define CYREG_ETH1_DESIGNCFG_DEBUG8 ((volatile un_ETH_DESIGNCFG_DEBUG8_t*) 0x4049129CUL)
|
||||
#define CYREG_ETH1_DESIGNCFG_DEBUG9 ((volatile un_ETH_DESIGNCFG_DEBUG9_t*) 0x404912A0UL)
|
||||
#define CYREG_ETH1_DESIGNCFG_DEBUG10 ((volatile un_ETH_DESIGNCFG_DEBUG10_t*) 0x404912A4UL)
|
||||
#define CYREG_ETH1_SPEC_ADD5_BOTTOM ((volatile un_ETH_SPEC_ADD5_BOTTOM_t*) 0x40491300UL)
|
||||
#define CYREG_ETH1_SPEC_ADD5_TOP ((volatile un_ETH_SPEC_ADD5_TOP_t*) 0x40491304UL)
|
||||
#define CYREG_ETH1_SPEC_ADD36_BOTTOM ((volatile un_ETH_SPEC_ADD36_BOTTOM_t*) 0x404913F8UL)
|
||||
#define CYREG_ETH1_SPEC_ADD36_TOP ((volatile un_ETH_SPEC_ADD36_TOP_t*) 0x404913FCUL)
|
||||
#define CYREG_ETH1_INT_Q1_STATUS ((volatile un_ETH_INT_Q1_STATUS_t*) 0x40491400UL)
|
||||
#define CYREG_ETH1_INT_Q2_STATUS ((volatile un_ETH_INT_Q2_STATUS_t*) 0x40491404UL)
|
||||
#define CYREG_ETH1_INT_Q3_STATUS ((volatile un_ETH_INT_Q3_STATUS_t*) 0x40491408UL)
|
||||
#define CYREG_ETH1_INT_Q15_STATUS ((volatile un_ETH_INT_Q15_STATUS_t*) 0x40491438UL)
|
||||
#define CYREG_ETH1_TRANSMIT_Q1_PTR ((volatile un_ETH_TRANSMIT_Q1_PTR_t*) 0x40491440UL)
|
||||
#define CYREG_ETH1_TRANSMIT_Q2_PTR ((volatile un_ETH_TRANSMIT_Q2_PTR_t*) 0x40491444UL)
|
||||
#define CYREG_ETH1_TRANSMIT_Q3_PTR ((volatile un_ETH_TRANSMIT_Q3_PTR_t*) 0x40491448UL)
|
||||
#define CYREG_ETH1_TRANSMIT_Q15_PTR ((volatile un_ETH_TRANSMIT_Q15_PTR_t*) 0x40491478UL)
|
||||
#define CYREG_ETH1_RECEIVE_Q1_PTR ((volatile un_ETH_RECEIVE_Q1_PTR_t*) 0x40491480UL)
|
||||
#define CYREG_ETH1_RECEIVE_Q2_PTR ((volatile un_ETH_RECEIVE_Q2_PTR_t*) 0x40491484UL)
|
||||
#define CYREG_ETH1_RECEIVE_Q3_PTR ((volatile un_ETH_RECEIVE_Q3_PTR_t*) 0x40491488UL)
|
||||
#define CYREG_ETH1_RECEIVE_Q7_PTR ((volatile un_ETH_RECEIVE_Q7_PTR_t*) 0x40491498UL)
|
||||
#define CYREG_ETH1_DMA_RXBUF_SIZE_Q1 ((volatile un_ETH_DMA_RXBUF_SIZE_Q1_t*) 0x404914A0UL)
|
||||
#define CYREG_ETH1_DMA_RXBUF_SIZE_Q2 ((volatile un_ETH_DMA_RXBUF_SIZE_Q2_t*) 0x404914A4UL)
|
||||
#define CYREG_ETH1_DMA_RXBUF_SIZE_Q3 ((volatile un_ETH_DMA_RXBUF_SIZE_Q3_t*) 0x404914A8UL)
|
||||
#define CYREG_ETH1_DMA_RXBUF_SIZE_Q7 ((volatile un_ETH_DMA_RXBUF_SIZE_Q7_t*) 0x404914B8UL)
|
||||
#define CYREG_ETH1_CBS_CONTROL ((volatile un_ETH_CBS_CONTROL_t*) 0x404914BCUL)
|
||||
#define CYREG_ETH1_CBS_IDLESLOPE_Q_A ((volatile un_ETH_CBS_IDLESLOPE_Q_A_t*) 0x404914C0UL)
|
||||
#define CYREG_ETH1_CBS_IDLESLOPE_Q_B ((volatile un_ETH_CBS_IDLESLOPE_Q_B_t*) 0x404914C4UL)
|
||||
#define CYREG_ETH1_UPPER_TX_Q_BASE_ADDR ((volatile un_ETH_UPPER_TX_Q_BASE_ADDR_t*) 0x404914C8UL)
|
||||
#define CYREG_ETH1_TX_BD_CONTROL ((volatile un_ETH_TX_BD_CONTROL_t*) 0x404914CCUL)
|
||||
#define CYREG_ETH1_RX_BD_CONTROL ((volatile un_ETH_RX_BD_CONTROL_t*) 0x404914D0UL)
|
||||
#define CYREG_ETH1_UPPER_RX_Q_BASE_ADDR ((volatile un_ETH_UPPER_RX_Q_BASE_ADDR_t*) 0x404914D4UL)
|
||||
#define CYREG_ETH1_HIDDEN_REG0 ((volatile un_ETH_HIDDEN_REG0_t*) 0x404914E0UL)
|
||||
#define CYREG_ETH1_HIDDEN_REG1 ((volatile un_ETH_HIDDEN_REG1_t*) 0x404914E4UL)
|
||||
#define CYREG_ETH1_HIDDEN_REG2 ((volatile un_ETH_HIDDEN_REG2_t*) 0x404914E8UL)
|
||||
#define CYREG_ETH1_HIDDEN_REG3 ((volatile un_ETH_HIDDEN_REG3_t*) 0x404914ECUL)
|
||||
#define CYREG_ETH1_HIDDEN_REG4 ((volatile un_ETH_HIDDEN_REG4_t*) 0x404914F8UL)
|
||||
#define CYREG_ETH1_HIDDEN_REG5 ((volatile un_ETH_HIDDEN_REG5_t*) 0x404914FCUL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_0 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_0_t*) 0x40491500UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_1 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_1_t*) 0x40491504UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_2 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_2_t*) 0x40491508UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_3 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_3_t*) 0x4049150CUL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_4 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_4_t*) 0x40491510UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_5 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_5_t*) 0x40491514UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_6 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_6_t*) 0x40491518UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_7 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_7_t*) 0x4049151CUL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_8 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_8_t*) 0x40491520UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_9 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_9_t*) 0x40491524UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_10 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_10_t*) 0x40491528UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_11 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_11_t*) 0x4049152CUL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_12 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_12_t*) 0x40491530UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_13 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_13_t*) 0x40491534UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_14 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_14_t*) 0x40491538UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_1_REGISTER_15 ((volatile un_ETH_SCREENING_TYPE_1_REGISTER_15_t*) 0x4049153CUL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_0 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_0_t*) 0x40491540UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_1 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_1_t*) 0x40491544UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_2 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_2_t*) 0x40491548UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_3 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_3_t*) 0x4049154CUL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_4 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_4_t*) 0x40491550UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_5 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_5_t*) 0x40491554UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_6 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_6_t*) 0x40491558UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_7 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_7_t*) 0x4049155CUL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_8 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_8_t*) 0x40491560UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_9 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_9_t*) 0x40491564UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_10 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_10_t*) 0x40491568UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_11 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_11_t*) 0x4049156CUL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_12 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_12_t*) 0x40491570UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_13 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_13_t*) 0x40491574UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_14 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_14_t*) 0x40491578UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_REGISTER_15 ((volatile un_ETH_SCREENING_TYPE_2_REGISTER_15_t*) 0x4049157CUL)
|
||||
#define CYREG_ETH1_TX_SCHED_CTRL ((volatile un_ETH_TX_SCHED_CTRL_t*) 0x40491580UL)
|
||||
#define CYREG_ETH1_BW_RATE_LIMIT_Q0TO3 ((volatile un_ETH_BW_RATE_LIMIT_Q0TO3_t*) 0x40491590UL)
|
||||
#define CYREG_ETH1_BW_RATE_LIMIT_Q4TO7 ((volatile un_ETH_BW_RATE_LIMIT_Q4TO7_t*) 0x40491594UL)
|
||||
#define CYREG_ETH1_BW_RATE_LIMIT_Q8TO11 ((volatile un_ETH_BW_RATE_LIMIT_Q8TO11_t*) 0x40491598UL)
|
||||
#define CYREG_ETH1_BW_RATE_LIMIT_Q12TO15 ((volatile un_ETH_BW_RATE_LIMIT_Q12TO15_t*) 0x4049159CUL)
|
||||
#define CYREG_ETH1_TX_Q_SEG_ALLOC_Q0TO7 ((volatile un_ETH_TX_Q_SEG_ALLOC_Q0TO7_t*) 0x404915A0UL)
|
||||
#define CYREG_ETH1_TX_Q_SEG_ALLOC_Q8TO15 ((volatile un_ETH_TX_Q_SEG_ALLOC_Q8TO15_t*) 0x404915A4UL)
|
||||
#define CYREG_ETH1_RECEIVE_Q8_PTR ((volatile un_ETH_RECEIVE_Q8_PTR_t*) 0x404915C0UL)
|
||||
#define CYREG_ETH1_RECEIVE_Q15_PTR ((volatile un_ETH_RECEIVE_Q15_PTR_t*) 0x404915DCUL)
|
||||
#define CYREG_ETH1_DMA_RXBUF_SIZE_Q8 ((volatile un_ETH_DMA_RXBUF_SIZE_Q8_t*) 0x404915E0UL)
|
||||
#define CYREG_ETH1_DMA_RXBUF_SIZE_Q15 ((volatile un_ETH_DMA_RXBUF_SIZE_Q15_t*) 0x404915FCUL)
|
||||
#define CYREG_ETH1_INT_Q1_ENABLE ((volatile un_ETH_INT_Q1_ENABLE_t*) 0x40491600UL)
|
||||
#define CYREG_ETH1_INT_Q2_ENABLE ((volatile un_ETH_INT_Q2_ENABLE_t*) 0x40491604UL)
|
||||
#define CYREG_ETH1_INT_Q3_ENABLE ((volatile un_ETH_INT_Q3_ENABLE_t*) 0x40491608UL)
|
||||
#define CYREG_ETH1_INT_Q7_ENABLE ((volatile un_ETH_INT_Q7_ENABLE_t*) 0x40491618UL)
|
||||
#define CYREG_ETH1_INT_Q1_DISABLE ((volatile un_ETH_INT_Q1_DISABLE_t*) 0x40491620UL)
|
||||
#define CYREG_ETH1_INT_Q2_DISABLE ((volatile un_ETH_INT_Q2_DISABLE_t*) 0x40491624UL)
|
||||
#define CYREG_ETH1_INT_Q3_DISABLE ((volatile un_ETH_INT_Q3_DISABLE_t*) 0x40491628UL)
|
||||
#define CYREG_ETH1_INT_Q7_DISABLE ((volatile un_ETH_INT_Q7_DISABLE_t*) 0x40491638UL)
|
||||
#define CYREG_ETH1_INT_Q1_MASK ((volatile un_ETH_INT_Q1_MASK_t*) 0x40491640UL)
|
||||
#define CYREG_ETH1_INT_Q2_MASK ((volatile un_ETH_INT_Q2_MASK_t*) 0x40491644UL)
|
||||
#define CYREG_ETH1_INT_Q3_MASK ((volatile un_ETH_INT_Q3_MASK_t*) 0x40491648UL)
|
||||
#define CYREG_ETH1_INT_Q7_MASK ((volatile un_ETH_INT_Q7_MASK_t*) 0x40491658UL)
|
||||
#define CYREG_ETH1_INT_Q8_ENABLE ((volatile un_ETH_INT_Q8_ENABLE_t*) 0x40491660UL)
|
||||
#define CYREG_ETH1_INT_Q15_ENABLE ((volatile un_ETH_INT_Q15_ENABLE_t*) 0x4049167CUL)
|
||||
#define CYREG_ETH1_INT_Q8_DISABLE ((volatile un_ETH_INT_Q8_DISABLE_t*) 0x40491680UL)
|
||||
#define CYREG_ETH1_INT_Q15_DISABLE ((volatile un_ETH_INT_Q15_DISABLE_t*) 0x4049169CUL)
|
||||
#define CYREG_ETH1_INT_Q8_MASK ((volatile un_ETH_INT_Q8_MASK_t*) 0x404916A0UL)
|
||||
#define CYREG_ETH1_INT_Q15_MASK ((volatile un_ETH_INT_Q15_MASK_t*) 0x404916BCUL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_ETHERTYPE_REG_0 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_0_t*) 0x404916E0UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_ETHERTYPE_REG_1 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_1_t*) 0x404916E4UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_ETHERTYPE_REG_2 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_2_t*) 0x404916E8UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_ETHERTYPE_REG_3 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_3_t*) 0x404916ECUL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_ETHERTYPE_REG_4 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_4_t*) 0x404916F0UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_ETHERTYPE_REG_5 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_5_t*) 0x404916F4UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_ETHERTYPE_REG_6 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_6_t*) 0x404916F8UL)
|
||||
#define CYREG_ETH1_SCREENING_TYPE_2_ETHERTYPE_REG_7 ((volatile un_ETH_SCREENING_TYPE_2_ETHERTYPE_REG_7_t*) 0x404916FCUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_0_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_0_WORD_0_t*) 0x40491700UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_0_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_0_WORD_1_t*) 0x40491704UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_1_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_1_WORD_0_t*) 0x40491708UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_1_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_1_WORD_1_t*) 0x4049170CUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_2_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_2_WORD_0_t*) 0x40491710UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_2_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_2_WORD_1_t*) 0x40491714UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_3_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_3_WORD_0_t*) 0x40491718UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_3_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_3_WORD_1_t*) 0x4049171CUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_4_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_4_WORD_0_t*) 0x40491720UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_4_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_4_WORD_1_t*) 0x40491724UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_5_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_5_WORD_0_t*) 0x40491728UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_5_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_5_WORD_1_t*) 0x4049172CUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_6_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_6_WORD_0_t*) 0x40491730UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_6_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_6_WORD_1_t*) 0x40491734UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_7_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_7_WORD_0_t*) 0x40491738UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_7_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_7_WORD_1_t*) 0x4049173CUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_8_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_8_WORD_0_t*) 0x40491740UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_8_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_8_WORD_1_t*) 0x40491744UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_9_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_9_WORD_0_t*) 0x40491748UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_9_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_9_WORD_1_t*) 0x4049174CUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_10_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_10_WORD_0_t*) 0x40491750UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_10_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_10_WORD_1_t*) 0x40491754UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_11_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_11_WORD_0_t*) 0x40491758UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_11_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_11_WORD_1_t*) 0x4049175CUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_12_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_12_WORD_0_t*) 0x40491760UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_12_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_12_WORD_1_t*) 0x40491764UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_13_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_13_WORD_0_t*) 0x40491768UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_13_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_13_WORD_1_t*) 0x4049176CUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_14_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_14_WORD_0_t*) 0x40491770UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_14_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_14_WORD_1_t*) 0x40491774UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_15_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_15_WORD_0_t*) 0x40491778UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_15_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_15_WORD_1_t*) 0x4049177CUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_16_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_16_WORD_0_t*) 0x40491780UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_16_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_16_WORD_1_t*) 0x40491784UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_17_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_17_WORD_0_t*) 0x40491788UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_17_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_17_WORD_1_t*) 0x4049178CUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_18_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_18_WORD_0_t*) 0x40491790UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_18_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_18_WORD_1_t*) 0x40491794UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_19_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_19_WORD_0_t*) 0x40491798UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_19_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_19_WORD_1_t*) 0x4049179CUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_20_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_20_WORD_0_t*) 0x404917A0UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_20_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_20_WORD_1_t*) 0x404917A4UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_21_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_21_WORD_0_t*) 0x404917A8UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_21_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_21_WORD_1_t*) 0x404917ACUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_22_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_22_WORD_0_t*) 0x404917B0UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_22_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_22_WORD_1_t*) 0x404917B4UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_23_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_23_WORD_0_t*) 0x404917B8UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_23_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_23_WORD_1_t*) 0x404917BCUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_24_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_24_WORD_0_t*) 0x404917C0UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_24_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_24_WORD_1_t*) 0x404917C4UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_25_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_25_WORD_0_t*) 0x404917C8UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_25_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_25_WORD_1_t*) 0x404917CCUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_26_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_26_WORD_0_t*) 0x404917D0UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_26_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_26_WORD_1_t*) 0x404917D4UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_27_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_27_WORD_0_t*) 0x404917D8UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_27_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_27_WORD_1_t*) 0x404917DCUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_28_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_28_WORD_0_t*) 0x404917E0UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_28_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_28_WORD_1_t*) 0x404917E4UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_29_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_29_WORD_0_t*) 0x404917E8UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_29_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_29_WORD_1_t*) 0x404917ECUL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_30_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_30_WORD_0_t*) 0x404917F0UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_30_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_30_WORD_1_t*) 0x404917F4UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_31_WORD_0 ((volatile un_ETH_TYPE2_COMPARE_31_WORD_0_t*) 0x404917F8UL)
|
||||
#define CYREG_ETH1_TYPE2_COMPARE_31_WORD_1 ((volatile un_ETH_TYPE2_COMPARE_31_WORD_1_t*) 0x404917FCUL)
|
||||
|
||||
#endif /* _CYREG_ETH_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,159 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_evtgen.h
|
||||
*
|
||||
* \brief
|
||||
* EVTGEN register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_EVTGEN_H_
|
||||
#define _CYREG_EVTGEN_H_
|
||||
|
||||
#include "cyip_evtgen.h"
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT0)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT0_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F0800UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT0_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F0804UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT0_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F0808UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT1)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT1_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F0820UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT1_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F0824UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT1_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F0828UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT2)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT2_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F0840UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT2_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F0844UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT2_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F0848UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT3)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT3_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F0860UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT3_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F0864UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT3_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F0868UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT4)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT4_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F0880UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT4_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F0884UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT4_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F0888UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT5)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT5_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F08A0UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT5_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F08A4UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT5_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F08A8UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT6)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT6_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F08C0UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT6_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F08C4UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT6_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F08C8UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT7)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT7_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F08E0UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT7_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F08E4UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT7_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F08E8UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT8)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT8_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F0900UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT8_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F0904UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT8_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F0908UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT9)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT9_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F0920UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT9_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F0924UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT9_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F0928UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT10)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT10_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F0940UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT10_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F0944UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT10_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F0948UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT11)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT11_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F0960UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT11_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F0964UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT11_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F0968UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT12)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT12_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F0980UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT12_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F0984UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT12_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F0988UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT13)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT13_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F09A0UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT13_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F09A4UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT13_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F09A8UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT14)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT14_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F09C0UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT14_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F09C4UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT14_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F09C8UL)
|
||||
|
||||
/**
|
||||
* \brief Comparator structure (EVTGEN_COMP_STRUCT15)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT15_COMP_CTL ((volatile un_EVTGEN_COMP_STRUCT_COMP_CTL_t*) 0x403F09E0UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT15_COMP0 ((volatile un_EVTGEN_COMP_STRUCT_COMP0_t*) 0x403F09E4UL)
|
||||
#define CYREG_EVTGEN0_COMP_STRUCT15_COMP1 ((volatile un_EVTGEN_COMP_STRUCT_COMP1_t*) 0x403F09E8UL)
|
||||
|
||||
/**
|
||||
* \brief Event generator (EVTGEN0)
|
||||
*/
|
||||
#define CYREG_EVTGEN0_CTL ((volatile un_EVTGEN_CTL_t*) 0x403F0000UL)
|
||||
#define CYREG_EVTGEN0_COMP0_STATUS ((volatile un_EVTGEN_COMP0_STATUS_t*) 0x403F0004UL)
|
||||
#define CYREG_EVTGEN0_COMP1_STATUS ((volatile un_EVTGEN_COMP1_STATUS_t*) 0x403F0008UL)
|
||||
#define CYREG_EVTGEN0_COUNTER_STATUS ((volatile un_EVTGEN_COUNTER_STATUS_t*) 0x403F0010UL)
|
||||
#define CYREG_EVTGEN0_COUNTER ((volatile un_EVTGEN_COUNTER_t*) 0x403F0014UL)
|
||||
#define CYREG_EVTGEN0_RATIO_CTL ((volatile un_EVTGEN_RATIO_CTL_t*) 0x403F0020UL)
|
||||
#define CYREG_EVTGEN0_RATIO ((volatile un_EVTGEN_RATIO_t*) 0x403F0024UL)
|
||||
#define CYREG_EVTGEN0_REF_CLOCK_CTL ((volatile un_EVTGEN_REF_CLOCK_CTL_t*) 0x403F0030UL)
|
||||
#define CYREG_EVTGEN0_INTR ((volatile un_EVTGEN_INTR_t*) 0x403F0700UL)
|
||||
#define CYREG_EVTGEN0_INTR_SET ((volatile un_EVTGEN_INTR_SET_t*) 0x403F0704UL)
|
||||
#define CYREG_EVTGEN0_INTR_MASK ((volatile un_EVTGEN_INTR_MASK_t*) 0x403F0708UL)
|
||||
#define CYREG_EVTGEN0_INTR_MASKED ((volatile un_EVTGEN_INTR_MASKED_t*) 0x403F070CUL)
|
||||
#define CYREG_EVTGEN0_INTR_DPSLP ((volatile un_EVTGEN_INTR_DPSLP_t*) 0x403F0710UL)
|
||||
#define CYREG_EVTGEN0_INTR_DPSLP_SET ((volatile un_EVTGEN_INTR_DPSLP_SET_t*) 0x403F0714UL)
|
||||
#define CYREG_EVTGEN0_INTR_DPSLP_MASK ((volatile un_EVTGEN_INTR_DPSLP_MASK_t*) 0x403F0718UL)
|
||||
#define CYREG_EVTGEN0_INTR_DPSLP_MASKED ((volatile un_EVTGEN_INTR_DPSLP_MASKED_t*) 0x403F071CUL)
|
||||
|
||||
#endif /* _CYREG_EVTGEN_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,107 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_fault.h
|
||||
*
|
||||
* \brief
|
||||
* FAULT register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_FAULT_H_
|
||||
#define _CYREG_FAULT_H_
|
||||
|
||||
#include "cyip_fault.h"
|
||||
|
||||
/**
|
||||
* \brief Fault structure (FAULT_STRUCT0)
|
||||
*/
|
||||
#define CYREG_FAULT_STRUCT0_CTL ((volatile un_FAULT_STRUCT_CTL_t*) 0x40210000UL)
|
||||
#define CYREG_FAULT_STRUCT0_STATUS ((volatile un_FAULT_STRUCT_STATUS_t*) 0x4021000CUL)
|
||||
#define CYREG_FAULT_STRUCT0_DATA0 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210010UL)
|
||||
#define CYREG_FAULT_STRUCT0_DATA1 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210014UL)
|
||||
#define CYREG_FAULT_STRUCT0_DATA2 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210018UL)
|
||||
#define CYREG_FAULT_STRUCT0_DATA3 ((volatile un_FAULT_STRUCT_DATA_t*) 0x4021001CUL)
|
||||
#define CYREG_FAULT_STRUCT0_PENDING0 ((volatile un_FAULT_STRUCT_PENDING0_t*) 0x40210040UL)
|
||||
#define CYREG_FAULT_STRUCT0_PENDING1 ((volatile un_FAULT_STRUCT_PENDING1_t*) 0x40210044UL)
|
||||
#define CYREG_FAULT_STRUCT0_PENDING2 ((volatile un_FAULT_STRUCT_PENDING2_t*) 0x40210048UL)
|
||||
#define CYREG_FAULT_STRUCT0_MASK0 ((volatile un_FAULT_STRUCT_MASK0_t*) 0x40210050UL)
|
||||
#define CYREG_FAULT_STRUCT0_MASK1 ((volatile un_FAULT_STRUCT_MASK1_t*) 0x40210054UL)
|
||||
#define CYREG_FAULT_STRUCT0_MASK2 ((volatile un_FAULT_STRUCT_MASK2_t*) 0x40210058UL)
|
||||
#define CYREG_FAULT_STRUCT0_INTR ((volatile un_FAULT_STRUCT_INTR_t*) 0x402100C0UL)
|
||||
#define CYREG_FAULT_STRUCT0_INTR_SET ((volatile un_FAULT_STRUCT_INTR_SET_t*) 0x402100C4UL)
|
||||
#define CYREG_FAULT_STRUCT0_INTR_MASK ((volatile un_FAULT_STRUCT_INTR_MASK_t*) 0x402100C8UL)
|
||||
#define CYREG_FAULT_STRUCT0_INTR_MASKED ((volatile un_FAULT_STRUCT_INTR_MASKED_t*) 0x402100CCUL)
|
||||
|
||||
/**
|
||||
* \brief Fault structure (FAULT_STRUCT1)
|
||||
*/
|
||||
#define CYREG_FAULT_STRUCT1_CTL ((volatile un_FAULT_STRUCT_CTL_t*) 0x40210100UL)
|
||||
#define CYREG_FAULT_STRUCT1_STATUS ((volatile un_FAULT_STRUCT_STATUS_t*) 0x4021010CUL)
|
||||
#define CYREG_FAULT_STRUCT1_DATA0 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210110UL)
|
||||
#define CYREG_FAULT_STRUCT1_DATA1 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210114UL)
|
||||
#define CYREG_FAULT_STRUCT1_DATA2 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210118UL)
|
||||
#define CYREG_FAULT_STRUCT1_DATA3 ((volatile un_FAULT_STRUCT_DATA_t*) 0x4021011CUL)
|
||||
#define CYREG_FAULT_STRUCT1_PENDING0 ((volatile un_FAULT_STRUCT_PENDING0_t*) 0x40210140UL)
|
||||
#define CYREG_FAULT_STRUCT1_PENDING1 ((volatile un_FAULT_STRUCT_PENDING1_t*) 0x40210144UL)
|
||||
#define CYREG_FAULT_STRUCT1_PENDING2 ((volatile un_FAULT_STRUCT_PENDING2_t*) 0x40210148UL)
|
||||
#define CYREG_FAULT_STRUCT1_MASK0 ((volatile un_FAULT_STRUCT_MASK0_t*) 0x40210150UL)
|
||||
#define CYREG_FAULT_STRUCT1_MASK1 ((volatile un_FAULT_STRUCT_MASK1_t*) 0x40210154UL)
|
||||
#define CYREG_FAULT_STRUCT1_MASK2 ((volatile un_FAULT_STRUCT_MASK2_t*) 0x40210158UL)
|
||||
#define CYREG_FAULT_STRUCT1_INTR ((volatile un_FAULT_STRUCT_INTR_t*) 0x402101C0UL)
|
||||
#define CYREG_FAULT_STRUCT1_INTR_SET ((volatile un_FAULT_STRUCT_INTR_SET_t*) 0x402101C4UL)
|
||||
#define CYREG_FAULT_STRUCT1_INTR_MASK ((volatile un_FAULT_STRUCT_INTR_MASK_t*) 0x402101C8UL)
|
||||
#define CYREG_FAULT_STRUCT1_INTR_MASKED ((volatile un_FAULT_STRUCT_INTR_MASKED_t*) 0x402101CCUL)
|
||||
|
||||
/**
|
||||
* \brief Fault structure (FAULT_STRUCT2)
|
||||
*/
|
||||
#define CYREG_FAULT_STRUCT2_CTL ((volatile un_FAULT_STRUCT_CTL_t*) 0x40210200UL)
|
||||
#define CYREG_FAULT_STRUCT2_STATUS ((volatile un_FAULT_STRUCT_STATUS_t*) 0x4021020CUL)
|
||||
#define CYREG_FAULT_STRUCT2_DATA0 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210210UL)
|
||||
#define CYREG_FAULT_STRUCT2_DATA1 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210214UL)
|
||||
#define CYREG_FAULT_STRUCT2_DATA2 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210218UL)
|
||||
#define CYREG_FAULT_STRUCT2_DATA3 ((volatile un_FAULT_STRUCT_DATA_t*) 0x4021021CUL)
|
||||
#define CYREG_FAULT_STRUCT2_PENDING0 ((volatile un_FAULT_STRUCT_PENDING0_t*) 0x40210240UL)
|
||||
#define CYREG_FAULT_STRUCT2_PENDING1 ((volatile un_FAULT_STRUCT_PENDING1_t*) 0x40210244UL)
|
||||
#define CYREG_FAULT_STRUCT2_PENDING2 ((volatile un_FAULT_STRUCT_PENDING2_t*) 0x40210248UL)
|
||||
#define CYREG_FAULT_STRUCT2_MASK0 ((volatile un_FAULT_STRUCT_MASK0_t*) 0x40210250UL)
|
||||
#define CYREG_FAULT_STRUCT2_MASK1 ((volatile un_FAULT_STRUCT_MASK1_t*) 0x40210254UL)
|
||||
#define CYREG_FAULT_STRUCT2_MASK2 ((volatile un_FAULT_STRUCT_MASK2_t*) 0x40210258UL)
|
||||
#define CYREG_FAULT_STRUCT2_INTR ((volatile un_FAULT_STRUCT_INTR_t*) 0x402102C0UL)
|
||||
#define CYREG_FAULT_STRUCT2_INTR_SET ((volatile un_FAULT_STRUCT_INTR_SET_t*) 0x402102C4UL)
|
||||
#define CYREG_FAULT_STRUCT2_INTR_MASK ((volatile un_FAULT_STRUCT_INTR_MASK_t*) 0x402102C8UL)
|
||||
#define CYREG_FAULT_STRUCT2_INTR_MASKED ((volatile un_FAULT_STRUCT_INTR_MASKED_t*) 0x402102CCUL)
|
||||
|
||||
/**
|
||||
* \brief Fault structure (FAULT_STRUCT3)
|
||||
*/
|
||||
#define CYREG_FAULT_STRUCT3_CTL ((volatile un_FAULT_STRUCT_CTL_t*) 0x40210300UL)
|
||||
#define CYREG_FAULT_STRUCT3_STATUS ((volatile un_FAULT_STRUCT_STATUS_t*) 0x4021030CUL)
|
||||
#define CYREG_FAULT_STRUCT3_DATA0 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210310UL)
|
||||
#define CYREG_FAULT_STRUCT3_DATA1 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210314UL)
|
||||
#define CYREG_FAULT_STRUCT3_DATA2 ((volatile un_FAULT_STRUCT_DATA_t*) 0x40210318UL)
|
||||
#define CYREG_FAULT_STRUCT3_DATA3 ((volatile un_FAULT_STRUCT_DATA_t*) 0x4021031CUL)
|
||||
#define CYREG_FAULT_STRUCT3_PENDING0 ((volatile un_FAULT_STRUCT_PENDING0_t*) 0x40210340UL)
|
||||
#define CYREG_FAULT_STRUCT3_PENDING1 ((volatile un_FAULT_STRUCT_PENDING1_t*) 0x40210344UL)
|
||||
#define CYREG_FAULT_STRUCT3_PENDING2 ((volatile un_FAULT_STRUCT_PENDING2_t*) 0x40210348UL)
|
||||
#define CYREG_FAULT_STRUCT3_MASK0 ((volatile un_FAULT_STRUCT_MASK0_t*) 0x40210350UL)
|
||||
#define CYREG_FAULT_STRUCT3_MASK1 ((volatile un_FAULT_STRUCT_MASK1_t*) 0x40210354UL)
|
||||
#define CYREG_FAULT_STRUCT3_MASK2 ((volatile un_FAULT_STRUCT_MASK2_t*) 0x40210358UL)
|
||||
#define CYREG_FAULT_STRUCT3_INTR ((volatile un_FAULT_STRUCT_INTR_t*) 0x402103C0UL)
|
||||
#define CYREG_FAULT_STRUCT3_INTR_SET ((volatile un_FAULT_STRUCT_INTR_SET_t*) 0x402103C4UL)
|
||||
#define CYREG_FAULT_STRUCT3_INTR_MASK ((volatile un_FAULT_STRUCT_INTR_MASK_t*) 0x402103C8UL)
|
||||
#define CYREG_FAULT_STRUCT3_INTR_MASKED ((volatile un_FAULT_STRUCT_INTR_MASKED_t*) 0x402103CCUL)
|
||||
|
||||
#endif /* _CYREG_FAULT_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,71 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_flashc.h
|
||||
*
|
||||
* \brief
|
||||
* FLASHC register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_FLASHC_H_
|
||||
#define _CYREG_FLASHC_H_
|
||||
|
||||
#include "cyip_flashc.h"
|
||||
|
||||
/**
|
||||
* \brief Flash Macro Registers (FLASHC_FM_CTL_ECT0)
|
||||
*/
|
||||
#define CYREG_FLASHC_FM_CTL ((volatile un_FLASHC_FM_CTL_t*) 0x4024F000UL)
|
||||
#define CYREG_FLASHC_FM_CODE_MARGIN ((volatile un_FLASHC_FM_CODE_MARGIN_t*) 0x4024F004UL)
|
||||
#define CYREG_FLASHC_FM_ADDR ((volatile un_FLASHC_FM_ADDR_t*) 0x4024F008UL)
|
||||
#define CYREG_FLASHC_GEOMTRY ((volatile un_FLASHC_GEOMTRY_t*) 0x4024F00CUL)
|
||||
#define CYREG_FLASHC_INTR ((volatile un_FLASHC_INTR_t*) 0x4024F020UL)
|
||||
#define CYREG_FLASHC_INTR_SET ((volatile un_FLASHC_INTR_SET_t*) 0x4024F024UL)
|
||||
#define CYREG_FLASHC_INTR_MASK ((volatile un_FLASHC_INTR_MASK_t*) 0x4024F028UL)
|
||||
#define CYREG_FLASHC_INTR_MASKED ((volatile un_FLASHC_INTR_MASKED_t*) 0x4024F02CUL)
|
||||
#define CYREG_FLASHC_ECC_OVERRIDE ((volatile un_FLASHC_ECC_OVERRIDE_t*) 0x4024F030UL)
|
||||
#define CYREG_FLASHC_FM_DATA ((volatile un_FLASHC_FM_DATA_t*) 0x4024F040UL)
|
||||
#define CYREG_FLASHC_BOOKMARK ((volatile un_FLASHC_BOOKMARK_t*) 0x4024F064UL)
|
||||
#define CYREG_FLASHC_MAIN_FLASH_SAFETY ((volatile un_FLASHC_MAIN_FLASH_SAFETY_t*) 0x4024F400UL)
|
||||
#define CYREG_FLASHC_STATUS ((volatile un_FLASHC_STATUS_t*) 0x4024F404UL)
|
||||
#define CYREG_FLASHC_WORK_FLASH_SAFETY ((volatile un_FLASHC_WORK_FLASH_SAFETY_t*) 0x4024F500UL)
|
||||
|
||||
/**
|
||||
* \brief Flash controller (FLASHC0)
|
||||
*/
|
||||
#define CYREG_FLASHC_FLASH_CTL ((volatile un_FLASHC_FLASH_CTL_t*) 0x40240000UL)
|
||||
#define CYREG_FLASHC_FLASH_PWR_CTL ((volatile un_FLASHC_FLASH_PWR_CTL_t*) 0x40240004UL)
|
||||
#define CYREG_FLASHC_FLASH_CMD ((volatile un_FLASHC_FLASH_CMD_t*) 0x40240008UL)
|
||||
#define CYREG_FLASHC_ECC_CTL ((volatile un_FLASHC_ECC_CTL_t*) 0x402402A0UL)
|
||||
#define CYREG_FLASHC_FM_SRAM_ECC_CTL0 ((volatile un_FLASHC_FM_SRAM_ECC_CTL0_t*) 0x402402B0UL)
|
||||
#define CYREG_FLASHC_FM_SRAM_ECC_CTL1 ((volatile un_FLASHC_FM_SRAM_ECC_CTL1_t*) 0x402402B4UL)
|
||||
#define CYREG_FLASHC_FM_SRAM_ECC_CTL2 ((volatile un_FLASHC_FM_SRAM_ECC_CTL2_t*) 0x402402B8UL)
|
||||
#define CYREG_FLASHC_FM_SRAM_ECC_CTL3 ((volatile un_FLASHC_FM_SRAM_ECC_CTL3_t*) 0x402402BCUL)
|
||||
#define CYREG_FLASHC_CM0_CA_CTL0 ((volatile un_FLASHC_CM0_CA_CTL0_t*) 0x40240400UL)
|
||||
#define CYREG_FLASHC_CM0_CA_CTL1 ((volatile un_FLASHC_CM0_CA_CTL1_t*) 0x40240404UL)
|
||||
#define CYREG_FLASHC_CM0_CA_CTL2 ((volatile un_FLASHC_CM0_CA_CTL2_t*) 0x40240408UL)
|
||||
#define CYREG_FLASHC_CM0_CA_STATUS0 ((volatile un_FLASHC_CM0_CA_STATUS0_t*) 0x40240440UL)
|
||||
#define CYREG_FLASHC_CM0_CA_STATUS1 ((volatile un_FLASHC_CM0_CA_STATUS1_t*) 0x40240444UL)
|
||||
#define CYREG_FLASHC_CM0_CA_STATUS2 ((volatile un_FLASHC_CM0_CA_STATUS2_t*) 0x40240448UL)
|
||||
#define CYREG_FLASHC_CM0_STATUS ((volatile un_FLASHC_CM0_STATUS_t*) 0x40240460UL)
|
||||
#define CYREG_FLASHC_CM7_0_STATUS ((volatile un_FLASHC_CM7_0_STATUS_t*) 0x402404E0UL)
|
||||
#define CYREG_FLASHC_CM7_1_STATUS ((volatile un_FLASHC_CM7_1_STATUS_t*) 0x40240560UL)
|
||||
#define CYREG_FLASHC_CRYPTO_BUFF_CTL ((volatile un_FLASHC_CRYPTO_BUFF_CTL_t*) 0x40240580UL)
|
||||
#define CYREG_FLASHC_DW0_BUFF_CTL ((volatile un_FLASHC_DW0_BUFF_CTL_t*) 0x40240600UL)
|
||||
#define CYREG_FLASHC_DW1_BUFF_CTL ((volatile un_FLASHC_DW1_BUFF_CTL_t*) 0x40240680UL)
|
||||
#define CYREG_FLASHC_DMAC_BUFF_CTL ((volatile un_FLASHC_DMAC_BUFF_CTL_t*) 0x40240700UL)
|
||||
#define CYREG_FLASHC_SLOW0_MS_BUFF_CTL ((volatile un_FLASHC_SLOW0_MS_BUFF_CTL_t*) 0x40240780UL)
|
||||
|
||||
#endif /* _CYREG_FLASHC_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,416 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_flexray.h
|
||||
*
|
||||
* \brief
|
||||
* FLEXRAY register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_FLEXRAY_H_
|
||||
#define _CYREG_FLEXRAY_H_
|
||||
|
||||
#include "cyip_flexray.h"
|
||||
|
||||
/**
|
||||
* \brief FlexRay Bus Interface (FLEXRAY)
|
||||
*/
|
||||
#define CYREG_FLEXRAY0_CTL ((volatile un_FLEXRAY_CTL_t*) 0x40560000UL)
|
||||
#define CYREG_FLEXRAY0_DMA_CTL ((volatile un_FLEXRAY_DMA_CTL_t*) 0x40560004UL)
|
||||
#define CYREG_FLEXRAY0_TEST1 ((volatile un_FLEXRAY_TEST1_t*) 0x40560010UL)
|
||||
#define CYREG_FLEXRAY0_TEST2 ((volatile un_FLEXRAY_TEST2_t*) 0x40560014UL)
|
||||
#define CYREG_FLEXRAY0_LCK ((volatile un_FLEXRAY_LCK_t*) 0x4056001CUL)
|
||||
#define CYREG_FLEXRAY0_EIR ((volatile un_FLEXRAY_EIR_t*) 0x40560020UL)
|
||||
#define CYREG_FLEXRAY0_SIR ((volatile un_FLEXRAY_SIR_t*) 0x40560024UL)
|
||||
#define CYREG_FLEXRAY0_EILS ((volatile un_FLEXRAY_EILS_t*) 0x40560028UL)
|
||||
#define CYREG_FLEXRAY0_SILS ((volatile un_FLEXRAY_SILS_t*) 0x4056002CUL)
|
||||
#define CYREG_FLEXRAY0_EIES ((volatile un_FLEXRAY_EIES_t*) 0x40560030UL)
|
||||
#define CYREG_FLEXRAY0_EIER ((volatile un_FLEXRAY_EIER_t*) 0x40560034UL)
|
||||
#define CYREG_FLEXRAY0_SIES ((volatile un_FLEXRAY_SIES_t*) 0x40560038UL)
|
||||
#define CYREG_FLEXRAY0_SIER ((volatile un_FLEXRAY_SIER_t*) 0x4056003CUL)
|
||||
#define CYREG_FLEXRAY0_ILE ((volatile un_FLEXRAY_ILE_t*) 0x40560040UL)
|
||||
#define CYREG_FLEXRAY0_T0C ((volatile un_FLEXRAY_T0C_t*) 0x40560044UL)
|
||||
#define CYREG_FLEXRAY0_T1C ((volatile un_FLEXRAY_T1C_t*) 0x40560048UL)
|
||||
#define CYREG_FLEXRAY0_STPW1 ((volatile un_FLEXRAY_STPW1_t*) 0x4056004CUL)
|
||||
#define CYREG_FLEXRAY0_STPW2 ((volatile un_FLEXRAY_STPW2_t*) 0x40560050UL)
|
||||
#define CYREG_FLEXRAY0_SUCC1 ((volatile un_FLEXRAY_SUCC1_t*) 0x40560080UL)
|
||||
#define CYREG_FLEXRAY0_SUCC2 ((volatile un_FLEXRAY_SUCC2_t*) 0x40560084UL)
|
||||
#define CYREG_FLEXRAY0_SUCC3 ((volatile un_FLEXRAY_SUCC3_t*) 0x40560088UL)
|
||||
#define CYREG_FLEXRAY0_NEMC ((volatile un_FLEXRAY_NEMC_t*) 0x4056008CUL)
|
||||
#define CYREG_FLEXRAY0_PRTC1 ((volatile un_FLEXRAY_PRTC1_t*) 0x40560090UL)
|
||||
#define CYREG_FLEXRAY0_PRTC2 ((volatile un_FLEXRAY_PRTC2_t*) 0x40560094UL)
|
||||
#define CYREG_FLEXRAY0_MHDC ((volatile un_FLEXRAY_MHDC_t*) 0x40560098UL)
|
||||
#define CYREG_FLEXRAY0_GTUC1 ((volatile un_FLEXRAY_GTUC1_t*) 0x405600A0UL)
|
||||
#define CYREG_FLEXRAY0_GTUC2 ((volatile un_FLEXRAY_GTUC2_t*) 0x405600A4UL)
|
||||
#define CYREG_FLEXRAY0_GTUC3 ((volatile un_FLEXRAY_GTUC3_t*) 0x405600A8UL)
|
||||
#define CYREG_FLEXRAY0_GTUC4 ((volatile un_FLEXRAY_GTUC4_t*) 0x405600ACUL)
|
||||
#define CYREG_FLEXRAY0_GTUC5 ((volatile un_FLEXRAY_GTUC5_t*) 0x405600B0UL)
|
||||
#define CYREG_FLEXRAY0_GTUC6 ((volatile un_FLEXRAY_GTUC6_t*) 0x405600B4UL)
|
||||
#define CYREG_FLEXRAY0_GTUC7 ((volatile un_FLEXRAY_GTUC7_t*) 0x405600B8UL)
|
||||
#define CYREG_FLEXRAY0_GTUC8 ((volatile un_FLEXRAY_GTUC8_t*) 0x405600BCUL)
|
||||
#define CYREG_FLEXRAY0_GTUC9 ((volatile un_FLEXRAY_GTUC9_t*) 0x405600C0UL)
|
||||
#define CYREG_FLEXRAY0_GTUC10 ((volatile un_FLEXRAY_GTUC10_t*) 0x405600C4UL)
|
||||
#define CYREG_FLEXRAY0_GTUC11 ((volatile un_FLEXRAY_GTUC11_t*) 0x405600C8UL)
|
||||
#define CYREG_FLEXRAY0_CCSV ((volatile un_FLEXRAY_CCSV_t*) 0x40560100UL)
|
||||
#define CYREG_FLEXRAY0_CCEV ((volatile un_FLEXRAY_CCEV_t*) 0x40560104UL)
|
||||
#define CYREG_FLEXRAY0_SCV ((volatile un_FLEXRAY_SCV_t*) 0x40560110UL)
|
||||
#define CYREG_FLEXRAY0_MTCCV ((volatile un_FLEXRAY_MTCCV_t*) 0x40560114UL)
|
||||
#define CYREG_FLEXRAY0_RCV ((volatile un_FLEXRAY_RCV_t*) 0x40560118UL)
|
||||
#define CYREG_FLEXRAY0_OCV ((volatile un_FLEXRAY_OCV_t*) 0x4056011CUL)
|
||||
#define CYREG_FLEXRAY0_SFS ((volatile un_FLEXRAY_SFS_t*) 0x40560120UL)
|
||||
#define CYREG_FLEXRAY0_SWNIT ((volatile un_FLEXRAY_SWNIT_t*) 0x40560124UL)
|
||||
#define CYREG_FLEXRAY0_ACS ((volatile un_FLEXRAY_ACS_t*) 0x40560128UL)
|
||||
#define CYREG_FLEXRAY0_ESID0 ((volatile un_FLEXRAY_ESID_t*) 0x40560130UL)
|
||||
#define CYREG_FLEXRAY0_ESID1 ((volatile un_FLEXRAY_ESID_t*) 0x40560134UL)
|
||||
#define CYREG_FLEXRAY0_ESID2 ((volatile un_FLEXRAY_ESID_t*) 0x40560138UL)
|
||||
#define CYREG_FLEXRAY0_ESID3 ((volatile un_FLEXRAY_ESID_t*) 0x4056013CUL)
|
||||
#define CYREG_FLEXRAY0_ESID4 ((volatile un_FLEXRAY_ESID_t*) 0x40560140UL)
|
||||
#define CYREG_FLEXRAY0_ESID5 ((volatile un_FLEXRAY_ESID_t*) 0x40560144UL)
|
||||
#define CYREG_FLEXRAY0_ESID6 ((volatile un_FLEXRAY_ESID_t*) 0x40560148UL)
|
||||
#define CYREG_FLEXRAY0_ESID7 ((volatile un_FLEXRAY_ESID_t*) 0x4056014CUL)
|
||||
#define CYREG_FLEXRAY0_ESID8 ((volatile un_FLEXRAY_ESID_t*) 0x40560150UL)
|
||||
#define CYREG_FLEXRAY0_ESID9 ((volatile un_FLEXRAY_ESID_t*) 0x40560154UL)
|
||||
#define CYREG_FLEXRAY0_ESID10 ((volatile un_FLEXRAY_ESID_t*) 0x40560158UL)
|
||||
#define CYREG_FLEXRAY0_ESID11 ((volatile un_FLEXRAY_ESID_t*) 0x4056015CUL)
|
||||
#define CYREG_FLEXRAY0_ESID12 ((volatile un_FLEXRAY_ESID_t*) 0x40560160UL)
|
||||
#define CYREG_FLEXRAY0_ESID13 ((volatile un_FLEXRAY_ESID_t*) 0x40560164UL)
|
||||
#define CYREG_FLEXRAY0_ESID14 ((volatile un_FLEXRAY_ESID_t*) 0x40560168UL)
|
||||
#define CYREG_FLEXRAY0_OSID0 ((volatile un_FLEXRAY_OSID_t*) 0x40560170UL)
|
||||
#define CYREG_FLEXRAY0_OSID1 ((volatile un_FLEXRAY_OSID_t*) 0x40560174UL)
|
||||
#define CYREG_FLEXRAY0_OSID2 ((volatile un_FLEXRAY_OSID_t*) 0x40560178UL)
|
||||
#define CYREG_FLEXRAY0_OSID3 ((volatile un_FLEXRAY_OSID_t*) 0x4056017CUL)
|
||||
#define CYREG_FLEXRAY0_OSID4 ((volatile un_FLEXRAY_OSID_t*) 0x40560180UL)
|
||||
#define CYREG_FLEXRAY0_OSID5 ((volatile un_FLEXRAY_OSID_t*) 0x40560184UL)
|
||||
#define CYREG_FLEXRAY0_OSID6 ((volatile un_FLEXRAY_OSID_t*) 0x40560188UL)
|
||||
#define CYREG_FLEXRAY0_OSID7 ((volatile un_FLEXRAY_OSID_t*) 0x4056018CUL)
|
||||
#define CYREG_FLEXRAY0_OSID8 ((volatile un_FLEXRAY_OSID_t*) 0x40560190UL)
|
||||
#define CYREG_FLEXRAY0_OSID9 ((volatile un_FLEXRAY_OSID_t*) 0x40560194UL)
|
||||
#define CYREG_FLEXRAY0_OSID10 ((volatile un_FLEXRAY_OSID_t*) 0x40560198UL)
|
||||
#define CYREG_FLEXRAY0_OSID11 ((volatile un_FLEXRAY_OSID_t*) 0x4056019CUL)
|
||||
#define CYREG_FLEXRAY0_OSID12 ((volatile un_FLEXRAY_OSID_t*) 0x405601A0UL)
|
||||
#define CYREG_FLEXRAY0_OSID13 ((volatile un_FLEXRAY_OSID_t*) 0x405601A4UL)
|
||||
#define CYREG_FLEXRAY0_OSID14 ((volatile un_FLEXRAY_OSID_t*) 0x405601A8UL)
|
||||
#define CYREG_FLEXRAY0_NMV1 ((volatile un_FLEXRAY_NMV1_t*) 0x405601B0UL)
|
||||
#define CYREG_FLEXRAY0_NMV2 ((volatile un_FLEXRAY_NMV2_t*) 0x405601B4UL)
|
||||
#define CYREG_FLEXRAY0_NMV3 ((volatile un_FLEXRAY_NMV3_t*) 0x405601B8UL)
|
||||
#define CYREG_FLEXRAY0_MRC ((volatile un_FLEXRAY_MRC_t*) 0x40560300UL)
|
||||
#define CYREG_FLEXRAY0_FRF ((volatile un_FLEXRAY_FRF_t*) 0x40560304UL)
|
||||
#define CYREG_FLEXRAY0_FRFM ((volatile un_FLEXRAY_FRFM_t*) 0x40560308UL)
|
||||
#define CYREG_FLEXRAY0_FCL ((volatile un_FLEXRAY_FCL_t*) 0x4056030CUL)
|
||||
#define CYREG_FLEXRAY0_MHDS ((volatile un_FLEXRAY_MHDS_t*) 0x40560310UL)
|
||||
#define CYREG_FLEXRAY0_LDTS ((volatile un_FLEXRAY_LDTS_t*) 0x40560314UL)
|
||||
#define CYREG_FLEXRAY0_FSR ((volatile un_FLEXRAY_FSR_t*) 0x40560318UL)
|
||||
#define CYREG_FLEXRAY0_MHDF ((volatile un_FLEXRAY_MHDF_t*) 0x4056031CUL)
|
||||
#define CYREG_FLEXRAY0_TXRQ1 ((volatile un_FLEXRAY_TXRQ1_t*) 0x40560320UL)
|
||||
#define CYREG_FLEXRAY0_TXRQ2 ((volatile un_FLEXRAY_TXRQ2_t*) 0x40560324UL)
|
||||
#define CYREG_FLEXRAY0_TXRQ3 ((volatile un_FLEXRAY_TXRQ3_t*) 0x40560328UL)
|
||||
#define CYREG_FLEXRAY0_TXRQ4 ((volatile un_FLEXRAY_TXRQ4_t*) 0x4056032CUL)
|
||||
#define CYREG_FLEXRAY0_NDAT1 ((volatile un_FLEXRAY_NDAT1_t*) 0x40560330UL)
|
||||
#define CYREG_FLEXRAY0_NDAT2 ((volatile un_FLEXRAY_NDAT2_t*) 0x40560334UL)
|
||||
#define CYREG_FLEXRAY0_NDAT3 ((volatile un_FLEXRAY_NDAT3_t*) 0x40560338UL)
|
||||
#define CYREG_FLEXRAY0_NDAT4 ((volatile un_FLEXRAY_NDAT4_t*) 0x4056033CUL)
|
||||
#define CYREG_FLEXRAY0_MBSC1 ((volatile un_FLEXRAY_MBSC1_t*) 0x40560340UL)
|
||||
#define CYREG_FLEXRAY0_MBSC2 ((volatile un_FLEXRAY_MBSC2_t*) 0x40560344UL)
|
||||
#define CYREG_FLEXRAY0_MBSC3 ((volatile un_FLEXRAY_MBSC3_t*) 0x40560348UL)
|
||||
#define CYREG_FLEXRAY0_MBSC4 ((volatile un_FLEXRAY_MBSC4_t*) 0x4056034CUL)
|
||||
#define CYREG_FLEXRAY0_CREL ((volatile un_FLEXRAY_CREL_t*) 0x405603F0UL)
|
||||
#define CYREG_FLEXRAY0_ENDN ((volatile un_FLEXRAY_ENDN_t*) 0x405603F4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS0 ((volatile un_FLEXRAY_WRDS_t*) 0x40560400UL)
|
||||
#define CYREG_FLEXRAY0_WRDS1 ((volatile un_FLEXRAY_WRDS_t*) 0x40560404UL)
|
||||
#define CYREG_FLEXRAY0_WRDS2 ((volatile un_FLEXRAY_WRDS_t*) 0x40560408UL)
|
||||
#define CYREG_FLEXRAY0_WRDS3 ((volatile un_FLEXRAY_WRDS_t*) 0x4056040CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS4 ((volatile un_FLEXRAY_WRDS_t*) 0x40560410UL)
|
||||
#define CYREG_FLEXRAY0_WRDS5 ((volatile un_FLEXRAY_WRDS_t*) 0x40560414UL)
|
||||
#define CYREG_FLEXRAY0_WRDS6 ((volatile un_FLEXRAY_WRDS_t*) 0x40560418UL)
|
||||
#define CYREG_FLEXRAY0_WRDS7 ((volatile un_FLEXRAY_WRDS_t*) 0x4056041CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS8 ((volatile un_FLEXRAY_WRDS_t*) 0x40560420UL)
|
||||
#define CYREG_FLEXRAY0_WRDS9 ((volatile un_FLEXRAY_WRDS_t*) 0x40560424UL)
|
||||
#define CYREG_FLEXRAY0_WRDS10 ((volatile un_FLEXRAY_WRDS_t*) 0x40560428UL)
|
||||
#define CYREG_FLEXRAY0_WRDS11 ((volatile un_FLEXRAY_WRDS_t*) 0x4056042CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS12 ((volatile un_FLEXRAY_WRDS_t*) 0x40560430UL)
|
||||
#define CYREG_FLEXRAY0_WRDS13 ((volatile un_FLEXRAY_WRDS_t*) 0x40560434UL)
|
||||
#define CYREG_FLEXRAY0_WRDS14 ((volatile un_FLEXRAY_WRDS_t*) 0x40560438UL)
|
||||
#define CYREG_FLEXRAY0_WRDS15 ((volatile un_FLEXRAY_WRDS_t*) 0x4056043CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS16 ((volatile un_FLEXRAY_WRDS_t*) 0x40560440UL)
|
||||
#define CYREG_FLEXRAY0_WRDS17 ((volatile un_FLEXRAY_WRDS_t*) 0x40560444UL)
|
||||
#define CYREG_FLEXRAY0_WRDS18 ((volatile un_FLEXRAY_WRDS_t*) 0x40560448UL)
|
||||
#define CYREG_FLEXRAY0_WRDS19 ((volatile un_FLEXRAY_WRDS_t*) 0x4056044CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS20 ((volatile un_FLEXRAY_WRDS_t*) 0x40560450UL)
|
||||
#define CYREG_FLEXRAY0_WRDS21 ((volatile un_FLEXRAY_WRDS_t*) 0x40560454UL)
|
||||
#define CYREG_FLEXRAY0_WRDS22 ((volatile un_FLEXRAY_WRDS_t*) 0x40560458UL)
|
||||
#define CYREG_FLEXRAY0_WRDS23 ((volatile un_FLEXRAY_WRDS_t*) 0x4056045CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS24 ((volatile un_FLEXRAY_WRDS_t*) 0x40560460UL)
|
||||
#define CYREG_FLEXRAY0_WRDS25 ((volatile un_FLEXRAY_WRDS_t*) 0x40560464UL)
|
||||
#define CYREG_FLEXRAY0_WRDS26 ((volatile un_FLEXRAY_WRDS_t*) 0x40560468UL)
|
||||
#define CYREG_FLEXRAY0_WRDS27 ((volatile un_FLEXRAY_WRDS_t*) 0x4056046CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS28 ((volatile un_FLEXRAY_WRDS_t*) 0x40560470UL)
|
||||
#define CYREG_FLEXRAY0_WRDS29 ((volatile un_FLEXRAY_WRDS_t*) 0x40560474UL)
|
||||
#define CYREG_FLEXRAY0_WRDS30 ((volatile un_FLEXRAY_WRDS_t*) 0x40560478UL)
|
||||
#define CYREG_FLEXRAY0_WRDS31 ((volatile un_FLEXRAY_WRDS_t*) 0x4056047CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS32 ((volatile un_FLEXRAY_WRDS_t*) 0x40560480UL)
|
||||
#define CYREG_FLEXRAY0_WRDS33 ((volatile un_FLEXRAY_WRDS_t*) 0x40560484UL)
|
||||
#define CYREG_FLEXRAY0_WRDS34 ((volatile un_FLEXRAY_WRDS_t*) 0x40560488UL)
|
||||
#define CYREG_FLEXRAY0_WRDS35 ((volatile un_FLEXRAY_WRDS_t*) 0x4056048CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS36 ((volatile un_FLEXRAY_WRDS_t*) 0x40560490UL)
|
||||
#define CYREG_FLEXRAY0_WRDS37 ((volatile un_FLEXRAY_WRDS_t*) 0x40560494UL)
|
||||
#define CYREG_FLEXRAY0_WRDS38 ((volatile un_FLEXRAY_WRDS_t*) 0x40560498UL)
|
||||
#define CYREG_FLEXRAY0_WRDS39 ((volatile un_FLEXRAY_WRDS_t*) 0x4056049CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS40 ((volatile un_FLEXRAY_WRDS_t*) 0x405604A0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS41 ((volatile un_FLEXRAY_WRDS_t*) 0x405604A4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS42 ((volatile un_FLEXRAY_WRDS_t*) 0x405604A8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS43 ((volatile un_FLEXRAY_WRDS_t*) 0x405604ACUL)
|
||||
#define CYREG_FLEXRAY0_WRDS44 ((volatile un_FLEXRAY_WRDS_t*) 0x405604B0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS45 ((volatile un_FLEXRAY_WRDS_t*) 0x405604B4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS46 ((volatile un_FLEXRAY_WRDS_t*) 0x405604B8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS47 ((volatile un_FLEXRAY_WRDS_t*) 0x405604BCUL)
|
||||
#define CYREG_FLEXRAY0_WRDS48 ((volatile un_FLEXRAY_WRDS_t*) 0x405604C0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS49 ((volatile un_FLEXRAY_WRDS_t*) 0x405604C4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS50 ((volatile un_FLEXRAY_WRDS_t*) 0x405604C8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS51 ((volatile un_FLEXRAY_WRDS_t*) 0x405604CCUL)
|
||||
#define CYREG_FLEXRAY0_WRDS52 ((volatile un_FLEXRAY_WRDS_t*) 0x405604D0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS53 ((volatile un_FLEXRAY_WRDS_t*) 0x405604D4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS54 ((volatile un_FLEXRAY_WRDS_t*) 0x405604D8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS55 ((volatile un_FLEXRAY_WRDS_t*) 0x405604DCUL)
|
||||
#define CYREG_FLEXRAY0_WRDS56 ((volatile un_FLEXRAY_WRDS_t*) 0x405604E0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS57 ((volatile un_FLEXRAY_WRDS_t*) 0x405604E4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS58 ((volatile un_FLEXRAY_WRDS_t*) 0x405604E8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS59 ((volatile un_FLEXRAY_WRDS_t*) 0x405604ECUL)
|
||||
#define CYREG_FLEXRAY0_WRDS60 ((volatile un_FLEXRAY_WRDS_t*) 0x405604F0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS61 ((volatile un_FLEXRAY_WRDS_t*) 0x405604F4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS62 ((volatile un_FLEXRAY_WRDS_t*) 0x405604F8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS63 ((volatile un_FLEXRAY_WRDS_t*) 0x405604FCUL)
|
||||
#define CYREG_FLEXRAY0_WRHS1 ((volatile un_FLEXRAY_WRHS1_t*) 0x40560500UL)
|
||||
#define CYREG_FLEXRAY0_WRHS2 ((volatile un_FLEXRAY_WRHS2_t*) 0x40560504UL)
|
||||
#define CYREG_FLEXRAY0_WRHS3 ((volatile un_FLEXRAY_WRHS3_t*) 0x40560508UL)
|
||||
#define CYREG_FLEXRAY0_IBCM ((volatile un_FLEXRAY_IBCM_t*) 0x40560510UL)
|
||||
#define CYREG_FLEXRAY0_IBCR ((volatile un_FLEXRAY_IBCR_t*) 0x40560514UL)
|
||||
#define CYREG_FLEXRAY0_RDDS0 ((volatile un_FLEXRAY_RDDS_t*) 0x40560600UL)
|
||||
#define CYREG_FLEXRAY0_RDDS1 ((volatile un_FLEXRAY_RDDS_t*) 0x40560604UL)
|
||||
#define CYREG_FLEXRAY0_RDDS2 ((volatile un_FLEXRAY_RDDS_t*) 0x40560608UL)
|
||||
#define CYREG_FLEXRAY0_RDDS3 ((volatile un_FLEXRAY_RDDS_t*) 0x4056060CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS4 ((volatile un_FLEXRAY_RDDS_t*) 0x40560610UL)
|
||||
#define CYREG_FLEXRAY0_RDDS5 ((volatile un_FLEXRAY_RDDS_t*) 0x40560614UL)
|
||||
#define CYREG_FLEXRAY0_RDDS6 ((volatile un_FLEXRAY_RDDS_t*) 0x40560618UL)
|
||||
#define CYREG_FLEXRAY0_RDDS7 ((volatile un_FLEXRAY_RDDS_t*) 0x4056061CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS8 ((volatile un_FLEXRAY_RDDS_t*) 0x40560620UL)
|
||||
#define CYREG_FLEXRAY0_RDDS9 ((volatile un_FLEXRAY_RDDS_t*) 0x40560624UL)
|
||||
#define CYREG_FLEXRAY0_RDDS10 ((volatile un_FLEXRAY_RDDS_t*) 0x40560628UL)
|
||||
#define CYREG_FLEXRAY0_RDDS11 ((volatile un_FLEXRAY_RDDS_t*) 0x4056062CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS12 ((volatile un_FLEXRAY_RDDS_t*) 0x40560630UL)
|
||||
#define CYREG_FLEXRAY0_RDDS13 ((volatile un_FLEXRAY_RDDS_t*) 0x40560634UL)
|
||||
#define CYREG_FLEXRAY0_RDDS14 ((volatile un_FLEXRAY_RDDS_t*) 0x40560638UL)
|
||||
#define CYREG_FLEXRAY0_RDDS15 ((volatile un_FLEXRAY_RDDS_t*) 0x4056063CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS16 ((volatile un_FLEXRAY_RDDS_t*) 0x40560640UL)
|
||||
#define CYREG_FLEXRAY0_RDDS17 ((volatile un_FLEXRAY_RDDS_t*) 0x40560644UL)
|
||||
#define CYREG_FLEXRAY0_RDDS18 ((volatile un_FLEXRAY_RDDS_t*) 0x40560648UL)
|
||||
#define CYREG_FLEXRAY0_RDDS19 ((volatile un_FLEXRAY_RDDS_t*) 0x4056064CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS20 ((volatile un_FLEXRAY_RDDS_t*) 0x40560650UL)
|
||||
#define CYREG_FLEXRAY0_RDDS21 ((volatile un_FLEXRAY_RDDS_t*) 0x40560654UL)
|
||||
#define CYREG_FLEXRAY0_RDDS22 ((volatile un_FLEXRAY_RDDS_t*) 0x40560658UL)
|
||||
#define CYREG_FLEXRAY0_RDDS23 ((volatile un_FLEXRAY_RDDS_t*) 0x4056065CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS24 ((volatile un_FLEXRAY_RDDS_t*) 0x40560660UL)
|
||||
#define CYREG_FLEXRAY0_RDDS25 ((volatile un_FLEXRAY_RDDS_t*) 0x40560664UL)
|
||||
#define CYREG_FLEXRAY0_RDDS26 ((volatile un_FLEXRAY_RDDS_t*) 0x40560668UL)
|
||||
#define CYREG_FLEXRAY0_RDDS27 ((volatile un_FLEXRAY_RDDS_t*) 0x4056066CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS28 ((volatile un_FLEXRAY_RDDS_t*) 0x40560670UL)
|
||||
#define CYREG_FLEXRAY0_RDDS29 ((volatile un_FLEXRAY_RDDS_t*) 0x40560674UL)
|
||||
#define CYREG_FLEXRAY0_RDDS30 ((volatile un_FLEXRAY_RDDS_t*) 0x40560678UL)
|
||||
#define CYREG_FLEXRAY0_RDDS31 ((volatile un_FLEXRAY_RDDS_t*) 0x4056067CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS32 ((volatile un_FLEXRAY_RDDS_t*) 0x40560680UL)
|
||||
#define CYREG_FLEXRAY0_RDDS33 ((volatile un_FLEXRAY_RDDS_t*) 0x40560684UL)
|
||||
#define CYREG_FLEXRAY0_RDDS34 ((volatile un_FLEXRAY_RDDS_t*) 0x40560688UL)
|
||||
#define CYREG_FLEXRAY0_RDDS35 ((volatile un_FLEXRAY_RDDS_t*) 0x4056068CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS36 ((volatile un_FLEXRAY_RDDS_t*) 0x40560690UL)
|
||||
#define CYREG_FLEXRAY0_RDDS37 ((volatile un_FLEXRAY_RDDS_t*) 0x40560694UL)
|
||||
#define CYREG_FLEXRAY0_RDDS38 ((volatile un_FLEXRAY_RDDS_t*) 0x40560698UL)
|
||||
#define CYREG_FLEXRAY0_RDDS39 ((volatile un_FLEXRAY_RDDS_t*) 0x4056069CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS40 ((volatile un_FLEXRAY_RDDS_t*) 0x405606A0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS41 ((volatile un_FLEXRAY_RDDS_t*) 0x405606A4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS42 ((volatile un_FLEXRAY_RDDS_t*) 0x405606A8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS43 ((volatile un_FLEXRAY_RDDS_t*) 0x405606ACUL)
|
||||
#define CYREG_FLEXRAY0_RDDS44 ((volatile un_FLEXRAY_RDDS_t*) 0x405606B0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS45 ((volatile un_FLEXRAY_RDDS_t*) 0x405606B4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS46 ((volatile un_FLEXRAY_RDDS_t*) 0x405606B8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS47 ((volatile un_FLEXRAY_RDDS_t*) 0x405606BCUL)
|
||||
#define CYREG_FLEXRAY0_RDDS48 ((volatile un_FLEXRAY_RDDS_t*) 0x405606C0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS49 ((volatile un_FLEXRAY_RDDS_t*) 0x405606C4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS50 ((volatile un_FLEXRAY_RDDS_t*) 0x405606C8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS51 ((volatile un_FLEXRAY_RDDS_t*) 0x405606CCUL)
|
||||
#define CYREG_FLEXRAY0_RDDS52 ((volatile un_FLEXRAY_RDDS_t*) 0x405606D0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS53 ((volatile un_FLEXRAY_RDDS_t*) 0x405606D4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS54 ((volatile un_FLEXRAY_RDDS_t*) 0x405606D8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS55 ((volatile un_FLEXRAY_RDDS_t*) 0x405606DCUL)
|
||||
#define CYREG_FLEXRAY0_RDDS56 ((volatile un_FLEXRAY_RDDS_t*) 0x405606E0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS57 ((volatile un_FLEXRAY_RDDS_t*) 0x405606E4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS58 ((volatile un_FLEXRAY_RDDS_t*) 0x405606E8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS59 ((volatile un_FLEXRAY_RDDS_t*) 0x405606ECUL)
|
||||
#define CYREG_FLEXRAY0_RDDS60 ((volatile un_FLEXRAY_RDDS_t*) 0x405606F0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS61 ((volatile un_FLEXRAY_RDDS_t*) 0x405606F4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS62 ((volatile un_FLEXRAY_RDDS_t*) 0x405606F8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS63 ((volatile un_FLEXRAY_RDDS_t*) 0x405606FCUL)
|
||||
#define CYREG_FLEXRAY0_RDHS1 ((volatile un_FLEXRAY_RDHS1_t*) 0x40560700UL)
|
||||
#define CYREG_FLEXRAY0_RDHS2 ((volatile un_FLEXRAY_RDHS2_t*) 0x40560704UL)
|
||||
#define CYREG_FLEXRAY0_RDHS3 ((volatile un_FLEXRAY_RDHS3_t*) 0x40560708UL)
|
||||
#define CYREG_FLEXRAY0_MBS ((volatile un_FLEXRAY_MBS_t*) 0x4056070CUL)
|
||||
#define CYREG_FLEXRAY0_OBCM ((volatile un_FLEXRAY_OBCM_t*) 0x40560710UL)
|
||||
#define CYREG_FLEXRAY0_OBCR ((volatile un_FLEXRAY_OBCR_t*) 0x40560714UL)
|
||||
#define CYREG_FLEXRAY0_WRHS1_MIR2 ((volatile un_FLEXRAY_WRHS1_MIR2_t*) 0x40560BF0UL)
|
||||
#define CYREG_FLEXRAY0_WRHS2_MIR2 ((volatile un_FLEXRAY_WRHS2_MIR2_t*) 0x40560BF4UL)
|
||||
#define CYREG_FLEXRAY0_WRHS3_MIR2 ((volatile un_FLEXRAY_WRHS3_MIR2_t*) 0x40560BF8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR0 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C00UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR1 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C04UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR2 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C08UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR3 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C0CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR4 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C10UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR5 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C14UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR6 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C18UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR7 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C1CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR8 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C20UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR9 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C24UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR10 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C28UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR11 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C2CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR12 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C30UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR13 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C34UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR14 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C38UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR15 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C3CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR16 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C40UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR17 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C44UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR18 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C48UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR19 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C4CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR20 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C50UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR21 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C54UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR22 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C58UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR23 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C5CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR24 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C60UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR25 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C64UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR26 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C68UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR27 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C6CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR28 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C70UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR29 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C74UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR30 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C78UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR31 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C7CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR32 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C80UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR33 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C84UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR34 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C88UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR35 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C8CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR36 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C90UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR37 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C94UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR38 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C98UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR39 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560C9CUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR40 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CA0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR41 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CA4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR42 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CA8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR43 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CACUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR44 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CB0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR45 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CB4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR46 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CB8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR47 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CBCUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR48 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CC0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR49 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CC4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR50 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CC8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR51 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CCCUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR52 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CD0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR53 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CD4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR54 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CD8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR55 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CDCUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR56 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CE0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR57 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CE4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR58 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CE8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR59 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CECUL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR60 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CF0UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR61 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CF4UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR62 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CF8UL)
|
||||
#define CYREG_FLEXRAY0_WRDS_MIR63 ((volatile un_FLEXRAY_WRDS_MIR_t*) 0x40560CFCUL)
|
||||
#define CYREG_FLEXRAY0_WRHS1_MIR ((volatile un_FLEXRAY_WRHS1_MIR_t*) 0x40560D00UL)
|
||||
#define CYREG_FLEXRAY0_WRHS2_MIR ((volatile un_FLEXRAY_WRHS2_MIR_t*) 0x40560D04UL)
|
||||
#define CYREG_FLEXRAY0_WRHS3_MIR ((volatile un_FLEXRAY_WRHS3_MIR_t*) 0x40560D08UL)
|
||||
#define CYREG_FLEXRAY0_IBCM_MIR ((volatile un_FLEXRAY_IBCM_MIR_t*) 0x40560D10UL)
|
||||
#define CYREG_FLEXRAY0_IBCR_MIR ((volatile un_FLEXRAY_IBCR_MIR_t*) 0x40560D14UL)
|
||||
#define CYREG_FLEXRAY0_RDHS1_MIR2 ((volatile un_FLEXRAY_RDHS1_MIR2_t*) 0x40560DF0UL)
|
||||
#define CYREG_FLEXRAY0_RDHS2_MIR2 ((volatile un_FLEXRAY_RDHS2_MIR2_t*) 0x40560DF4UL)
|
||||
#define CYREG_FLEXRAY0_RDHS3_MIR2 ((volatile un_FLEXRAY_RDHS3_MIR2_t*) 0x40560DF8UL)
|
||||
#define CYREG_FLEXRAY0_MBS_MIR2 ((volatile un_FLEXRAY_MBS_MIR2_t*) 0x40560DFCUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR0 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E00UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR1 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E04UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR2 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E08UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR3 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E0CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR4 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E10UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR5 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E14UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR6 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E18UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR7 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E1CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR8 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E20UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR9 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E24UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR10 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E28UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR11 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E2CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR12 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E30UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR13 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E34UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR14 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E38UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR15 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E3CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR16 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E40UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR17 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E44UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR18 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E48UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR19 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E4CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR20 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E50UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR21 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E54UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR22 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E58UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR23 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E5CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR24 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E60UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR25 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E64UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR26 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E68UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR27 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E6CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR28 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E70UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR29 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E74UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR30 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E78UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR31 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E7CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR32 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E80UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR33 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E84UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR34 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E88UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR35 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E8CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR36 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E90UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR37 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E94UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR38 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E98UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR39 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560E9CUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR40 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EA0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR41 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EA4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR42 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EA8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR43 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EACUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR44 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EB0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR45 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EB4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR46 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EB8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR47 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EBCUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR48 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EC0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR49 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EC4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR50 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EC8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR51 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560ECCUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR52 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560ED0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR53 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560ED4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR54 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560ED8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR55 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EDCUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR56 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EE0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR57 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EE4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR58 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EE8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR59 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EECUL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR60 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EF0UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR61 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EF4UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR62 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EF8UL)
|
||||
#define CYREG_FLEXRAY0_RDDS_MIR63 ((volatile un_FLEXRAY_RDDS_MIR_t*) 0x40560EFCUL)
|
||||
#define CYREG_FLEXRAY0_RDHS1_MIR ((volatile un_FLEXRAY_RDHS1_MIR_t*) 0x40560F00UL)
|
||||
#define CYREG_FLEXRAY0_RDHS2_MIR ((volatile un_FLEXRAY_RDHS2_MIR_t*) 0x40560F04UL)
|
||||
#define CYREG_FLEXRAY0_RDHS3_MIR ((volatile un_FLEXRAY_RDHS3_MIR_t*) 0x40560F08UL)
|
||||
#define CYREG_FLEXRAY0_MBS_MIR ((volatile un_FLEXRAY_MBS_MIR_t*) 0x40560F0CUL)
|
||||
#define CYREG_FLEXRAY0_OBCM_MIR ((volatile un_FLEXRAY_OBCM_MIR_t*) 0x40560F10UL)
|
||||
#define CYREG_FLEXRAY0_OBCR_MIR ((volatile un_FLEXRAY_OBCR_MIR_t*) 0x40560F14UL)
|
||||
|
||||
#endif /* _CYREG_FLEXRAY_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,668 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_gpio.h
|
||||
*
|
||||
* \brief
|
||||
* GPIO register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_GPIO_H_
|
||||
#define _CYREG_GPIO_H_
|
||||
|
||||
#include "cyip_gpio_v3.h"
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT0)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT0_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310000UL)
|
||||
#define CYREG_GPIO_PRT0_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310004UL)
|
||||
#define CYREG_GPIO_PRT0_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310008UL)
|
||||
#define CYREG_GPIO_PRT0_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031000CUL)
|
||||
#define CYREG_GPIO_PRT0_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310010UL)
|
||||
#define CYREG_GPIO_PRT0_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310014UL)
|
||||
#define CYREG_GPIO_PRT0_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310018UL)
|
||||
#define CYREG_GPIO_PRT0_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031001CUL)
|
||||
#define CYREG_GPIO_PRT0_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310020UL)
|
||||
#define CYREG_GPIO_PRT0_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310040UL)
|
||||
#define CYREG_GPIO_PRT0_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310044UL)
|
||||
#define CYREG_GPIO_PRT0_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310048UL)
|
||||
#define CYREG_GPIO_PRT0_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031004CUL)
|
||||
#define CYREG_GPIO_PRT0_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310058UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT1)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT1_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310080UL)
|
||||
#define CYREG_GPIO_PRT1_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310084UL)
|
||||
#define CYREG_GPIO_PRT1_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310088UL)
|
||||
#define CYREG_GPIO_PRT1_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031008CUL)
|
||||
#define CYREG_GPIO_PRT1_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310090UL)
|
||||
#define CYREG_GPIO_PRT1_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310094UL)
|
||||
#define CYREG_GPIO_PRT1_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310098UL)
|
||||
#define CYREG_GPIO_PRT1_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031009CUL)
|
||||
#define CYREG_GPIO_PRT1_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403100A0UL)
|
||||
#define CYREG_GPIO_PRT1_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403100C0UL)
|
||||
#define CYREG_GPIO_PRT1_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403100C4UL)
|
||||
#define CYREG_GPIO_PRT1_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403100C8UL)
|
||||
#define CYREG_GPIO_PRT1_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403100CCUL)
|
||||
#define CYREG_GPIO_PRT1_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403100D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT2)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT2_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310100UL)
|
||||
#define CYREG_GPIO_PRT2_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310104UL)
|
||||
#define CYREG_GPIO_PRT2_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310108UL)
|
||||
#define CYREG_GPIO_PRT2_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031010CUL)
|
||||
#define CYREG_GPIO_PRT2_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310110UL)
|
||||
#define CYREG_GPIO_PRT2_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310114UL)
|
||||
#define CYREG_GPIO_PRT2_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310118UL)
|
||||
#define CYREG_GPIO_PRT2_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031011CUL)
|
||||
#define CYREG_GPIO_PRT2_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310120UL)
|
||||
#define CYREG_GPIO_PRT2_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310140UL)
|
||||
#define CYREG_GPIO_PRT2_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310144UL)
|
||||
#define CYREG_GPIO_PRT2_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310148UL)
|
||||
#define CYREG_GPIO_PRT2_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031014CUL)
|
||||
#define CYREG_GPIO_PRT2_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310158UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT3)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT3_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310180UL)
|
||||
#define CYREG_GPIO_PRT3_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310184UL)
|
||||
#define CYREG_GPIO_PRT3_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310188UL)
|
||||
#define CYREG_GPIO_PRT3_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031018CUL)
|
||||
#define CYREG_GPIO_PRT3_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310190UL)
|
||||
#define CYREG_GPIO_PRT3_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310194UL)
|
||||
#define CYREG_GPIO_PRT3_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310198UL)
|
||||
#define CYREG_GPIO_PRT3_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031019CUL)
|
||||
#define CYREG_GPIO_PRT3_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403101A0UL)
|
||||
#define CYREG_GPIO_PRT3_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403101C0UL)
|
||||
#define CYREG_GPIO_PRT3_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403101C4UL)
|
||||
#define CYREG_GPIO_PRT3_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403101C8UL)
|
||||
#define CYREG_GPIO_PRT3_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403101CCUL)
|
||||
#define CYREG_GPIO_PRT3_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403101D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT4)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT4_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310200UL)
|
||||
#define CYREG_GPIO_PRT4_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310204UL)
|
||||
#define CYREG_GPIO_PRT4_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310208UL)
|
||||
#define CYREG_GPIO_PRT4_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031020CUL)
|
||||
#define CYREG_GPIO_PRT4_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310210UL)
|
||||
#define CYREG_GPIO_PRT4_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310214UL)
|
||||
#define CYREG_GPIO_PRT4_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310218UL)
|
||||
#define CYREG_GPIO_PRT4_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031021CUL)
|
||||
#define CYREG_GPIO_PRT4_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310220UL)
|
||||
#define CYREG_GPIO_PRT4_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310240UL)
|
||||
#define CYREG_GPIO_PRT4_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310244UL)
|
||||
#define CYREG_GPIO_PRT4_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310248UL)
|
||||
#define CYREG_GPIO_PRT4_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031024CUL)
|
||||
#define CYREG_GPIO_PRT4_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310258UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT5)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT5_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310280UL)
|
||||
#define CYREG_GPIO_PRT5_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310284UL)
|
||||
#define CYREG_GPIO_PRT5_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310288UL)
|
||||
#define CYREG_GPIO_PRT5_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031028CUL)
|
||||
#define CYREG_GPIO_PRT5_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310290UL)
|
||||
#define CYREG_GPIO_PRT5_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310294UL)
|
||||
#define CYREG_GPIO_PRT5_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310298UL)
|
||||
#define CYREG_GPIO_PRT5_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031029CUL)
|
||||
#define CYREG_GPIO_PRT5_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403102A0UL)
|
||||
#define CYREG_GPIO_PRT5_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403102C0UL)
|
||||
#define CYREG_GPIO_PRT5_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403102C4UL)
|
||||
#define CYREG_GPIO_PRT5_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403102C8UL)
|
||||
#define CYREG_GPIO_PRT5_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403102CCUL)
|
||||
#define CYREG_GPIO_PRT5_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403102D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT6)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT6_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310300UL)
|
||||
#define CYREG_GPIO_PRT6_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310304UL)
|
||||
#define CYREG_GPIO_PRT6_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310308UL)
|
||||
#define CYREG_GPIO_PRT6_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031030CUL)
|
||||
#define CYREG_GPIO_PRT6_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310310UL)
|
||||
#define CYREG_GPIO_PRT6_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310314UL)
|
||||
#define CYREG_GPIO_PRT6_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310318UL)
|
||||
#define CYREG_GPIO_PRT6_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031031CUL)
|
||||
#define CYREG_GPIO_PRT6_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310320UL)
|
||||
#define CYREG_GPIO_PRT6_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310340UL)
|
||||
#define CYREG_GPIO_PRT6_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310344UL)
|
||||
#define CYREG_GPIO_PRT6_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310348UL)
|
||||
#define CYREG_GPIO_PRT6_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031034CUL)
|
||||
#define CYREG_GPIO_PRT6_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310358UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT7)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT7_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310380UL)
|
||||
#define CYREG_GPIO_PRT7_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310384UL)
|
||||
#define CYREG_GPIO_PRT7_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310388UL)
|
||||
#define CYREG_GPIO_PRT7_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031038CUL)
|
||||
#define CYREG_GPIO_PRT7_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310390UL)
|
||||
#define CYREG_GPIO_PRT7_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310394UL)
|
||||
#define CYREG_GPIO_PRT7_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310398UL)
|
||||
#define CYREG_GPIO_PRT7_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031039CUL)
|
||||
#define CYREG_GPIO_PRT7_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403103A0UL)
|
||||
#define CYREG_GPIO_PRT7_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403103C0UL)
|
||||
#define CYREG_GPIO_PRT7_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403103C4UL)
|
||||
#define CYREG_GPIO_PRT7_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403103C8UL)
|
||||
#define CYREG_GPIO_PRT7_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403103CCUL)
|
||||
#define CYREG_GPIO_PRT7_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403103D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT8)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT8_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310400UL)
|
||||
#define CYREG_GPIO_PRT8_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310404UL)
|
||||
#define CYREG_GPIO_PRT8_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310408UL)
|
||||
#define CYREG_GPIO_PRT8_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031040CUL)
|
||||
#define CYREG_GPIO_PRT8_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310410UL)
|
||||
#define CYREG_GPIO_PRT8_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310414UL)
|
||||
#define CYREG_GPIO_PRT8_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310418UL)
|
||||
#define CYREG_GPIO_PRT8_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031041CUL)
|
||||
#define CYREG_GPIO_PRT8_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310420UL)
|
||||
#define CYREG_GPIO_PRT8_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310440UL)
|
||||
#define CYREG_GPIO_PRT8_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310444UL)
|
||||
#define CYREG_GPIO_PRT8_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310448UL)
|
||||
#define CYREG_GPIO_PRT8_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031044CUL)
|
||||
#define CYREG_GPIO_PRT8_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310458UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT9)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT9_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310480UL)
|
||||
#define CYREG_GPIO_PRT9_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310484UL)
|
||||
#define CYREG_GPIO_PRT9_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310488UL)
|
||||
#define CYREG_GPIO_PRT9_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031048CUL)
|
||||
#define CYREG_GPIO_PRT9_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310490UL)
|
||||
#define CYREG_GPIO_PRT9_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310494UL)
|
||||
#define CYREG_GPIO_PRT9_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310498UL)
|
||||
#define CYREG_GPIO_PRT9_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031049CUL)
|
||||
#define CYREG_GPIO_PRT9_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403104A0UL)
|
||||
#define CYREG_GPIO_PRT9_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403104C0UL)
|
||||
#define CYREG_GPIO_PRT9_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403104C4UL)
|
||||
#define CYREG_GPIO_PRT9_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403104C8UL)
|
||||
#define CYREG_GPIO_PRT9_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403104CCUL)
|
||||
#define CYREG_GPIO_PRT9_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403104D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT10)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT10_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310500UL)
|
||||
#define CYREG_GPIO_PRT10_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310504UL)
|
||||
#define CYREG_GPIO_PRT10_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310508UL)
|
||||
#define CYREG_GPIO_PRT10_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031050CUL)
|
||||
#define CYREG_GPIO_PRT10_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310510UL)
|
||||
#define CYREG_GPIO_PRT10_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310514UL)
|
||||
#define CYREG_GPIO_PRT10_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310518UL)
|
||||
#define CYREG_GPIO_PRT10_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031051CUL)
|
||||
#define CYREG_GPIO_PRT10_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310520UL)
|
||||
#define CYREG_GPIO_PRT10_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310540UL)
|
||||
#define CYREG_GPIO_PRT10_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310544UL)
|
||||
#define CYREG_GPIO_PRT10_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310548UL)
|
||||
#define CYREG_GPIO_PRT10_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031054CUL)
|
||||
#define CYREG_GPIO_PRT10_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310558UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT11)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT11_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310580UL)
|
||||
#define CYREG_GPIO_PRT11_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310584UL)
|
||||
#define CYREG_GPIO_PRT11_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310588UL)
|
||||
#define CYREG_GPIO_PRT11_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031058CUL)
|
||||
#define CYREG_GPIO_PRT11_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310590UL)
|
||||
#define CYREG_GPIO_PRT11_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310594UL)
|
||||
#define CYREG_GPIO_PRT11_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310598UL)
|
||||
#define CYREG_GPIO_PRT11_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031059CUL)
|
||||
#define CYREG_GPIO_PRT11_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403105A0UL)
|
||||
#define CYREG_GPIO_PRT11_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403105C0UL)
|
||||
#define CYREG_GPIO_PRT11_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403105C4UL)
|
||||
#define CYREG_GPIO_PRT11_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403105C8UL)
|
||||
#define CYREG_GPIO_PRT11_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403105CCUL)
|
||||
#define CYREG_GPIO_PRT11_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403105D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT12)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT12_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310600UL)
|
||||
#define CYREG_GPIO_PRT12_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310604UL)
|
||||
#define CYREG_GPIO_PRT12_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310608UL)
|
||||
#define CYREG_GPIO_PRT12_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031060CUL)
|
||||
#define CYREG_GPIO_PRT12_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310610UL)
|
||||
#define CYREG_GPIO_PRT12_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310614UL)
|
||||
#define CYREG_GPIO_PRT12_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310618UL)
|
||||
#define CYREG_GPIO_PRT12_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031061CUL)
|
||||
#define CYREG_GPIO_PRT12_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310620UL)
|
||||
#define CYREG_GPIO_PRT12_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310640UL)
|
||||
#define CYREG_GPIO_PRT12_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310644UL)
|
||||
#define CYREG_GPIO_PRT12_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310648UL)
|
||||
#define CYREG_GPIO_PRT12_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031064CUL)
|
||||
#define CYREG_GPIO_PRT12_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310658UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT13)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT13_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310680UL)
|
||||
#define CYREG_GPIO_PRT13_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310684UL)
|
||||
#define CYREG_GPIO_PRT13_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310688UL)
|
||||
#define CYREG_GPIO_PRT13_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031068CUL)
|
||||
#define CYREG_GPIO_PRT13_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310690UL)
|
||||
#define CYREG_GPIO_PRT13_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310694UL)
|
||||
#define CYREG_GPIO_PRT13_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310698UL)
|
||||
#define CYREG_GPIO_PRT13_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031069CUL)
|
||||
#define CYREG_GPIO_PRT13_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403106A0UL)
|
||||
#define CYREG_GPIO_PRT13_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403106C0UL)
|
||||
#define CYREG_GPIO_PRT13_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403106C4UL)
|
||||
#define CYREG_GPIO_PRT13_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403106C8UL)
|
||||
#define CYREG_GPIO_PRT13_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403106CCUL)
|
||||
#define CYREG_GPIO_PRT13_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403106D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT14)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT14_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310700UL)
|
||||
#define CYREG_GPIO_PRT14_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310704UL)
|
||||
#define CYREG_GPIO_PRT14_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310708UL)
|
||||
#define CYREG_GPIO_PRT14_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031070CUL)
|
||||
#define CYREG_GPIO_PRT14_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310710UL)
|
||||
#define CYREG_GPIO_PRT14_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310714UL)
|
||||
#define CYREG_GPIO_PRT14_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310718UL)
|
||||
#define CYREG_GPIO_PRT14_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031071CUL)
|
||||
#define CYREG_GPIO_PRT14_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310720UL)
|
||||
#define CYREG_GPIO_PRT14_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310740UL)
|
||||
#define CYREG_GPIO_PRT14_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310744UL)
|
||||
#define CYREG_GPIO_PRT14_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310748UL)
|
||||
#define CYREG_GPIO_PRT14_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031074CUL)
|
||||
#define CYREG_GPIO_PRT14_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310758UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT15)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT15_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310780UL)
|
||||
#define CYREG_GPIO_PRT15_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310784UL)
|
||||
#define CYREG_GPIO_PRT15_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310788UL)
|
||||
#define CYREG_GPIO_PRT15_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031078CUL)
|
||||
#define CYREG_GPIO_PRT15_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310790UL)
|
||||
#define CYREG_GPIO_PRT15_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310794UL)
|
||||
#define CYREG_GPIO_PRT15_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310798UL)
|
||||
#define CYREG_GPIO_PRT15_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031079CUL)
|
||||
#define CYREG_GPIO_PRT15_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403107A0UL)
|
||||
#define CYREG_GPIO_PRT15_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403107C0UL)
|
||||
#define CYREG_GPIO_PRT15_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403107C4UL)
|
||||
#define CYREG_GPIO_PRT15_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403107C8UL)
|
||||
#define CYREG_GPIO_PRT15_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403107CCUL)
|
||||
#define CYREG_GPIO_PRT15_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403107D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT16)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT16_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310800UL)
|
||||
#define CYREG_GPIO_PRT16_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310804UL)
|
||||
#define CYREG_GPIO_PRT16_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310808UL)
|
||||
#define CYREG_GPIO_PRT16_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031080CUL)
|
||||
#define CYREG_GPIO_PRT16_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310810UL)
|
||||
#define CYREG_GPIO_PRT16_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310814UL)
|
||||
#define CYREG_GPIO_PRT16_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310818UL)
|
||||
#define CYREG_GPIO_PRT16_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031081CUL)
|
||||
#define CYREG_GPIO_PRT16_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310820UL)
|
||||
#define CYREG_GPIO_PRT16_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310840UL)
|
||||
#define CYREG_GPIO_PRT16_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310844UL)
|
||||
#define CYREG_GPIO_PRT16_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310848UL)
|
||||
#define CYREG_GPIO_PRT16_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031084CUL)
|
||||
#define CYREG_GPIO_PRT16_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310858UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT17)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT17_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310880UL)
|
||||
#define CYREG_GPIO_PRT17_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310884UL)
|
||||
#define CYREG_GPIO_PRT17_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310888UL)
|
||||
#define CYREG_GPIO_PRT17_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031088CUL)
|
||||
#define CYREG_GPIO_PRT17_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310890UL)
|
||||
#define CYREG_GPIO_PRT17_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310894UL)
|
||||
#define CYREG_GPIO_PRT17_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310898UL)
|
||||
#define CYREG_GPIO_PRT17_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031089CUL)
|
||||
#define CYREG_GPIO_PRT17_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403108A0UL)
|
||||
#define CYREG_GPIO_PRT17_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403108C0UL)
|
||||
#define CYREG_GPIO_PRT17_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403108C4UL)
|
||||
#define CYREG_GPIO_PRT17_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403108C8UL)
|
||||
#define CYREG_GPIO_PRT17_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403108CCUL)
|
||||
#define CYREG_GPIO_PRT17_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403108D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT18)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT18_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310900UL)
|
||||
#define CYREG_GPIO_PRT18_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310904UL)
|
||||
#define CYREG_GPIO_PRT18_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310908UL)
|
||||
#define CYREG_GPIO_PRT18_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031090CUL)
|
||||
#define CYREG_GPIO_PRT18_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310910UL)
|
||||
#define CYREG_GPIO_PRT18_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310914UL)
|
||||
#define CYREG_GPIO_PRT18_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310918UL)
|
||||
#define CYREG_GPIO_PRT18_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031091CUL)
|
||||
#define CYREG_GPIO_PRT18_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310920UL)
|
||||
#define CYREG_GPIO_PRT18_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310940UL)
|
||||
#define CYREG_GPIO_PRT18_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310944UL)
|
||||
#define CYREG_GPIO_PRT18_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310948UL)
|
||||
#define CYREG_GPIO_PRT18_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031094CUL)
|
||||
#define CYREG_GPIO_PRT18_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310958UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT19)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT19_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310980UL)
|
||||
#define CYREG_GPIO_PRT19_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310984UL)
|
||||
#define CYREG_GPIO_PRT19_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310988UL)
|
||||
#define CYREG_GPIO_PRT19_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031098CUL)
|
||||
#define CYREG_GPIO_PRT19_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310990UL)
|
||||
#define CYREG_GPIO_PRT19_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310994UL)
|
||||
#define CYREG_GPIO_PRT19_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310998UL)
|
||||
#define CYREG_GPIO_PRT19_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031099CUL)
|
||||
#define CYREG_GPIO_PRT19_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403109A0UL)
|
||||
#define CYREG_GPIO_PRT19_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403109C0UL)
|
||||
#define CYREG_GPIO_PRT19_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403109C4UL)
|
||||
#define CYREG_GPIO_PRT19_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403109C8UL)
|
||||
#define CYREG_GPIO_PRT19_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403109CCUL)
|
||||
#define CYREG_GPIO_PRT19_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403109D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT20)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT20_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310A00UL)
|
||||
#define CYREG_GPIO_PRT20_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310A04UL)
|
||||
#define CYREG_GPIO_PRT20_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310A08UL)
|
||||
#define CYREG_GPIO_PRT20_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310A0CUL)
|
||||
#define CYREG_GPIO_PRT20_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310A10UL)
|
||||
#define CYREG_GPIO_PRT20_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310A14UL)
|
||||
#define CYREG_GPIO_PRT20_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310A18UL)
|
||||
#define CYREG_GPIO_PRT20_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310A1CUL)
|
||||
#define CYREG_GPIO_PRT20_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310A20UL)
|
||||
#define CYREG_GPIO_PRT20_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310A40UL)
|
||||
#define CYREG_GPIO_PRT20_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310A44UL)
|
||||
#define CYREG_GPIO_PRT20_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310A48UL)
|
||||
#define CYREG_GPIO_PRT20_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310A4CUL)
|
||||
#define CYREG_GPIO_PRT20_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310A58UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT21)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT21_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310A80UL)
|
||||
#define CYREG_GPIO_PRT21_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310A84UL)
|
||||
#define CYREG_GPIO_PRT21_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310A88UL)
|
||||
#define CYREG_GPIO_PRT21_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310A8CUL)
|
||||
#define CYREG_GPIO_PRT21_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310A90UL)
|
||||
#define CYREG_GPIO_PRT21_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310A94UL)
|
||||
#define CYREG_GPIO_PRT21_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310A98UL)
|
||||
#define CYREG_GPIO_PRT21_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310A9CUL)
|
||||
#define CYREG_GPIO_PRT21_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310AA0UL)
|
||||
#define CYREG_GPIO_PRT21_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310AC0UL)
|
||||
#define CYREG_GPIO_PRT21_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310AC4UL)
|
||||
#define CYREG_GPIO_PRT21_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310AC8UL)
|
||||
#define CYREG_GPIO_PRT21_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310ACCUL)
|
||||
#define CYREG_GPIO_PRT21_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310AD8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT22)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT22_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310B00UL)
|
||||
#define CYREG_GPIO_PRT22_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310B04UL)
|
||||
#define CYREG_GPIO_PRT22_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310B08UL)
|
||||
#define CYREG_GPIO_PRT22_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310B0CUL)
|
||||
#define CYREG_GPIO_PRT22_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310B10UL)
|
||||
#define CYREG_GPIO_PRT22_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310B14UL)
|
||||
#define CYREG_GPIO_PRT22_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310B18UL)
|
||||
#define CYREG_GPIO_PRT22_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310B1CUL)
|
||||
#define CYREG_GPIO_PRT22_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310B20UL)
|
||||
#define CYREG_GPIO_PRT22_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310B40UL)
|
||||
#define CYREG_GPIO_PRT22_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310B44UL)
|
||||
#define CYREG_GPIO_PRT22_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310B48UL)
|
||||
#define CYREG_GPIO_PRT22_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310B4CUL)
|
||||
#define CYREG_GPIO_PRT22_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310B58UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT23)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT23_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310B80UL)
|
||||
#define CYREG_GPIO_PRT23_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310B84UL)
|
||||
#define CYREG_GPIO_PRT23_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310B88UL)
|
||||
#define CYREG_GPIO_PRT23_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310B8CUL)
|
||||
#define CYREG_GPIO_PRT23_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310B90UL)
|
||||
#define CYREG_GPIO_PRT23_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310B94UL)
|
||||
#define CYREG_GPIO_PRT23_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310B98UL)
|
||||
#define CYREG_GPIO_PRT23_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310B9CUL)
|
||||
#define CYREG_GPIO_PRT23_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310BA0UL)
|
||||
#define CYREG_GPIO_PRT23_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310BC0UL)
|
||||
#define CYREG_GPIO_PRT23_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310BC4UL)
|
||||
#define CYREG_GPIO_PRT23_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310BC8UL)
|
||||
#define CYREG_GPIO_PRT23_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310BCCUL)
|
||||
#define CYREG_GPIO_PRT23_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310BD8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT24)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT24_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310C00UL)
|
||||
#define CYREG_GPIO_PRT24_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310C04UL)
|
||||
#define CYREG_GPIO_PRT24_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310C08UL)
|
||||
#define CYREG_GPIO_PRT24_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310C0CUL)
|
||||
#define CYREG_GPIO_PRT24_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310C10UL)
|
||||
#define CYREG_GPIO_PRT24_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310C14UL)
|
||||
#define CYREG_GPIO_PRT24_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310C18UL)
|
||||
#define CYREG_GPIO_PRT24_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310C1CUL)
|
||||
#define CYREG_GPIO_PRT24_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310C20UL)
|
||||
#define CYREG_GPIO_PRT24_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310C40UL)
|
||||
#define CYREG_GPIO_PRT24_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310C44UL)
|
||||
#define CYREG_GPIO_PRT24_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310C48UL)
|
||||
#define CYREG_GPIO_PRT24_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310C4CUL)
|
||||
#define CYREG_GPIO_PRT24_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310C58UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT25)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT25_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310C80UL)
|
||||
#define CYREG_GPIO_PRT25_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310C84UL)
|
||||
#define CYREG_GPIO_PRT25_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310C88UL)
|
||||
#define CYREG_GPIO_PRT25_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310C8CUL)
|
||||
#define CYREG_GPIO_PRT25_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310C90UL)
|
||||
#define CYREG_GPIO_PRT25_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310C94UL)
|
||||
#define CYREG_GPIO_PRT25_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310C98UL)
|
||||
#define CYREG_GPIO_PRT25_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310C9CUL)
|
||||
#define CYREG_GPIO_PRT25_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310CA0UL)
|
||||
#define CYREG_GPIO_PRT25_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310CC0UL)
|
||||
#define CYREG_GPIO_PRT25_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310CC4UL)
|
||||
#define CYREG_GPIO_PRT25_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310CC8UL)
|
||||
#define CYREG_GPIO_PRT25_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310CCCUL)
|
||||
#define CYREG_GPIO_PRT25_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310CD8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT26)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT26_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310D00UL)
|
||||
#define CYREG_GPIO_PRT26_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310D04UL)
|
||||
#define CYREG_GPIO_PRT26_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310D08UL)
|
||||
#define CYREG_GPIO_PRT26_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310D0CUL)
|
||||
#define CYREG_GPIO_PRT26_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310D10UL)
|
||||
#define CYREG_GPIO_PRT26_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310D14UL)
|
||||
#define CYREG_GPIO_PRT26_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310D18UL)
|
||||
#define CYREG_GPIO_PRT26_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310D1CUL)
|
||||
#define CYREG_GPIO_PRT26_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310D20UL)
|
||||
#define CYREG_GPIO_PRT26_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310D40UL)
|
||||
#define CYREG_GPIO_PRT26_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310D44UL)
|
||||
#define CYREG_GPIO_PRT26_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310D48UL)
|
||||
#define CYREG_GPIO_PRT26_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310D4CUL)
|
||||
#define CYREG_GPIO_PRT26_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310D58UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT27)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT27_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310D80UL)
|
||||
#define CYREG_GPIO_PRT27_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310D84UL)
|
||||
#define CYREG_GPIO_PRT27_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310D88UL)
|
||||
#define CYREG_GPIO_PRT27_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310D8CUL)
|
||||
#define CYREG_GPIO_PRT27_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310D90UL)
|
||||
#define CYREG_GPIO_PRT27_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310D94UL)
|
||||
#define CYREG_GPIO_PRT27_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310D98UL)
|
||||
#define CYREG_GPIO_PRT27_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310D9CUL)
|
||||
#define CYREG_GPIO_PRT27_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310DA0UL)
|
||||
#define CYREG_GPIO_PRT27_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310DC0UL)
|
||||
#define CYREG_GPIO_PRT27_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310DC4UL)
|
||||
#define CYREG_GPIO_PRT27_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310DC8UL)
|
||||
#define CYREG_GPIO_PRT27_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310DCCUL)
|
||||
#define CYREG_GPIO_PRT27_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310DD8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT28)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT28_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310E00UL)
|
||||
#define CYREG_GPIO_PRT28_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310E04UL)
|
||||
#define CYREG_GPIO_PRT28_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310E08UL)
|
||||
#define CYREG_GPIO_PRT28_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310E0CUL)
|
||||
#define CYREG_GPIO_PRT28_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310E10UL)
|
||||
#define CYREG_GPIO_PRT28_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310E14UL)
|
||||
#define CYREG_GPIO_PRT28_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310E18UL)
|
||||
#define CYREG_GPIO_PRT28_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310E1CUL)
|
||||
#define CYREG_GPIO_PRT28_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310E20UL)
|
||||
#define CYREG_GPIO_PRT28_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310E40UL)
|
||||
#define CYREG_GPIO_PRT28_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310E44UL)
|
||||
#define CYREG_GPIO_PRT28_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310E48UL)
|
||||
#define CYREG_GPIO_PRT28_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310E4CUL)
|
||||
#define CYREG_GPIO_PRT28_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310E58UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT29)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT29_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310E80UL)
|
||||
#define CYREG_GPIO_PRT29_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310E84UL)
|
||||
#define CYREG_GPIO_PRT29_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310E88UL)
|
||||
#define CYREG_GPIO_PRT29_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310E8CUL)
|
||||
#define CYREG_GPIO_PRT29_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310E90UL)
|
||||
#define CYREG_GPIO_PRT29_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310E94UL)
|
||||
#define CYREG_GPIO_PRT29_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310E98UL)
|
||||
#define CYREG_GPIO_PRT29_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310E9CUL)
|
||||
#define CYREG_GPIO_PRT29_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310EA0UL)
|
||||
#define CYREG_GPIO_PRT29_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310EC0UL)
|
||||
#define CYREG_GPIO_PRT29_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310EC4UL)
|
||||
#define CYREG_GPIO_PRT29_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310EC8UL)
|
||||
#define CYREG_GPIO_PRT29_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310ECCUL)
|
||||
#define CYREG_GPIO_PRT29_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310ED8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT30)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT30_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310F00UL)
|
||||
#define CYREG_GPIO_PRT30_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310F04UL)
|
||||
#define CYREG_GPIO_PRT30_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310F08UL)
|
||||
#define CYREG_GPIO_PRT30_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310F0CUL)
|
||||
#define CYREG_GPIO_PRT30_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310F10UL)
|
||||
#define CYREG_GPIO_PRT30_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310F14UL)
|
||||
#define CYREG_GPIO_PRT30_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310F18UL)
|
||||
#define CYREG_GPIO_PRT30_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310F1CUL)
|
||||
#define CYREG_GPIO_PRT30_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310F20UL)
|
||||
#define CYREG_GPIO_PRT30_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310F40UL)
|
||||
#define CYREG_GPIO_PRT30_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310F44UL)
|
||||
#define CYREG_GPIO_PRT30_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310F48UL)
|
||||
#define CYREG_GPIO_PRT30_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310F4CUL)
|
||||
#define CYREG_GPIO_PRT30_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310F58UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT31)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT31_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40310F80UL)
|
||||
#define CYREG_GPIO_PRT31_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40310F84UL)
|
||||
#define CYREG_GPIO_PRT31_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40310F88UL)
|
||||
#define CYREG_GPIO_PRT31_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x40310F8CUL)
|
||||
#define CYREG_GPIO_PRT31_IN ((volatile un_GPIO_PRT_IN_t*) 0x40310F90UL)
|
||||
#define CYREG_GPIO_PRT31_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40310F94UL)
|
||||
#define CYREG_GPIO_PRT31_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40310F98UL)
|
||||
#define CYREG_GPIO_PRT31_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x40310F9CUL)
|
||||
#define CYREG_GPIO_PRT31_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40310FA0UL)
|
||||
#define CYREG_GPIO_PRT31_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40310FC0UL)
|
||||
#define CYREG_GPIO_PRT31_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40310FC4UL)
|
||||
#define CYREG_GPIO_PRT31_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40310FC8UL)
|
||||
#define CYREG_GPIO_PRT31_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x40310FCCUL)
|
||||
#define CYREG_GPIO_PRT31_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40310FD8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT32)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT32_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40311000UL)
|
||||
#define CYREG_GPIO_PRT32_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40311004UL)
|
||||
#define CYREG_GPIO_PRT32_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40311008UL)
|
||||
#define CYREG_GPIO_PRT32_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031100CUL)
|
||||
#define CYREG_GPIO_PRT32_IN ((volatile un_GPIO_PRT_IN_t*) 0x40311010UL)
|
||||
#define CYREG_GPIO_PRT32_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40311014UL)
|
||||
#define CYREG_GPIO_PRT32_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40311018UL)
|
||||
#define CYREG_GPIO_PRT32_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031101CUL)
|
||||
#define CYREG_GPIO_PRT32_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40311020UL)
|
||||
#define CYREG_GPIO_PRT32_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40311040UL)
|
||||
#define CYREG_GPIO_PRT32_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40311044UL)
|
||||
#define CYREG_GPIO_PRT32_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40311048UL)
|
||||
#define CYREG_GPIO_PRT32_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031104CUL)
|
||||
#define CYREG_GPIO_PRT32_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40311058UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT33)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT33_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40311080UL)
|
||||
#define CYREG_GPIO_PRT33_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40311084UL)
|
||||
#define CYREG_GPIO_PRT33_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40311088UL)
|
||||
#define CYREG_GPIO_PRT33_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031108CUL)
|
||||
#define CYREG_GPIO_PRT33_IN ((volatile un_GPIO_PRT_IN_t*) 0x40311090UL)
|
||||
#define CYREG_GPIO_PRT33_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40311094UL)
|
||||
#define CYREG_GPIO_PRT33_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40311098UL)
|
||||
#define CYREG_GPIO_PRT33_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031109CUL)
|
||||
#define CYREG_GPIO_PRT33_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x403110A0UL)
|
||||
#define CYREG_GPIO_PRT33_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x403110C0UL)
|
||||
#define CYREG_GPIO_PRT33_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x403110C4UL)
|
||||
#define CYREG_GPIO_PRT33_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x403110C8UL)
|
||||
#define CYREG_GPIO_PRT33_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x403110CCUL)
|
||||
#define CYREG_GPIO_PRT33_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x403110D8UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT34)
|
||||
*/
|
||||
#define CYREG_GPIO_PRT34_OUT ((volatile un_GPIO_PRT_OUT_t*) 0x40311100UL)
|
||||
#define CYREG_GPIO_PRT34_OUT_CLR ((volatile un_GPIO_PRT_OUT_CLR_t*) 0x40311104UL)
|
||||
#define CYREG_GPIO_PRT34_OUT_SET ((volatile un_GPIO_PRT_OUT_SET_t*) 0x40311108UL)
|
||||
#define CYREG_GPIO_PRT34_OUT_INV ((volatile un_GPIO_PRT_OUT_INV_t*) 0x4031110CUL)
|
||||
#define CYREG_GPIO_PRT34_IN ((volatile un_GPIO_PRT_IN_t*) 0x40311110UL)
|
||||
#define CYREG_GPIO_PRT34_INTR ((volatile un_GPIO_PRT_INTR_t*) 0x40311114UL)
|
||||
#define CYREG_GPIO_PRT34_INTR_MASK ((volatile un_GPIO_PRT_INTR_MASK_t*) 0x40311118UL)
|
||||
#define CYREG_GPIO_PRT34_INTR_MASKED ((volatile un_GPIO_PRT_INTR_MASKED_t*) 0x4031111CUL)
|
||||
#define CYREG_GPIO_PRT34_INTR_SET ((volatile un_GPIO_PRT_INTR_SET_t*) 0x40311120UL)
|
||||
#define CYREG_GPIO_PRT34_INTR_CFG ((volatile un_GPIO_PRT_INTR_CFG_t*) 0x40311140UL)
|
||||
#define CYREG_GPIO_PRT34_CFG ((volatile un_GPIO_PRT_CFG_t*) 0x40311144UL)
|
||||
#define CYREG_GPIO_PRT34_CFG_IN ((volatile un_GPIO_PRT_CFG_IN_t*) 0x40311148UL)
|
||||
#define CYREG_GPIO_PRT34_CFG_OUT ((volatile un_GPIO_PRT_CFG_OUT_t*) 0x4031114CUL)
|
||||
#define CYREG_GPIO_PRT34_CFG_IN_AUTOLVL ((volatile un_GPIO_PRT_CFG_IN_AUTOLVL_t*) 0x40311158UL)
|
||||
|
||||
/**
|
||||
* \brief GPIO port control/configuration (GPIO0)
|
||||
*/
|
||||
#define CYREG_GPIO_INTR_CAUSE0 ((volatile un_GPIO_INTR_CAUSE0_t*) 0x40314000UL)
|
||||
#define CYREG_GPIO_INTR_CAUSE1 ((volatile un_GPIO_INTR_CAUSE1_t*) 0x40314004UL)
|
||||
#define CYREG_GPIO_VDD_ACTIVE ((volatile un_GPIO_VDD_ACTIVE_t*) 0x40314010UL)
|
||||
#define CYREG_GPIO_VDD_INTR ((volatile un_GPIO_VDD_INTR_t*) 0x40314014UL)
|
||||
#define CYREG_GPIO_VDD_INTR_MASK ((volatile un_GPIO_VDD_INTR_MASK_t*) 0x40314018UL)
|
||||
#define CYREG_GPIO_VDD_INTR_MASKED ((volatile un_GPIO_VDD_INTR_MASKED_t*) 0x4031401CUL)
|
||||
#define CYREG_GPIO_VDD_INTR_SET ((volatile un_GPIO_VDD_INTR_SET_t*) 0x40314020UL)
|
||||
|
||||
#endif /* _CYREG_GPIO_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,241 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_hsiom.h
|
||||
*
|
||||
* \brief
|
||||
* HSIOM register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_HSIOM_H_
|
||||
#define _CYREG_HSIOM_H_
|
||||
|
||||
#include "cyip_hsiom_v3.h"
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT0)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT0_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300000UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT1)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT1_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300010UL)
|
||||
#define CYREG_HSIOM_PRT1_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300014UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT2)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT2_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300020UL)
|
||||
#define CYREG_HSIOM_PRT2_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300024UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT3)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT3_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300030UL)
|
||||
#define CYREG_HSIOM_PRT3_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300034UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT4)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT4_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300040UL)
|
||||
#define CYREG_HSIOM_PRT4_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300044UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT5)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT5_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300050UL)
|
||||
#define CYREG_HSIOM_PRT5_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300054UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT6)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT6_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300060UL)
|
||||
#define CYREG_HSIOM_PRT6_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300064UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT7)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT7_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300070UL)
|
||||
#define CYREG_HSIOM_PRT7_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300074UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT8)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT8_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300080UL)
|
||||
#define CYREG_HSIOM_PRT8_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300084UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT9)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT9_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300090UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT10)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT10_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403000A0UL)
|
||||
#define CYREG_HSIOM_PRT10_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x403000A4UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT11)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT11_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403000B0UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT12)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT12_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403000C0UL)
|
||||
#define CYREG_HSIOM_PRT12_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x403000C4UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT13)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT13_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403000D0UL)
|
||||
#define CYREG_HSIOM_PRT13_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x403000D4UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT14)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT14_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403000E0UL)
|
||||
#define CYREG_HSIOM_PRT14_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x403000E4UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT15)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT15_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403000F0UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT16)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT16_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300100UL)
|
||||
#define CYREG_HSIOM_PRT16_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300104UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT17)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT17_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300110UL)
|
||||
#define CYREG_HSIOM_PRT17_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300114UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT18)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT18_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300120UL)
|
||||
#define CYREG_HSIOM_PRT18_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300124UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT19)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT19_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300130UL)
|
||||
#define CYREG_HSIOM_PRT19_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300134UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT20)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT20_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300140UL)
|
||||
#define CYREG_HSIOM_PRT20_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300144UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT21)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT21_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300150UL)
|
||||
#define CYREG_HSIOM_PRT21_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300154UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT22)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT22_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300160UL)
|
||||
#define CYREG_HSIOM_PRT22_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300164UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT23)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT23_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300170UL)
|
||||
#define CYREG_HSIOM_PRT23_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300174UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT24)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT24_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300180UL)
|
||||
#define CYREG_HSIOM_PRT24_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300184UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT25)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT25_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300190UL)
|
||||
#define CYREG_HSIOM_PRT25_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300194UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT26)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT26_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403001A0UL)
|
||||
#define CYREG_HSIOM_PRT26_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x403001A4UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT27)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT27_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403001B0UL)
|
||||
#define CYREG_HSIOM_PRT27_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x403001B4UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT28)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT28_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403001C0UL)
|
||||
#define CYREG_HSIOM_PRT28_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x403001C4UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT29)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT29_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403001D0UL)
|
||||
#define CYREG_HSIOM_PRT29_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x403001D4UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT30)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT30_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403001E0UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT31)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT31_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x403001F0UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT32)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT32_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300200UL)
|
||||
#define CYREG_HSIOM_PRT32_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300204UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT33)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT33_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300210UL)
|
||||
#define CYREG_HSIOM_PRT33_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300214UL)
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT34)
|
||||
*/
|
||||
#define CYREG_HSIOM_PRT34_PORT_SEL0 ((volatile un_HSIOM_PRT_PORT_SEL0_t*) 0x40300220UL)
|
||||
#define CYREG_HSIOM_PRT34_PORT_SEL1 ((volatile un_HSIOM_PRT_PORT_SEL1_t*) 0x40300224UL)
|
||||
|
||||
/**
|
||||
* \brief High Speed IO Matrix (HSIOM) (HSIOM0)
|
||||
*/
|
||||
#define CYREG_HSIOM_AMUX_SPLIT_CTL0 ((volatile un_HSIOM_AMUX_SPLIT_CTL_t*) 0x40302000UL)
|
||||
#define CYREG_HSIOM_AMUX_SPLIT_CTL1 ((volatile un_HSIOM_AMUX_SPLIT_CTL_t*) 0x40302004UL)
|
||||
#define CYREG_HSIOM_AMUX_SPLIT_CTL2 ((volatile un_HSIOM_AMUX_SPLIT_CTL_t*) 0x40302008UL)
|
||||
#define CYREG_HSIOM_AMUX_SPLIT_CTL3 ((volatile un_HSIOM_AMUX_SPLIT_CTL_t*) 0x4030200CUL)
|
||||
#define CYREG_HSIOM_MONITOR_CTL_0 ((volatile un_HSIOM_MONITOR_CTL_0_t*) 0x40302200UL)
|
||||
#define CYREG_HSIOM_ALT_JTAG_EN ((volatile un_HSIOM_ALT_JTAG_EN_t*) 0x40302240UL)
|
||||
|
||||
#endif /* _CYREG_HSIOM_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,99 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_i2s.h
|
||||
*
|
||||
* \brief
|
||||
* I2S register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_I2S_H_
|
||||
#define _CYREG_I2S_H_
|
||||
|
||||
#include "cyip_i2s_v2.h"
|
||||
|
||||
/**
|
||||
* \brief I2S registers (I2S0)
|
||||
*/
|
||||
#define CYREG_I2S0_CTL ((volatile un_I2S_CTL_t*) 0x40800000UL)
|
||||
#define CYREG_I2S0_CLOCK_CTL ((volatile un_I2S_CLOCK_CTL_t*) 0x40800010UL)
|
||||
#define CYREG_I2S0_CLOCK_STAT ((volatile un_I2S_CLOCK_STAT_t*) 0x40800014UL)
|
||||
#define CYREG_I2S0_CMD ((volatile un_I2S_CMD_t*) 0x40800020UL)
|
||||
#define CYREG_I2S0_TR_CTL ((volatile un_I2S_TR_CTL_t*) 0x40800040UL)
|
||||
#define CYREG_I2S0_TX_CTL ((volatile un_I2S_TX_CTL_t*) 0x40800080UL)
|
||||
#define CYREG_I2S0_TX_WATCHDOG ((volatile un_I2S_TX_WATCHDOG_t*) 0x40800084UL)
|
||||
#define CYREG_I2S0_RX_CTL ((volatile un_I2S_RX_CTL_t*) 0x408000A0UL)
|
||||
#define CYREG_I2S0_RX_WATCHDOG ((volatile un_I2S_RX_WATCHDOG_t*) 0x408000A4UL)
|
||||
#define CYREG_I2S0_TX_FIFO_CTL ((volatile un_I2S_TX_FIFO_CTL_t*) 0x40800200UL)
|
||||
#define CYREG_I2S0_TX_FIFO_STATUS ((volatile un_I2S_TX_FIFO_STATUS_t*) 0x40800204UL)
|
||||
#define CYREG_I2S0_TX_FIFO_WR ((volatile un_I2S_TX_FIFO_WR_t*) 0x40800208UL)
|
||||
#define CYREG_I2S0_RX_FIFO_CTL ((volatile un_I2S_RX_FIFO_CTL_t*) 0x40800300UL)
|
||||
#define CYREG_I2S0_RX_FIFO_STATUS ((volatile un_I2S_RX_FIFO_STATUS_t*) 0x40800304UL)
|
||||
#define CYREG_I2S0_RX_FIFO_RD ((volatile un_I2S_RX_FIFO_RD_t*) 0x40800308UL)
|
||||
#define CYREG_I2S0_RX_FIFO_RD_SILENT ((volatile un_I2S_RX_FIFO_RD_SILENT_t*) 0x4080030CUL)
|
||||
#define CYREG_I2S0_INTR ((volatile un_I2S_INTR_t*) 0x40800F00UL)
|
||||
#define CYREG_I2S0_INTR_SET ((volatile un_I2S_INTR_SET_t*) 0x40800F04UL)
|
||||
#define CYREG_I2S0_INTR_MASK ((volatile un_I2S_INTR_MASK_t*) 0x40800F08UL)
|
||||
#define CYREG_I2S0_INTR_MASKED ((volatile un_I2S_INTR_MASKED_t*) 0x40800F0CUL)
|
||||
|
||||
/**
|
||||
* \brief I2S registers (I2S1)
|
||||
*/
|
||||
#define CYREG_I2S1_CTL ((volatile un_I2S_CTL_t*) 0x40801000UL)
|
||||
#define CYREG_I2S1_CLOCK_CTL ((volatile un_I2S_CLOCK_CTL_t*) 0x40801010UL)
|
||||
#define CYREG_I2S1_CLOCK_STAT ((volatile un_I2S_CLOCK_STAT_t*) 0x40801014UL)
|
||||
#define CYREG_I2S1_CMD ((volatile un_I2S_CMD_t*) 0x40801020UL)
|
||||
#define CYREG_I2S1_TR_CTL ((volatile un_I2S_TR_CTL_t*) 0x40801040UL)
|
||||
#define CYREG_I2S1_TX_CTL ((volatile un_I2S_TX_CTL_t*) 0x40801080UL)
|
||||
#define CYREG_I2S1_TX_WATCHDOG ((volatile un_I2S_TX_WATCHDOG_t*) 0x40801084UL)
|
||||
#define CYREG_I2S1_RX_CTL ((volatile un_I2S_RX_CTL_t*) 0x408010A0UL)
|
||||
#define CYREG_I2S1_RX_WATCHDOG ((volatile un_I2S_RX_WATCHDOG_t*) 0x408010A4UL)
|
||||
#define CYREG_I2S1_TX_FIFO_CTL ((volatile un_I2S_TX_FIFO_CTL_t*) 0x40801200UL)
|
||||
#define CYREG_I2S1_TX_FIFO_STATUS ((volatile un_I2S_TX_FIFO_STATUS_t*) 0x40801204UL)
|
||||
#define CYREG_I2S1_TX_FIFO_WR ((volatile un_I2S_TX_FIFO_WR_t*) 0x40801208UL)
|
||||
#define CYREG_I2S1_RX_FIFO_CTL ((volatile un_I2S_RX_FIFO_CTL_t*) 0x40801300UL)
|
||||
#define CYREG_I2S1_RX_FIFO_STATUS ((volatile un_I2S_RX_FIFO_STATUS_t*) 0x40801304UL)
|
||||
#define CYREG_I2S1_RX_FIFO_RD ((volatile un_I2S_RX_FIFO_RD_t*) 0x40801308UL)
|
||||
#define CYREG_I2S1_RX_FIFO_RD_SILENT ((volatile un_I2S_RX_FIFO_RD_SILENT_t*) 0x4080130CUL)
|
||||
#define CYREG_I2S1_INTR ((volatile un_I2S_INTR_t*) 0x40801F00UL)
|
||||
#define CYREG_I2S1_INTR_SET ((volatile un_I2S_INTR_SET_t*) 0x40801F04UL)
|
||||
#define CYREG_I2S1_INTR_MASK ((volatile un_I2S_INTR_MASK_t*) 0x40801F08UL)
|
||||
#define CYREG_I2S1_INTR_MASKED ((volatile un_I2S_INTR_MASKED_t*) 0x40801F0CUL)
|
||||
|
||||
/**
|
||||
* \brief I2S registers (I2S2)
|
||||
*/
|
||||
#define CYREG_I2S2_CTL ((volatile un_I2S_CTL_t*) 0x40802000UL)
|
||||
#define CYREG_I2S2_CLOCK_CTL ((volatile un_I2S_CLOCK_CTL_t*) 0x40802010UL)
|
||||
#define CYREG_I2S2_CLOCK_STAT ((volatile un_I2S_CLOCK_STAT_t*) 0x40802014UL)
|
||||
#define CYREG_I2S2_CMD ((volatile un_I2S_CMD_t*) 0x40802020UL)
|
||||
#define CYREG_I2S2_TR_CTL ((volatile un_I2S_TR_CTL_t*) 0x40802040UL)
|
||||
#define CYREG_I2S2_TX_CTL ((volatile un_I2S_TX_CTL_t*) 0x40802080UL)
|
||||
#define CYREG_I2S2_TX_WATCHDOG ((volatile un_I2S_TX_WATCHDOG_t*) 0x40802084UL)
|
||||
#define CYREG_I2S2_RX_CTL ((volatile un_I2S_RX_CTL_t*) 0x408020A0UL)
|
||||
#define CYREG_I2S2_RX_WATCHDOG ((volatile un_I2S_RX_WATCHDOG_t*) 0x408020A4UL)
|
||||
#define CYREG_I2S2_TX_FIFO_CTL ((volatile un_I2S_TX_FIFO_CTL_t*) 0x40802200UL)
|
||||
#define CYREG_I2S2_TX_FIFO_STATUS ((volatile un_I2S_TX_FIFO_STATUS_t*) 0x40802204UL)
|
||||
#define CYREG_I2S2_TX_FIFO_WR ((volatile un_I2S_TX_FIFO_WR_t*) 0x40802208UL)
|
||||
#define CYREG_I2S2_RX_FIFO_CTL ((volatile un_I2S_RX_FIFO_CTL_t*) 0x40802300UL)
|
||||
#define CYREG_I2S2_RX_FIFO_STATUS ((volatile un_I2S_RX_FIFO_STATUS_t*) 0x40802304UL)
|
||||
#define CYREG_I2S2_RX_FIFO_RD ((volatile un_I2S_RX_FIFO_RD_t*) 0x40802308UL)
|
||||
#define CYREG_I2S2_RX_FIFO_RD_SILENT ((volatile un_I2S_RX_FIFO_RD_SILENT_t*) 0x4080230CUL)
|
||||
#define CYREG_I2S2_INTR ((volatile un_I2S_INTR_t*) 0x40802F00UL)
|
||||
#define CYREG_I2S2_INTR_SET ((volatile un_I2S_INTR_SET_t*) 0x40802F04UL)
|
||||
#define CYREG_I2S2_INTR_MASK ((volatile un_I2S_INTR_MASK_t*) 0x40802F08UL)
|
||||
#define CYREG_I2S2_INTR_MASKED ((volatile un_I2S_INTR_MASKED_t*) 0x40802F0CUL)
|
||||
|
||||
#endif /* _CYREG_I2S_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,171 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_ipc.h
|
||||
*
|
||||
* \brief
|
||||
* IPC register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_IPC_H_
|
||||
#define _CYREG_IPC_H_
|
||||
|
||||
#include "cyip_ipc.h"
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT0)
|
||||
*/
|
||||
#define CYREG_IPC_STRUCT0_ACQUIRE ((volatile un_IPC_STRUCT_ACQUIRE_t*) 0x40220000UL)
|
||||
#define CYREG_IPC_STRUCT0_RELEASE ((volatile un_IPC_STRUCT_RELEASE_t*) 0x40220004UL)
|
||||
#define CYREG_IPC_STRUCT0_NOTIFY ((volatile un_IPC_STRUCT_NOTIFY_t*) 0x40220008UL)
|
||||
#define CYREG_IPC_STRUCT0_DATA0 ((volatile un_IPC_STRUCT_DATA0_t*) 0x4022000CUL)
|
||||
#define CYREG_IPC_STRUCT0_DATA1 ((volatile un_IPC_STRUCT_DATA1_t*) 0x40220010UL)
|
||||
#define CYREG_IPC_STRUCT0_LOCK_STATUS ((volatile un_IPC_STRUCT_LOCK_STATUS_t*) 0x4022001CUL)
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT1)
|
||||
*/
|
||||
#define CYREG_IPC_STRUCT1_ACQUIRE ((volatile un_IPC_STRUCT_ACQUIRE_t*) 0x40220020UL)
|
||||
#define CYREG_IPC_STRUCT1_RELEASE ((volatile un_IPC_STRUCT_RELEASE_t*) 0x40220024UL)
|
||||
#define CYREG_IPC_STRUCT1_NOTIFY ((volatile un_IPC_STRUCT_NOTIFY_t*) 0x40220028UL)
|
||||
#define CYREG_IPC_STRUCT1_DATA0 ((volatile un_IPC_STRUCT_DATA0_t*) 0x4022002CUL)
|
||||
#define CYREG_IPC_STRUCT1_DATA1 ((volatile un_IPC_STRUCT_DATA1_t*) 0x40220030UL)
|
||||
#define CYREG_IPC_STRUCT1_LOCK_STATUS ((volatile un_IPC_STRUCT_LOCK_STATUS_t*) 0x4022003CUL)
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT2)
|
||||
*/
|
||||
#define CYREG_IPC_STRUCT2_ACQUIRE ((volatile un_IPC_STRUCT_ACQUIRE_t*) 0x40220040UL)
|
||||
#define CYREG_IPC_STRUCT2_RELEASE ((volatile un_IPC_STRUCT_RELEASE_t*) 0x40220044UL)
|
||||
#define CYREG_IPC_STRUCT2_NOTIFY ((volatile un_IPC_STRUCT_NOTIFY_t*) 0x40220048UL)
|
||||
#define CYREG_IPC_STRUCT2_DATA0 ((volatile un_IPC_STRUCT_DATA0_t*) 0x4022004CUL)
|
||||
#define CYREG_IPC_STRUCT2_DATA1 ((volatile un_IPC_STRUCT_DATA1_t*) 0x40220050UL)
|
||||
#define CYREG_IPC_STRUCT2_LOCK_STATUS ((volatile un_IPC_STRUCT_LOCK_STATUS_t*) 0x4022005CUL)
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT3)
|
||||
*/
|
||||
#define CYREG_IPC_STRUCT3_ACQUIRE ((volatile un_IPC_STRUCT_ACQUIRE_t*) 0x40220060UL)
|
||||
#define CYREG_IPC_STRUCT3_RELEASE ((volatile un_IPC_STRUCT_RELEASE_t*) 0x40220064UL)
|
||||
#define CYREG_IPC_STRUCT3_NOTIFY ((volatile un_IPC_STRUCT_NOTIFY_t*) 0x40220068UL)
|
||||
#define CYREG_IPC_STRUCT3_DATA0 ((volatile un_IPC_STRUCT_DATA0_t*) 0x4022006CUL)
|
||||
#define CYREG_IPC_STRUCT3_DATA1 ((volatile un_IPC_STRUCT_DATA1_t*) 0x40220070UL)
|
||||
#define CYREG_IPC_STRUCT3_LOCK_STATUS ((volatile un_IPC_STRUCT_LOCK_STATUS_t*) 0x4022007CUL)
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT4)
|
||||
*/
|
||||
#define CYREG_IPC_STRUCT4_ACQUIRE ((volatile un_IPC_STRUCT_ACQUIRE_t*) 0x40220080UL)
|
||||
#define CYREG_IPC_STRUCT4_RELEASE ((volatile un_IPC_STRUCT_RELEASE_t*) 0x40220084UL)
|
||||
#define CYREG_IPC_STRUCT4_NOTIFY ((volatile un_IPC_STRUCT_NOTIFY_t*) 0x40220088UL)
|
||||
#define CYREG_IPC_STRUCT4_DATA0 ((volatile un_IPC_STRUCT_DATA0_t*) 0x4022008CUL)
|
||||
#define CYREG_IPC_STRUCT4_DATA1 ((volatile un_IPC_STRUCT_DATA1_t*) 0x40220090UL)
|
||||
#define CYREG_IPC_STRUCT4_LOCK_STATUS ((volatile un_IPC_STRUCT_LOCK_STATUS_t*) 0x4022009CUL)
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT5)
|
||||
*/
|
||||
#define CYREG_IPC_STRUCT5_ACQUIRE ((volatile un_IPC_STRUCT_ACQUIRE_t*) 0x402200A0UL)
|
||||
#define CYREG_IPC_STRUCT5_RELEASE ((volatile un_IPC_STRUCT_RELEASE_t*) 0x402200A4UL)
|
||||
#define CYREG_IPC_STRUCT5_NOTIFY ((volatile un_IPC_STRUCT_NOTIFY_t*) 0x402200A8UL)
|
||||
#define CYREG_IPC_STRUCT5_DATA0 ((volatile un_IPC_STRUCT_DATA0_t*) 0x402200ACUL)
|
||||
#define CYREG_IPC_STRUCT5_DATA1 ((volatile un_IPC_STRUCT_DATA1_t*) 0x402200B0UL)
|
||||
#define CYREG_IPC_STRUCT5_LOCK_STATUS ((volatile un_IPC_STRUCT_LOCK_STATUS_t*) 0x402200BCUL)
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT6)
|
||||
*/
|
||||
#define CYREG_IPC_STRUCT6_ACQUIRE ((volatile un_IPC_STRUCT_ACQUIRE_t*) 0x402200C0UL)
|
||||
#define CYREG_IPC_STRUCT6_RELEASE ((volatile un_IPC_STRUCT_RELEASE_t*) 0x402200C4UL)
|
||||
#define CYREG_IPC_STRUCT6_NOTIFY ((volatile un_IPC_STRUCT_NOTIFY_t*) 0x402200C8UL)
|
||||
#define CYREG_IPC_STRUCT6_DATA0 ((volatile un_IPC_STRUCT_DATA0_t*) 0x402200CCUL)
|
||||
#define CYREG_IPC_STRUCT6_DATA1 ((volatile un_IPC_STRUCT_DATA1_t*) 0x402200D0UL)
|
||||
#define CYREG_IPC_STRUCT6_LOCK_STATUS ((volatile un_IPC_STRUCT_LOCK_STATUS_t*) 0x402200DCUL)
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT7)
|
||||
*/
|
||||
#define CYREG_IPC_STRUCT7_ACQUIRE ((volatile un_IPC_STRUCT_ACQUIRE_t*) 0x402200E0UL)
|
||||
#define CYREG_IPC_STRUCT7_RELEASE ((volatile un_IPC_STRUCT_RELEASE_t*) 0x402200E4UL)
|
||||
#define CYREG_IPC_STRUCT7_NOTIFY ((volatile un_IPC_STRUCT_NOTIFY_t*) 0x402200E8UL)
|
||||
#define CYREG_IPC_STRUCT7_DATA0 ((volatile un_IPC_STRUCT_DATA0_t*) 0x402200ECUL)
|
||||
#define CYREG_IPC_STRUCT7_DATA1 ((volatile un_IPC_STRUCT_DATA1_t*) 0x402200F0UL)
|
||||
#define CYREG_IPC_STRUCT7_LOCK_STATUS ((volatile un_IPC_STRUCT_LOCK_STATUS_t*) 0x402200FCUL)
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT0)
|
||||
*/
|
||||
#define CYREG_IPC_INTR_STRUCT0_INTR ((volatile un_IPC_INTR_STRUCT_INTR_t*) 0x40221000UL)
|
||||
#define CYREG_IPC_INTR_STRUCT0_INTR_SET ((volatile un_IPC_INTR_STRUCT_INTR_SET_t*) 0x40221004UL)
|
||||
#define CYREG_IPC_INTR_STRUCT0_INTR_MASK ((volatile un_IPC_INTR_STRUCT_INTR_MASK_t*) 0x40221008UL)
|
||||
#define CYREG_IPC_INTR_STRUCT0_INTR_MASKED ((volatile un_IPC_INTR_STRUCT_INTR_MASKED_t*) 0x4022100CUL)
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT1)
|
||||
*/
|
||||
#define CYREG_IPC_INTR_STRUCT1_INTR ((volatile un_IPC_INTR_STRUCT_INTR_t*) 0x40221020UL)
|
||||
#define CYREG_IPC_INTR_STRUCT1_INTR_SET ((volatile un_IPC_INTR_STRUCT_INTR_SET_t*) 0x40221024UL)
|
||||
#define CYREG_IPC_INTR_STRUCT1_INTR_MASK ((volatile un_IPC_INTR_STRUCT_INTR_MASK_t*) 0x40221028UL)
|
||||
#define CYREG_IPC_INTR_STRUCT1_INTR_MASKED ((volatile un_IPC_INTR_STRUCT_INTR_MASKED_t*) 0x4022102CUL)
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT2)
|
||||
*/
|
||||
#define CYREG_IPC_INTR_STRUCT2_INTR ((volatile un_IPC_INTR_STRUCT_INTR_t*) 0x40221040UL)
|
||||
#define CYREG_IPC_INTR_STRUCT2_INTR_SET ((volatile un_IPC_INTR_STRUCT_INTR_SET_t*) 0x40221044UL)
|
||||
#define CYREG_IPC_INTR_STRUCT2_INTR_MASK ((volatile un_IPC_INTR_STRUCT_INTR_MASK_t*) 0x40221048UL)
|
||||
#define CYREG_IPC_INTR_STRUCT2_INTR_MASKED ((volatile un_IPC_INTR_STRUCT_INTR_MASKED_t*) 0x4022104CUL)
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT3)
|
||||
*/
|
||||
#define CYREG_IPC_INTR_STRUCT3_INTR ((volatile un_IPC_INTR_STRUCT_INTR_t*) 0x40221060UL)
|
||||
#define CYREG_IPC_INTR_STRUCT3_INTR_SET ((volatile un_IPC_INTR_STRUCT_INTR_SET_t*) 0x40221064UL)
|
||||
#define CYREG_IPC_INTR_STRUCT3_INTR_MASK ((volatile un_IPC_INTR_STRUCT_INTR_MASK_t*) 0x40221068UL)
|
||||
#define CYREG_IPC_INTR_STRUCT3_INTR_MASKED ((volatile un_IPC_INTR_STRUCT_INTR_MASKED_t*) 0x4022106CUL)
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT4)
|
||||
*/
|
||||
#define CYREG_IPC_INTR_STRUCT4_INTR ((volatile un_IPC_INTR_STRUCT_INTR_t*) 0x40221080UL)
|
||||
#define CYREG_IPC_INTR_STRUCT4_INTR_SET ((volatile un_IPC_INTR_STRUCT_INTR_SET_t*) 0x40221084UL)
|
||||
#define CYREG_IPC_INTR_STRUCT4_INTR_MASK ((volatile un_IPC_INTR_STRUCT_INTR_MASK_t*) 0x40221088UL)
|
||||
#define CYREG_IPC_INTR_STRUCT4_INTR_MASKED ((volatile un_IPC_INTR_STRUCT_INTR_MASKED_t*) 0x4022108CUL)
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT5)
|
||||
*/
|
||||
#define CYREG_IPC_INTR_STRUCT5_INTR ((volatile un_IPC_INTR_STRUCT_INTR_t*) 0x402210A0UL)
|
||||
#define CYREG_IPC_INTR_STRUCT5_INTR_SET ((volatile un_IPC_INTR_STRUCT_INTR_SET_t*) 0x402210A4UL)
|
||||
#define CYREG_IPC_INTR_STRUCT5_INTR_MASK ((volatile un_IPC_INTR_STRUCT_INTR_MASK_t*) 0x402210A8UL)
|
||||
#define CYREG_IPC_INTR_STRUCT5_INTR_MASKED ((volatile un_IPC_INTR_STRUCT_INTR_MASKED_t*) 0x402210ACUL)
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT6)
|
||||
*/
|
||||
#define CYREG_IPC_INTR_STRUCT6_INTR ((volatile un_IPC_INTR_STRUCT_INTR_t*) 0x402210C0UL)
|
||||
#define CYREG_IPC_INTR_STRUCT6_INTR_SET ((volatile un_IPC_INTR_STRUCT_INTR_SET_t*) 0x402210C4UL)
|
||||
#define CYREG_IPC_INTR_STRUCT6_INTR_MASK ((volatile un_IPC_INTR_STRUCT_INTR_MASK_t*) 0x402210C8UL)
|
||||
#define CYREG_IPC_INTR_STRUCT6_INTR_MASKED ((volatile un_IPC_INTR_STRUCT_INTR_MASKED_t*) 0x402210CCUL)
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT7)
|
||||
*/
|
||||
#define CYREG_IPC_INTR_STRUCT7_INTR ((volatile un_IPC_INTR_STRUCT_INTR_t*) 0x402210E0UL)
|
||||
#define CYREG_IPC_INTR_STRUCT7_INTR_SET ((volatile un_IPC_INTR_STRUCT_INTR_SET_t*) 0x402210E4UL)
|
||||
#define CYREG_IPC_INTR_STRUCT7_INTR_MASK ((volatile un_IPC_INTR_STRUCT_INTR_MASK_t*) 0x402210E8UL)
|
||||
#define CYREG_IPC_INTR_STRUCT7_INTR_MASKED ((volatile un_IPC_INTR_STRUCT_INTR_MASKED_t*) 0x402210ECUL)
|
||||
|
||||
#endif /* _CYREG_IPC_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,353 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_lin.h
|
||||
*
|
||||
* \brief
|
||||
* LIN register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_LIN_H_
|
||||
#define _CYREG_LIN_H_
|
||||
|
||||
#include "cyip_lin.h"
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH0)
|
||||
*/
|
||||
#define CYREG_LIN0_CH0_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508000UL)
|
||||
#define CYREG_LIN0_CH0_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508004UL)
|
||||
#define CYREG_LIN0_CH0_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508008UL)
|
||||
#define CYREG_LIN0_CH0_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508010UL)
|
||||
#define CYREG_LIN0_CH0_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508060UL)
|
||||
#define CYREG_LIN0_CH0_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508080UL)
|
||||
#define CYREG_LIN0_CH0_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508084UL)
|
||||
#define CYREG_LIN0_CH0_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508088UL)
|
||||
#define CYREG_LIN0_CH0_INTR ((volatile un_LIN_CH_INTR_t*) 0x405080C0UL)
|
||||
#define CYREG_LIN0_CH0_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405080C4UL)
|
||||
#define CYREG_LIN0_CH0_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405080C8UL)
|
||||
#define CYREG_LIN0_CH0_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405080CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH1)
|
||||
*/
|
||||
#define CYREG_LIN0_CH1_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508100UL)
|
||||
#define CYREG_LIN0_CH1_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508104UL)
|
||||
#define CYREG_LIN0_CH1_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508108UL)
|
||||
#define CYREG_LIN0_CH1_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508110UL)
|
||||
#define CYREG_LIN0_CH1_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508160UL)
|
||||
#define CYREG_LIN0_CH1_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508180UL)
|
||||
#define CYREG_LIN0_CH1_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508184UL)
|
||||
#define CYREG_LIN0_CH1_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508188UL)
|
||||
#define CYREG_LIN0_CH1_INTR ((volatile un_LIN_CH_INTR_t*) 0x405081C0UL)
|
||||
#define CYREG_LIN0_CH1_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405081C4UL)
|
||||
#define CYREG_LIN0_CH1_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405081C8UL)
|
||||
#define CYREG_LIN0_CH1_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405081CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH2)
|
||||
*/
|
||||
#define CYREG_LIN0_CH2_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508200UL)
|
||||
#define CYREG_LIN0_CH2_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508204UL)
|
||||
#define CYREG_LIN0_CH2_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508208UL)
|
||||
#define CYREG_LIN0_CH2_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508210UL)
|
||||
#define CYREG_LIN0_CH2_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508260UL)
|
||||
#define CYREG_LIN0_CH2_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508280UL)
|
||||
#define CYREG_LIN0_CH2_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508284UL)
|
||||
#define CYREG_LIN0_CH2_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508288UL)
|
||||
#define CYREG_LIN0_CH2_INTR ((volatile un_LIN_CH_INTR_t*) 0x405082C0UL)
|
||||
#define CYREG_LIN0_CH2_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405082C4UL)
|
||||
#define CYREG_LIN0_CH2_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405082C8UL)
|
||||
#define CYREG_LIN0_CH2_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405082CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH3)
|
||||
*/
|
||||
#define CYREG_LIN0_CH3_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508300UL)
|
||||
#define CYREG_LIN0_CH3_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508304UL)
|
||||
#define CYREG_LIN0_CH3_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508308UL)
|
||||
#define CYREG_LIN0_CH3_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508310UL)
|
||||
#define CYREG_LIN0_CH3_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508360UL)
|
||||
#define CYREG_LIN0_CH3_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508380UL)
|
||||
#define CYREG_LIN0_CH3_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508384UL)
|
||||
#define CYREG_LIN0_CH3_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508388UL)
|
||||
#define CYREG_LIN0_CH3_INTR ((volatile un_LIN_CH_INTR_t*) 0x405083C0UL)
|
||||
#define CYREG_LIN0_CH3_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405083C4UL)
|
||||
#define CYREG_LIN0_CH3_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405083C8UL)
|
||||
#define CYREG_LIN0_CH3_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405083CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH4)
|
||||
*/
|
||||
#define CYREG_LIN0_CH4_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508400UL)
|
||||
#define CYREG_LIN0_CH4_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508404UL)
|
||||
#define CYREG_LIN0_CH4_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508408UL)
|
||||
#define CYREG_LIN0_CH4_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508410UL)
|
||||
#define CYREG_LIN0_CH4_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508460UL)
|
||||
#define CYREG_LIN0_CH4_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508480UL)
|
||||
#define CYREG_LIN0_CH4_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508484UL)
|
||||
#define CYREG_LIN0_CH4_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508488UL)
|
||||
#define CYREG_LIN0_CH4_INTR ((volatile un_LIN_CH_INTR_t*) 0x405084C0UL)
|
||||
#define CYREG_LIN0_CH4_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405084C4UL)
|
||||
#define CYREG_LIN0_CH4_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405084C8UL)
|
||||
#define CYREG_LIN0_CH4_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405084CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH5)
|
||||
*/
|
||||
#define CYREG_LIN0_CH5_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508500UL)
|
||||
#define CYREG_LIN0_CH5_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508504UL)
|
||||
#define CYREG_LIN0_CH5_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508508UL)
|
||||
#define CYREG_LIN0_CH5_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508510UL)
|
||||
#define CYREG_LIN0_CH5_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508560UL)
|
||||
#define CYREG_LIN0_CH5_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508580UL)
|
||||
#define CYREG_LIN0_CH5_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508584UL)
|
||||
#define CYREG_LIN0_CH5_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508588UL)
|
||||
#define CYREG_LIN0_CH5_INTR ((volatile un_LIN_CH_INTR_t*) 0x405085C0UL)
|
||||
#define CYREG_LIN0_CH5_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405085C4UL)
|
||||
#define CYREG_LIN0_CH5_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405085C8UL)
|
||||
#define CYREG_LIN0_CH5_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405085CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH6)
|
||||
*/
|
||||
#define CYREG_LIN0_CH6_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508600UL)
|
||||
#define CYREG_LIN0_CH6_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508604UL)
|
||||
#define CYREG_LIN0_CH6_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508608UL)
|
||||
#define CYREG_LIN0_CH6_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508610UL)
|
||||
#define CYREG_LIN0_CH6_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508660UL)
|
||||
#define CYREG_LIN0_CH6_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508680UL)
|
||||
#define CYREG_LIN0_CH6_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508684UL)
|
||||
#define CYREG_LIN0_CH6_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508688UL)
|
||||
#define CYREG_LIN0_CH6_INTR ((volatile un_LIN_CH_INTR_t*) 0x405086C0UL)
|
||||
#define CYREG_LIN0_CH6_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405086C4UL)
|
||||
#define CYREG_LIN0_CH6_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405086C8UL)
|
||||
#define CYREG_LIN0_CH6_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405086CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH7)
|
||||
*/
|
||||
#define CYREG_LIN0_CH7_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508700UL)
|
||||
#define CYREG_LIN0_CH7_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508704UL)
|
||||
#define CYREG_LIN0_CH7_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508708UL)
|
||||
#define CYREG_LIN0_CH7_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508710UL)
|
||||
#define CYREG_LIN0_CH7_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508760UL)
|
||||
#define CYREG_LIN0_CH7_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508780UL)
|
||||
#define CYREG_LIN0_CH7_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508784UL)
|
||||
#define CYREG_LIN0_CH7_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508788UL)
|
||||
#define CYREG_LIN0_CH7_INTR ((volatile un_LIN_CH_INTR_t*) 0x405087C0UL)
|
||||
#define CYREG_LIN0_CH7_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405087C4UL)
|
||||
#define CYREG_LIN0_CH7_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405087C8UL)
|
||||
#define CYREG_LIN0_CH7_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405087CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH8)
|
||||
*/
|
||||
#define CYREG_LIN0_CH8_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508800UL)
|
||||
#define CYREG_LIN0_CH8_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508804UL)
|
||||
#define CYREG_LIN0_CH8_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508808UL)
|
||||
#define CYREG_LIN0_CH8_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508810UL)
|
||||
#define CYREG_LIN0_CH8_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508860UL)
|
||||
#define CYREG_LIN0_CH8_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508880UL)
|
||||
#define CYREG_LIN0_CH8_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508884UL)
|
||||
#define CYREG_LIN0_CH8_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508888UL)
|
||||
#define CYREG_LIN0_CH8_INTR ((volatile un_LIN_CH_INTR_t*) 0x405088C0UL)
|
||||
#define CYREG_LIN0_CH8_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405088C4UL)
|
||||
#define CYREG_LIN0_CH8_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405088C8UL)
|
||||
#define CYREG_LIN0_CH8_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405088CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH9)
|
||||
*/
|
||||
#define CYREG_LIN0_CH9_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508900UL)
|
||||
#define CYREG_LIN0_CH9_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508904UL)
|
||||
#define CYREG_LIN0_CH9_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508908UL)
|
||||
#define CYREG_LIN0_CH9_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508910UL)
|
||||
#define CYREG_LIN0_CH9_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508960UL)
|
||||
#define CYREG_LIN0_CH9_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508980UL)
|
||||
#define CYREG_LIN0_CH9_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508984UL)
|
||||
#define CYREG_LIN0_CH9_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508988UL)
|
||||
#define CYREG_LIN0_CH9_INTR ((volatile un_LIN_CH_INTR_t*) 0x405089C0UL)
|
||||
#define CYREG_LIN0_CH9_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405089C4UL)
|
||||
#define CYREG_LIN0_CH9_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405089C8UL)
|
||||
#define CYREG_LIN0_CH9_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405089CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH10)
|
||||
*/
|
||||
#define CYREG_LIN0_CH10_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508A00UL)
|
||||
#define CYREG_LIN0_CH10_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508A04UL)
|
||||
#define CYREG_LIN0_CH10_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508A08UL)
|
||||
#define CYREG_LIN0_CH10_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508A10UL)
|
||||
#define CYREG_LIN0_CH10_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508A60UL)
|
||||
#define CYREG_LIN0_CH10_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508A80UL)
|
||||
#define CYREG_LIN0_CH10_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508A84UL)
|
||||
#define CYREG_LIN0_CH10_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508A88UL)
|
||||
#define CYREG_LIN0_CH10_INTR ((volatile un_LIN_CH_INTR_t*) 0x40508AC0UL)
|
||||
#define CYREG_LIN0_CH10_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x40508AC4UL)
|
||||
#define CYREG_LIN0_CH10_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x40508AC8UL)
|
||||
#define CYREG_LIN0_CH10_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x40508ACCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH11)
|
||||
*/
|
||||
#define CYREG_LIN0_CH11_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508B00UL)
|
||||
#define CYREG_LIN0_CH11_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508B04UL)
|
||||
#define CYREG_LIN0_CH11_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508B08UL)
|
||||
#define CYREG_LIN0_CH11_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508B10UL)
|
||||
#define CYREG_LIN0_CH11_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508B60UL)
|
||||
#define CYREG_LIN0_CH11_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508B80UL)
|
||||
#define CYREG_LIN0_CH11_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508B84UL)
|
||||
#define CYREG_LIN0_CH11_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508B88UL)
|
||||
#define CYREG_LIN0_CH11_INTR ((volatile un_LIN_CH_INTR_t*) 0x40508BC0UL)
|
||||
#define CYREG_LIN0_CH11_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x40508BC4UL)
|
||||
#define CYREG_LIN0_CH11_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x40508BC8UL)
|
||||
#define CYREG_LIN0_CH11_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x40508BCCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH12)
|
||||
*/
|
||||
#define CYREG_LIN0_CH12_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508C00UL)
|
||||
#define CYREG_LIN0_CH12_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508C04UL)
|
||||
#define CYREG_LIN0_CH12_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508C08UL)
|
||||
#define CYREG_LIN0_CH12_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508C10UL)
|
||||
#define CYREG_LIN0_CH12_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508C60UL)
|
||||
#define CYREG_LIN0_CH12_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508C80UL)
|
||||
#define CYREG_LIN0_CH12_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508C84UL)
|
||||
#define CYREG_LIN0_CH12_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508C88UL)
|
||||
#define CYREG_LIN0_CH12_INTR ((volatile un_LIN_CH_INTR_t*) 0x40508CC0UL)
|
||||
#define CYREG_LIN0_CH12_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x40508CC4UL)
|
||||
#define CYREG_LIN0_CH12_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x40508CC8UL)
|
||||
#define CYREG_LIN0_CH12_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x40508CCCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH13)
|
||||
*/
|
||||
#define CYREG_LIN0_CH13_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508D00UL)
|
||||
#define CYREG_LIN0_CH13_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508D04UL)
|
||||
#define CYREG_LIN0_CH13_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508D08UL)
|
||||
#define CYREG_LIN0_CH13_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508D10UL)
|
||||
#define CYREG_LIN0_CH13_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508D60UL)
|
||||
#define CYREG_LIN0_CH13_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508D80UL)
|
||||
#define CYREG_LIN0_CH13_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508D84UL)
|
||||
#define CYREG_LIN0_CH13_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508D88UL)
|
||||
#define CYREG_LIN0_CH13_INTR ((volatile un_LIN_CH_INTR_t*) 0x40508DC0UL)
|
||||
#define CYREG_LIN0_CH13_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x40508DC4UL)
|
||||
#define CYREG_LIN0_CH13_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x40508DC8UL)
|
||||
#define CYREG_LIN0_CH13_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x40508DCCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH14)
|
||||
*/
|
||||
#define CYREG_LIN0_CH14_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508E00UL)
|
||||
#define CYREG_LIN0_CH14_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508E04UL)
|
||||
#define CYREG_LIN0_CH14_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508E08UL)
|
||||
#define CYREG_LIN0_CH14_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508E10UL)
|
||||
#define CYREG_LIN0_CH14_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508E60UL)
|
||||
#define CYREG_LIN0_CH14_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508E80UL)
|
||||
#define CYREG_LIN0_CH14_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508E84UL)
|
||||
#define CYREG_LIN0_CH14_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508E88UL)
|
||||
#define CYREG_LIN0_CH14_INTR ((volatile un_LIN_CH_INTR_t*) 0x40508EC0UL)
|
||||
#define CYREG_LIN0_CH14_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x40508EC4UL)
|
||||
#define CYREG_LIN0_CH14_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x40508EC8UL)
|
||||
#define CYREG_LIN0_CH14_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x40508ECCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH15)
|
||||
*/
|
||||
#define CYREG_LIN0_CH15_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40508F00UL)
|
||||
#define CYREG_LIN0_CH15_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40508F04UL)
|
||||
#define CYREG_LIN0_CH15_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40508F08UL)
|
||||
#define CYREG_LIN0_CH15_CMD ((volatile un_LIN_CH_CMD_t*) 0x40508F10UL)
|
||||
#define CYREG_LIN0_CH15_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40508F60UL)
|
||||
#define CYREG_LIN0_CH15_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40508F80UL)
|
||||
#define CYREG_LIN0_CH15_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40508F84UL)
|
||||
#define CYREG_LIN0_CH15_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40508F88UL)
|
||||
#define CYREG_LIN0_CH15_INTR ((volatile un_LIN_CH_INTR_t*) 0x40508FC0UL)
|
||||
#define CYREG_LIN0_CH15_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x40508FC4UL)
|
||||
#define CYREG_LIN0_CH15_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x40508FC8UL)
|
||||
#define CYREG_LIN0_CH15_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x40508FCCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH16)
|
||||
*/
|
||||
#define CYREG_LIN0_CH16_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40509000UL)
|
||||
#define CYREG_LIN0_CH16_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40509004UL)
|
||||
#define CYREG_LIN0_CH16_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40509008UL)
|
||||
#define CYREG_LIN0_CH16_CMD ((volatile un_LIN_CH_CMD_t*) 0x40509010UL)
|
||||
#define CYREG_LIN0_CH16_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40509060UL)
|
||||
#define CYREG_LIN0_CH16_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40509080UL)
|
||||
#define CYREG_LIN0_CH16_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40509084UL)
|
||||
#define CYREG_LIN0_CH16_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40509088UL)
|
||||
#define CYREG_LIN0_CH16_INTR ((volatile un_LIN_CH_INTR_t*) 0x405090C0UL)
|
||||
#define CYREG_LIN0_CH16_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405090C4UL)
|
||||
#define CYREG_LIN0_CH16_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405090C8UL)
|
||||
#define CYREG_LIN0_CH16_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405090CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH17)
|
||||
*/
|
||||
#define CYREG_LIN0_CH17_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40509100UL)
|
||||
#define CYREG_LIN0_CH17_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40509104UL)
|
||||
#define CYREG_LIN0_CH17_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40509108UL)
|
||||
#define CYREG_LIN0_CH17_CMD ((volatile un_LIN_CH_CMD_t*) 0x40509110UL)
|
||||
#define CYREG_LIN0_CH17_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40509160UL)
|
||||
#define CYREG_LIN0_CH17_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40509180UL)
|
||||
#define CYREG_LIN0_CH17_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40509184UL)
|
||||
#define CYREG_LIN0_CH17_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40509188UL)
|
||||
#define CYREG_LIN0_CH17_INTR ((volatile un_LIN_CH_INTR_t*) 0x405091C0UL)
|
||||
#define CYREG_LIN0_CH17_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405091C4UL)
|
||||
#define CYREG_LIN0_CH17_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405091C8UL)
|
||||
#define CYREG_LIN0_CH17_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405091CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH18)
|
||||
*/
|
||||
#define CYREG_LIN0_CH18_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40509200UL)
|
||||
#define CYREG_LIN0_CH18_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40509204UL)
|
||||
#define CYREG_LIN0_CH18_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40509208UL)
|
||||
#define CYREG_LIN0_CH18_CMD ((volatile un_LIN_CH_CMD_t*) 0x40509210UL)
|
||||
#define CYREG_LIN0_CH18_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40509260UL)
|
||||
#define CYREG_LIN0_CH18_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40509280UL)
|
||||
#define CYREG_LIN0_CH18_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40509284UL)
|
||||
#define CYREG_LIN0_CH18_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40509288UL)
|
||||
#define CYREG_LIN0_CH18_INTR ((volatile un_LIN_CH_INTR_t*) 0x405092C0UL)
|
||||
#define CYREG_LIN0_CH18_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405092C4UL)
|
||||
#define CYREG_LIN0_CH18_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405092C8UL)
|
||||
#define CYREG_LIN0_CH18_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405092CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN channel structure (LIN_CH19)
|
||||
*/
|
||||
#define CYREG_LIN0_CH19_CTL0 ((volatile un_LIN_CH_CTL0_t*) 0x40509300UL)
|
||||
#define CYREG_LIN0_CH19_CTL1 ((volatile un_LIN_CH_CTL1_t*) 0x40509304UL)
|
||||
#define CYREG_LIN0_CH19_STATUS ((volatile un_LIN_CH_STATUS_t*) 0x40509308UL)
|
||||
#define CYREG_LIN0_CH19_CMD ((volatile un_LIN_CH_CMD_t*) 0x40509310UL)
|
||||
#define CYREG_LIN0_CH19_TX_RX_STATUS ((volatile un_LIN_CH_TX_RX_STATUS_t*) 0x40509360UL)
|
||||
#define CYREG_LIN0_CH19_PID_CHECKSUM ((volatile un_LIN_CH_PID_CHECKSUM_t*) 0x40509380UL)
|
||||
#define CYREG_LIN0_CH19_DATA0 ((volatile un_LIN_CH_DATA0_t*) 0x40509384UL)
|
||||
#define CYREG_LIN0_CH19_DATA1 ((volatile un_LIN_CH_DATA1_t*) 0x40509388UL)
|
||||
#define CYREG_LIN0_CH19_INTR ((volatile un_LIN_CH_INTR_t*) 0x405093C0UL)
|
||||
#define CYREG_LIN0_CH19_INTR_SET ((volatile un_LIN_CH_INTR_SET_t*) 0x405093C4UL)
|
||||
#define CYREG_LIN0_CH19_INTR_MASK ((volatile un_LIN_CH_INTR_MASK_t*) 0x405093C8UL)
|
||||
#define CYREG_LIN0_CH19_INTR_MASKED ((volatile un_LIN_CH_INTR_MASKED_t*) 0x405093CCUL)
|
||||
|
||||
/**
|
||||
* \brief LIN (LIN0)
|
||||
*/
|
||||
#define CYREG_LIN0_ERROR_CTL ((volatile un_LIN_ERROR_CTL_t*) 0x40500000UL)
|
||||
#define CYREG_LIN0_TEST_CTL ((volatile un_LIN_TEST_CTL_t*) 0x40500004UL)
|
||||
|
||||
#endif /* _CYREG_LIN_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,736 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_peri.h
|
||||
*
|
||||
* \brief
|
||||
* PERI register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_PERI_H_
|
||||
#define _CYREG_PERI_H_
|
||||
|
||||
#include "cyip_peri_v3.h"
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR0)
|
||||
*/
|
||||
#define CYREG_PERI_GR0_SL_CTL ((volatile un_PERI_GR_SL_CTL_t*) 0x40004010UL)
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR1)
|
||||
*/
|
||||
#define CYREG_PERI_GR1_SL_CTL ((volatile un_PERI_GR_SL_CTL_t*) 0x40004050UL)
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR2)
|
||||
*/
|
||||
#define CYREG_PERI_GR2_SL_CTL ((volatile un_PERI_GR_SL_CTL_t*) 0x40004090UL)
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR3)
|
||||
*/
|
||||
#define CYREG_PERI_GR3_CLOCK_CTL ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x400040C0UL)
|
||||
#define CYREG_PERI_GR3_SL_CTL ((volatile un_PERI_GR_SL_CTL_t*) 0x400040D0UL)
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR4)
|
||||
*/
|
||||
#define CYREG_PERI_GR4_CLOCK_CTL ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004100UL)
|
||||
#define CYREG_PERI_GR4_SL_CTL ((volatile un_PERI_GR_SL_CTL_t*) 0x40004110UL)
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR5)
|
||||
*/
|
||||
#define CYREG_PERI_GR5_CLOCK_CTL ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004140UL)
|
||||
#define CYREG_PERI_GR5_SL_CTL ((volatile un_PERI_GR_SL_CTL_t*) 0x40004150UL)
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR6)
|
||||
*/
|
||||
#define CYREG_PERI_GR6_CLOCK_CTL ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004180UL)
|
||||
#define CYREG_PERI_GR6_SL_CTL ((volatile un_PERI_GR_SL_CTL_t*) 0x40004190UL)
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR8)
|
||||
*/
|
||||
#define CYREG_PERI_GR8_CLOCK_CTL ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004200UL)
|
||||
#define CYREG_PERI_GR8_SL_CTL ((volatile un_PERI_GR_SL_CTL_t*) 0x40004210UL)
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR9)
|
||||
*/
|
||||
#define CYREG_PERI_GR9_CLOCK_CTL ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004240UL)
|
||||
#define CYREG_PERI_GR9_SL_CTL ((volatile un_PERI_GR_SL_CTL_t*) 0x40004250UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR0)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008000UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008004UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008008UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000800CUL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008010UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL5 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008014UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL6 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008018UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL7 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000801CUL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL8 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008020UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL9 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008024UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL10 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008028UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL11 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000802CUL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL12 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008030UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL13 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008034UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL14 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008038UL)
|
||||
#define CYREG_PERI_TR_GR0_TR_CTL15 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000803CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR1)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008400UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008404UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008408UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000840CUL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008410UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL5 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008414UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL6 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008418UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL7 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000841CUL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL8 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008420UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL9 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008424UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL10 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008428UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL11 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000842CUL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL12 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008430UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL13 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008434UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL14 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008438UL)
|
||||
#define CYREG_PERI_TR_GR1_TR_CTL15 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000843CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR2)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008800UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008804UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008808UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000880CUL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008810UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL5 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008814UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL6 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008818UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL7 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000881CUL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL8 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008820UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL9 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008824UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL10 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008828UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL11 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000882CUL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL12 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008830UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL13 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008834UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL14 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008838UL)
|
||||
#define CYREG_PERI_TR_GR2_TR_CTL15 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000883CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR3)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR3_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C00UL)
|
||||
#define CYREG_PERI_TR_GR3_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C04UL)
|
||||
#define CYREG_PERI_TR_GR3_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C08UL)
|
||||
#define CYREG_PERI_TR_GR3_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C0CUL)
|
||||
#define CYREG_PERI_TR_GR3_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C10UL)
|
||||
#define CYREG_PERI_TR_GR3_TR_CTL5 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C14UL)
|
||||
#define CYREG_PERI_TR_GR3_TR_CTL6 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C18UL)
|
||||
#define CYREG_PERI_TR_GR3_TR_CTL7 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C1CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR4)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009000UL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009004UL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009008UL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000900CUL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009010UL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL5 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009014UL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL6 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009018UL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL7 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000901CUL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL8 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009020UL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL9 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009024UL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL10 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009028UL)
|
||||
#define CYREG_PERI_TR_GR4_TR_CTL11 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000902CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR5)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009400UL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009404UL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009408UL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000940CUL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009410UL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL5 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009414UL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL6 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009418UL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL7 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000941CUL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL8 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009420UL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL9 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009424UL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL10 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009428UL)
|
||||
#define CYREG_PERI_TR_GR5_TR_CTL11 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000942CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR6)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009800UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009804UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009808UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000980CUL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009810UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL5 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009814UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL6 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009818UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL7 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000981CUL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL8 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009820UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL9 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009824UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL10 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009828UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL11 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000982CUL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL12 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009830UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL13 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009834UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL14 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009838UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL15 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000983CUL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL16 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009840UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL17 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009844UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL18 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009848UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL19 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000984CUL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL20 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009850UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL21 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009854UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL22 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009858UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL23 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000985CUL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL24 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009860UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL25 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009864UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL26 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009868UL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL27 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000986CUL)
|
||||
#define CYREG_PERI_TR_GR6_TR_CTL28 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009870UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR7)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C00UL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C04UL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C08UL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C0CUL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C10UL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL5 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C14UL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL6 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C18UL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL7 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C1CUL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL8 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C20UL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL9 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C24UL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL10 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C28UL)
|
||||
#define CYREG_PERI_TR_GR7_TR_CTL11 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C2CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR8)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A000UL)
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A004UL)
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A008UL)
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A00CUL)
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A010UL)
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL5 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A014UL)
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL6 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A018UL)
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL7 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A01CUL)
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL8 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A020UL)
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL9 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A024UL)
|
||||
#define CYREG_PERI_TR_GR8_TR_CTL10 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A028UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR9)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A400UL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A404UL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A408UL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A40CUL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A410UL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL5 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A414UL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL6 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A418UL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL7 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A41CUL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL8 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A420UL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL9 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A424UL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL10 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A428UL)
|
||||
#define CYREG_PERI_TR_GR9_TR_CTL11 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A42CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR10)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR10_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A800UL)
|
||||
#define CYREG_PERI_TR_GR10_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A804UL)
|
||||
#define CYREG_PERI_TR_GR10_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A808UL)
|
||||
#define CYREG_PERI_TR_GR10_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A80CUL)
|
||||
#define CYREG_PERI_TR_GR10_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A810UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR11)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR11_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000AC00UL)
|
||||
#define CYREG_PERI_TR_GR11_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000AC04UL)
|
||||
#define CYREG_PERI_TR_GR11_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000AC08UL)
|
||||
#define CYREG_PERI_TR_GR11_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000AC0CUL)
|
||||
#define CYREG_PERI_TR_GR11_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000AC10UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR12)
|
||||
*/
|
||||
#define CYREG_PERI_TR_GR12_TR_CTL0 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000B000UL)
|
||||
#define CYREG_PERI_TR_GR12_TR_CTL1 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000B004UL)
|
||||
#define CYREG_PERI_TR_GR12_TR_CTL2 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000B008UL)
|
||||
#define CYREG_PERI_TR_GR12_TR_CTL3 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000B00CUL)
|
||||
#define CYREG_PERI_TR_GR12_TR_CTL4 ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000B010UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR0)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C000UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C004UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C008UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C00CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C010UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL5 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C014UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL6 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C018UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL7 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C01CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL8 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C020UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL9 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C024UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C028UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C02CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C030UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C034UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C038UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR1)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C400UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C404UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C408UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C40CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C410UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL5 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C414UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL6 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C418UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL7 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C41CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL8 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C420UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL9 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C424UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C428UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C42CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C430UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C434UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C438UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C43CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C440UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C444UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C448UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C44CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C450UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C454UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL22 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C458UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL23 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C45CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL24 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C460UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL25 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C464UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL26 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C468UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL27 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C46CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL28 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C470UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL29 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C474UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL30 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C478UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL31 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C47CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL32 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C480UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL33 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C484UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL34 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C488UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL35 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C48CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL36 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C490UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL37 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C494UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL38 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C498UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL39 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C49CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL40 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4A0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL41 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4A4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL42 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4A8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL43 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4ACUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL44 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4B0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL45 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4B4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL46 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4B8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL47 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4BCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL48 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4C0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL49 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4C4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL50 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4C8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL51 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4CCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL52 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4D0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL53 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4D4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL54 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4D8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL55 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4DCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL56 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4E0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL57 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4E4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL58 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4E8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL59 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4ECUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL60 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4F0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL61 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4F4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL62 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4F8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL63 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4FCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL64 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C500UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL65 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C504UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL66 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C508UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL67 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C50CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL68 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C510UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL69 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C514UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL70 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C518UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL71 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C51CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL72 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C520UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL73 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C524UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL74 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C528UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL75 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C52CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL76 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C530UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL77 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C534UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL78 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C538UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL79 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C53CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL80 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C540UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL81 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C544UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL82 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C548UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL83 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C54CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL84 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C550UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL85 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C554UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL86 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C558UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL87 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C55CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL88 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C560UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL89 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C564UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL90 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C568UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL91 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C56CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL92 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C570UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL93 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C574UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL94 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C578UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL95 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C57CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR2)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C800UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C804UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C808UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C80CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C810UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL5 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C814UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL6 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C818UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL7 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C81CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL8 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C820UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL9 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C824UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C828UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C82CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C830UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C834UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C838UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C83CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C840UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C844UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C848UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C84CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C850UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C854UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR3)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC00UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC04UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR4)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D000UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D004UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D008UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D00CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D010UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL5 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D014UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL6 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D018UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL7 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D01CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL8 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D020UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL9 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D024UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D028UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D02CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D030UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D034UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D038UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR5)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D400UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D404UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D408UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D40CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D410UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL5 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D414UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR6)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D800UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D804UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D808UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D80CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D810UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL5 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D814UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL6 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D818UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL7 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D81CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL8 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D820UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL9 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D824UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D828UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D82CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D830UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D834UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D838UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D83CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D840UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D844UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D848UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D84CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D850UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D854UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL22 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D858UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL23 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D85CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL24 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D860UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL25 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D864UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL26 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D868UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL27 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D86CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL28 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D870UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL29 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D874UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL30 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D878UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL31 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D87CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL32 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D880UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL33 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D884UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL34 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D888UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL35 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D88CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL36 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D890UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL37 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D894UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL38 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D898UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL39 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D89CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL40 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8A0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL41 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8A4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL42 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8A8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL43 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8ACUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL44 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8B0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL45 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8B4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL46 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8B8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL47 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8BCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL48 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8C0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL49 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8C4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL50 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8C8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL51 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8CCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL52 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8D0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL53 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8D4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL54 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8D8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL55 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8DCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL56 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8E0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL57 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8E4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL58 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8E8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL59 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8ECUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL60 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8F0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL61 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8F4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL62 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8F8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL63 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8FCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL64 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D900UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL65 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D904UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL66 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D908UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL67 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D90CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL68 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D910UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL69 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D914UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL70 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D918UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL71 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D91CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL72 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D920UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL73 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D924UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL74 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D928UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL75 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D92CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL76 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D930UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL77 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D934UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL78 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D938UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL79 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D93CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL80 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D940UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL81 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D944UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL82 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D948UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL83 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D94CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL84 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D950UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL85 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D954UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL86 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D958UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL87 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D95CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL88 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D960UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL89 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D964UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL90 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D968UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL91 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D96CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL92 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D970UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL93 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D974UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL94 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D978UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL95 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D97CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR7)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC00UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC04UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC08UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC0CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC10UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL5 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC14UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL6 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC18UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL7 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC1CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL8 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC20UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL9 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC24UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC28UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC2CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC30UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC34UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC38UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC3CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC40UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC44UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC48UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC4CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC50UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC54UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL22 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC58UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL23 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC5CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL24 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC60UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL25 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC64UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL26 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC68UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL27 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC6CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL28 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC70UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL29 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC74UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL30 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC78UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL31 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC7CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL32 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC80UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL33 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC84UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL34 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC88UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL35 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC8CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL36 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC90UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL37 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC94UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL38 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC98UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL39 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC9CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL40 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCA0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL41 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCA4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL42 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCA8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL43 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCACUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL44 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCB0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL45 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCB4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL46 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCB8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL47 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCBCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL48 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCC0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL49 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCC4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL50 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCC8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL51 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCCCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL52 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCD0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL53 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCD4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL54 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCD8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL55 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCDCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL56 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCE0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL57 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCE4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL58 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCE8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL59 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCECUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL60 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCF0UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL61 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCF4UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL62 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCF8UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL63 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCFCUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL64 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD00UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL65 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD04UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL66 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD08UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL67 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD0CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL68 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD10UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL69 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD14UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL70 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD18UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL71 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD1CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL72 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD20UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL73 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD24UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL74 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD28UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL75 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD2CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL76 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD30UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL77 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD34UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL78 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD38UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL79 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD3CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL80 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD40UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL81 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD44UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL82 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD48UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL83 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD4CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL84 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD50UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL85 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD54UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL86 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD58UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL87 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD5CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL88 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD60UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL89 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD64UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL90 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD68UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL91 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD6CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL92 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD70UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL93 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD74UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL94 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD78UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL95 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD7CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR8)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E000UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E004UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E008UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E00CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E010UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR9)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E400UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E404UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E408UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E40CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E410UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR10)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E800UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E804UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E808UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E80CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E810UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL5 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E814UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL6 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E818UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL7 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E81CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL8 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E820UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL9 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E824UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E828UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E82CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E830UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E834UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E838UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E83CUL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E840UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E844UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E848UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E84CUL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR11)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR11_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000EC00UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR11_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000EC04UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR12)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR12_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000F000UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR12_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000F004UL)
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR13)
|
||||
*/
|
||||
#define CYREG_PERI_TR_1TO1_GR13_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000F400UL)
|
||||
#define CYREG_PERI_TR_1TO1_GR13_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000F404UL)
|
||||
|
||||
/**
|
||||
* \brief Peripheral interconnect (PERI0)
|
||||
*/
|
||||
#define CYREG_PERI_TIMEOUT_CTL ((volatile un_PERI_TIMEOUT_CTL_t*) 0x40000200UL)
|
||||
#define CYREG_PERI_TR_CMD ((volatile un_PERI_TR_CMD_t*) 0x40000220UL)
|
||||
#define CYREG_PERI_ECC_CTL ((volatile un_PERI_ECC_CTL_t*) 0x40002000UL)
|
||||
|
||||
#endif /* _CYREG_PERI_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,274 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_peri_pclk.h
|
||||
*
|
||||
* \brief
|
||||
* PERI_PCLK register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_PERI_PCLK_H_
|
||||
#define _CYREG_PERI_PCLK_H_
|
||||
|
||||
#include "cyip_peri_pclk_v3.h"
|
||||
|
||||
/**
|
||||
* \brief PERI clock domains (PERI_PCLK_GR0)
|
||||
*/
|
||||
#define CYREG_PERI_PCLK_GR0_DIV_CMD ((volatile un_PERI_PCLK_GR_DIV_CMD_t*) 0x40040000UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL0 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C00UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL1 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C04UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL2 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C08UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL3 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C0CUL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL4 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C10UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL5 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C14UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL6 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C18UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL7 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C1CUL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL8 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C20UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL9 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C24UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL10 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C28UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL11 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C2CUL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL12 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C30UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL13 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C34UL)
|
||||
#define CYREG_PERI_PCLK_GR0_CLOCK_CTL14 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40040C38UL)
|
||||
#define CYREG_PERI_PCLK_GR0_DIV_8_CTL0 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40041000UL)
|
||||
#define CYREG_PERI_PCLK_GR0_DIV_8_CTL1 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40041004UL)
|
||||
#define CYREG_PERI_PCLK_GR0_DIV_8_CTL2 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40041008UL)
|
||||
#define CYREG_PERI_PCLK_GR0_DIV_8_CTL3 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x4004100CUL)
|
||||
#define CYREG_PERI_PCLK_GR0_DIV_16_CTL0 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40041400UL)
|
||||
#define CYREG_PERI_PCLK_GR0_DIV_16_CTL1 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40041404UL)
|
||||
#define CYREG_PERI_PCLK_GR0_DIV_16_CTL2 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40041408UL)
|
||||
#define CYREG_PERI_PCLK_GR0_DIV_24_5_CTL0 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40041C00UL)
|
||||
|
||||
/**
|
||||
* \brief PERI clock domains (PERI_PCLK_GR1)
|
||||
*/
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_CMD ((volatile un_PERI_PCLK_GR_DIV_CMD_t*) 0x40042000UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL0 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C00UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL1 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C04UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL2 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C08UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL3 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C0CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL4 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C10UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL5 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C14UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL6 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C18UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL7 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C1CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL8 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C20UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL9 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C24UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL10 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C28UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL11 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C2CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL12 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C30UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL13 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C34UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL14 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C38UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL15 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C3CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL16 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C40UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL17 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C44UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL18 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C48UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL19 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C4CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL20 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C50UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL21 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C54UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL22 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C58UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL23 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C5CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL24 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C60UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL25 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C64UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL26 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C68UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL27 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C6CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL28 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C70UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL29 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C74UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL30 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C78UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL31 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C7CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL32 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C80UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL33 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C84UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL34 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C88UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL35 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C8CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL36 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C90UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL37 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C94UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL38 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C98UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL39 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042C9CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL40 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CA0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL41 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CA4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL42 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CA8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL43 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CACUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL44 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CB0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL45 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CB4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL46 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CB8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL47 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CBCUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL48 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CC0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL49 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CC4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL50 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CC8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL51 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CCCUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL52 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CD0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL53 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CD4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL54 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CD8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL55 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CDCUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL56 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CE0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL57 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CE4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL58 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CE8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL59 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CECUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL60 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CF0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL61 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CF4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL62 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CF8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL63 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042CFCUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL64 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D00UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL65 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D04UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL66 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D08UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL67 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D0CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL68 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D10UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL69 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D14UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL70 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D18UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL71 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D1CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL72 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D20UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL73 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D24UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL74 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D28UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL75 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D2CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL76 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D30UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL77 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D34UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL78 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D38UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL79 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D3CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL80 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D40UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL81 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D44UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL82 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D48UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL83 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D4CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL84 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D50UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL85 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D54UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL86 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D58UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL87 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D5CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL88 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D60UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL89 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D64UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL90 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D68UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL91 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D6CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL92 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D70UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL93 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D74UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL94 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D78UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL95 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D7CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL96 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D80UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL97 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D84UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL98 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D88UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL99 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D8CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL100 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D90UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL101 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D94UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL102 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D98UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL103 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042D9CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL104 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DA0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL105 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DA4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL106 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DA8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL107 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DACUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL108 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DB0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL109 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DB4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL110 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DB8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL111 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DBCUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL112 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DC0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL113 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DC4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL114 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DC8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL115 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DCCUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL116 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DD0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL117 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DD4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL118 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DD8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL119 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DDCUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL120 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DE0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL121 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DE4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL122 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DE8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL123 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DECUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL124 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DF0UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL125 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DF4UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL126 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DF8UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL127 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042DFCUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL128 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E00UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL129 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E04UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL130 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E08UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL131 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E0CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL132 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E10UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL133 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E14UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL134 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E18UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL135 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E1CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL136 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E20UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL137 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E24UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL138 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E28UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL139 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E2CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL140 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E30UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL141 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E34UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL142 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E38UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL143 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E3CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL144 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E40UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL145 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E44UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL146 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E48UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL147 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E4CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL148 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E50UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL149 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E54UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL150 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E58UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL151 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E5CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL152 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E60UL)
|
||||
#define CYREG_PERI_PCLK_GR1_CLOCK_CTL153 ((volatile un_PERI_PCLK_GR_CLOCK_CTL_t*) 0x40042E64UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL0 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043000UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL1 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043004UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL2 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043008UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL3 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x4004300CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL4 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043010UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL5 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043014UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL6 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043018UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL7 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x4004301CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL8 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043020UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL9 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043024UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL10 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043028UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL11 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x4004302CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL12 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043030UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL13 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043034UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL14 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043038UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL15 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x4004303CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL16 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043040UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL17 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043044UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_8_CTL18 ((volatile un_PERI_PCLK_GR_DIV_8_CTL_t*) 0x40043048UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL0 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043400UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL1 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043404UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL2 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043408UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL3 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x4004340CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL4 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043410UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL5 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043414UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL6 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043418UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL7 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x4004341CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL8 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043420UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL9 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043424UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL10 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043428UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL11 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x4004342CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL12 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043430UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL13 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043434UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL14 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043438UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL15 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x4004343CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL16 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043440UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL17 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043444UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL18 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x40043448UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_16_CTL19 ((volatile un_PERI_PCLK_GR_DIV_16_CTL_t*) 0x4004344CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL0 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C00UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL1 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C04UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL2 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C08UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL3 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C0CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL4 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C10UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL5 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C14UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL6 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C18UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL7 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C1CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL8 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C20UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL9 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C24UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL10 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C28UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL11 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C2CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL12 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C30UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL13 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C34UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL14 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C38UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL15 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C3CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL16 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C40UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL17 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C44UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL18 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C48UL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL19 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C4CUL)
|
||||
#define CYREG_PERI_PCLK_GR1_DIV_24_5_CTL20 ((volatile un_PERI_PCLK_GR_DIV_24_5_CTL_t*) 0x40043C50UL)
|
||||
|
||||
#endif /* _CYREG_PERI_PCLK_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,81 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_sdhc.h
|
||||
*
|
||||
* \brief
|
||||
* SDHC register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_SDHC_H_
|
||||
#define _CYREG_SDHC_H_
|
||||
|
||||
#include "cyip_sdhc.h"
|
||||
|
||||
/**
|
||||
* \brief MMIO at SDHC wrapper level (SDHC_WRAP0)
|
||||
*/
|
||||
#define CYREG_SDHC0_WRAP_CTL ((volatile un_SDHC_WRAP_CTL_t*) 0x40460000UL)
|
||||
|
||||
/**
|
||||
* \brief MMIO for Synopsys Mobile Storage Host Controller IP (SDHC_CORE0)
|
||||
*/
|
||||
#define CYREG_SDHC0_CORE_SDMASA_R ((volatile un_SDHC_CORE_SDMASA_R_t*) 0x40461000UL)
|
||||
#define CYREG_SDHC0_CORE_BLOCKSIZE_R ((volatile un_SDHC_CORE_BLOCKSIZE_R_t*) 0x40461004UL)
|
||||
#define CYREG_SDHC0_CORE_BLOCKCOUNT_R ((volatile un_SDHC_CORE_BLOCKCOUNT_R_t*) 0x40461006UL)
|
||||
#define CYREG_SDHC0_CORE_ARGUMENT_R ((volatile un_SDHC_CORE_ARGUMENT_R_t*) 0x40461008UL)
|
||||
#define CYREG_SDHC0_CORE_XFER_MODE_R ((volatile un_SDHC_CORE_XFER_MODE_R_t*) 0x4046100CUL)
|
||||
#define CYREG_SDHC0_CORE_CMD_R ((volatile un_SDHC_CORE_CMD_R_t*) 0x4046100EUL)
|
||||
#define CYREG_SDHC0_CORE_RESP01_R ((volatile un_SDHC_CORE_RESP01_R_t*) 0x40461010UL)
|
||||
#define CYREG_SDHC0_CORE_RESP23_R ((volatile un_SDHC_CORE_RESP23_R_t*) 0x40461014UL)
|
||||
#define CYREG_SDHC0_CORE_RESP45_R ((volatile un_SDHC_CORE_RESP45_R_t*) 0x40461018UL)
|
||||
#define CYREG_SDHC0_CORE_RESP67_R ((volatile un_SDHC_CORE_RESP67_R_t*) 0x4046101CUL)
|
||||
#define CYREG_SDHC0_CORE_BUF_DATA_R ((volatile un_SDHC_CORE_BUF_DATA_R_t*) 0x40461020UL)
|
||||
#define CYREG_SDHC0_CORE_PSTATE_REG ((volatile un_SDHC_CORE_PSTATE_REG_t*) 0x40461024UL)
|
||||
#define CYREG_SDHC0_CORE_HOST_CTRL1_R ((volatile un_SDHC_CORE_HOST_CTRL1_R_t*) 0x40461028UL)
|
||||
#define CYREG_SDHC0_CORE_PWR_CTRL_R ((volatile un_SDHC_CORE_PWR_CTRL_R_t*) 0x40461029UL)
|
||||
#define CYREG_SDHC0_CORE_BGAP_CTRL_R ((volatile un_SDHC_CORE_BGAP_CTRL_R_t*) 0x4046102AUL)
|
||||
#define CYREG_SDHC0_CORE_WUP_CTRL_R ((volatile un_SDHC_CORE_WUP_CTRL_R_t*) 0x4046102BUL)
|
||||
#define CYREG_SDHC0_CORE_CLK_CTRL_R ((volatile un_SDHC_CORE_CLK_CTRL_R_t*) 0x4046102CUL)
|
||||
#define CYREG_SDHC0_CORE_TOUT_CTRL_R ((volatile un_SDHC_CORE_TOUT_CTRL_R_t*) 0x4046102EUL)
|
||||
#define CYREG_SDHC0_CORE_SW_RST_R ((volatile un_SDHC_CORE_SW_RST_R_t*) 0x4046102FUL)
|
||||
#define CYREG_SDHC0_CORE_NORMAL_INT_STAT_R ((volatile un_SDHC_CORE_NORMAL_INT_STAT_R_t*) 0x40461030UL)
|
||||
#define CYREG_SDHC0_CORE_ERROR_INT_STAT_R ((volatile un_SDHC_CORE_ERROR_INT_STAT_R_t*) 0x40461032UL)
|
||||
#define CYREG_SDHC0_CORE_NORMAL_INT_STAT_EN_R ((volatile un_SDHC_CORE_NORMAL_INT_STAT_EN_R_t*) 0x40461034UL)
|
||||
#define CYREG_SDHC0_CORE_ERROR_INT_STAT_EN_R ((volatile un_SDHC_CORE_ERROR_INT_STAT_EN_R_t*) 0x40461036UL)
|
||||
#define CYREG_SDHC0_CORE_NORMAL_INT_SIGNAL_EN_R ((volatile un_SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_t*) 0x40461038UL)
|
||||
#define CYREG_SDHC0_CORE_ERROR_INT_SIGNAL_EN_R ((volatile un_SDHC_CORE_ERROR_INT_SIGNAL_EN_R_t*) 0x4046103AUL)
|
||||
#define CYREG_SDHC0_CORE_AUTO_CMD_STAT_R ((volatile un_SDHC_CORE_AUTO_CMD_STAT_R_t*) 0x4046103CUL)
|
||||
#define CYREG_SDHC0_CORE_HOST_CTRL2_R ((volatile un_SDHC_CORE_HOST_CTRL2_R_t*) 0x4046103EUL)
|
||||
#define CYREG_SDHC0_CORE_CAPABILITIES1_R ((volatile un_SDHC_CORE_CAPABILITIES1_R_t*) 0x40461040UL)
|
||||
#define CYREG_SDHC0_CORE_CAPABILITIES2_R ((volatile un_SDHC_CORE_CAPABILITIES2_R_t*) 0x40461044UL)
|
||||
#define CYREG_SDHC0_CORE_CURR_CAPABILITIES1_R ((volatile un_SDHC_CORE_CURR_CAPABILITIES1_R_t*) 0x40461048UL)
|
||||
#define CYREG_SDHC0_CORE_CURR_CAPABILITIES2_R ((volatile un_SDHC_CORE_CURR_CAPABILITIES2_R_t*) 0x4046104CUL)
|
||||
#define CYREG_SDHC0_CORE_FORCE_AUTO_CMD_STAT_R ((volatile un_SDHC_CORE_FORCE_AUTO_CMD_STAT_R_t*) 0x40461050UL)
|
||||
#define CYREG_SDHC0_CORE_FORCE_ERROR_INT_STAT_R ((volatile un_SDHC_CORE_FORCE_ERROR_INT_STAT_R_t*) 0x40461052UL)
|
||||
#define CYREG_SDHC0_CORE_ADMA_ERR_STAT_R ((volatile un_SDHC_CORE_ADMA_ERR_STAT_R_t*) 0x40461054UL)
|
||||
#define CYREG_SDHC0_CORE_ADMA_SA_LOW_R ((volatile un_SDHC_CORE_ADMA_SA_LOW_R_t*) 0x40461058UL)
|
||||
#define CYREG_SDHC0_CORE_ADMA_ID_LOW_R ((volatile un_SDHC_CORE_ADMA_ID_LOW_R_t*) 0x40461078UL)
|
||||
#define CYREG_SDHC0_CORE_HOST_CNTRL_VERS_R ((volatile un_SDHC_CORE_HOST_CNTRL_VERS_R_t*) 0x404610FEUL)
|
||||
#define CYREG_SDHC0_CORE_MSHC_VER_ID_R ((volatile un_SDHC_CORE_MSHC_VER_ID_R_t*) 0x40461500UL)
|
||||
#define CYREG_SDHC0_CORE_MSHC_VER_TYPE_R ((volatile un_SDHC_CORE_MSHC_VER_TYPE_R_t*) 0x40461504UL)
|
||||
#define CYREG_SDHC0_CORE_MSHC_CTRL_R ((volatile un_SDHC_CORE_MSHC_CTRL_R_t*) 0x40461508UL)
|
||||
#define CYREG_SDHC0_CORE_MBIU_CTRL_R ((volatile un_SDHC_CORE_MBIU_CTRL_R_t*) 0x40461510UL)
|
||||
#define CYREG_SDHC0_CORE_EMMC_CTRL_R ((volatile un_SDHC_CORE_EMMC_CTRL_R_t*) 0x4046152CUL)
|
||||
#define CYREG_SDHC0_CORE_BOOT_CTRL_R ((volatile un_SDHC_CORE_BOOT_CTRL_R_t*) 0x4046152EUL)
|
||||
#define CYREG_SDHC0_CORE_GP_IN_R ((volatile un_SDHC_CORE_GP_IN_R_t*) 0x40461530UL)
|
||||
#define CYREG_SDHC0_CORE_GP_OUT_R ((volatile un_SDHC_CORE_GP_OUT_R_t*) 0x40461534UL)
|
||||
|
||||
#endif /* _CYREG_SDHC_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,152 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_smartio.h
|
||||
*
|
||||
* \brief
|
||||
* SMARTIO register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_SMARTIO_H_
|
||||
#define _CYREG_SMARTIO_H_
|
||||
|
||||
#include "cyip_smartio_v3.h"
|
||||
|
||||
/**
|
||||
* \brief Programmable IO port registers (SMARTIO_PRT12)
|
||||
*/
|
||||
#define CYREG_SMARTIO_PRT12_CTL ((volatile un_SMARTIO_PRT_CTL_t*) 0x40320C00UL)
|
||||
#define CYREG_SMARTIO_PRT12_SYNC_CTL ((volatile un_SMARTIO_PRT_SYNC_CTL_t*) 0x40320C10UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_SEL0 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320C20UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_SEL1 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320C24UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_SEL2 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320C28UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_SEL3 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320C2CUL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_SEL4 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320C30UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_SEL5 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320C34UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_SEL6 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320C38UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_SEL7 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320C3CUL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_CTL0 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320C40UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_CTL1 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320C44UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_CTL2 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320C48UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_CTL3 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320C4CUL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_CTL4 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320C50UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_CTL5 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320C54UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_CTL6 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320C58UL)
|
||||
#define CYREG_SMARTIO_PRT12_LUT_CTL7 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320C5CUL)
|
||||
#define CYREG_SMARTIO_PRT12_DU_SEL ((volatile un_SMARTIO_PRT_DU_SEL_t*) 0x40320CC0UL)
|
||||
#define CYREG_SMARTIO_PRT12_DU_CTL ((volatile un_SMARTIO_PRT_DU_CTL_t*) 0x40320CC4UL)
|
||||
#define CYREG_SMARTIO_PRT12_DATA ((volatile un_SMARTIO_PRT_DATA_t*) 0x40320CF0UL)
|
||||
|
||||
/**
|
||||
* \brief Programmable IO port registers (SMARTIO_PRT13)
|
||||
*/
|
||||
#define CYREG_SMARTIO_PRT13_CTL ((volatile un_SMARTIO_PRT_CTL_t*) 0x40320D00UL)
|
||||
#define CYREG_SMARTIO_PRT13_SYNC_CTL ((volatile un_SMARTIO_PRT_SYNC_CTL_t*) 0x40320D10UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_SEL0 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320D20UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_SEL1 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320D24UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_SEL2 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320D28UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_SEL3 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320D2CUL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_SEL4 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320D30UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_SEL5 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320D34UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_SEL6 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320D38UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_SEL7 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320D3CUL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_CTL0 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320D40UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_CTL1 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320D44UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_CTL2 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320D48UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_CTL3 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320D4CUL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_CTL4 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320D50UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_CTL5 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320D54UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_CTL6 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320D58UL)
|
||||
#define CYREG_SMARTIO_PRT13_LUT_CTL7 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320D5CUL)
|
||||
#define CYREG_SMARTIO_PRT13_DU_SEL ((volatile un_SMARTIO_PRT_DU_SEL_t*) 0x40320DC0UL)
|
||||
#define CYREG_SMARTIO_PRT13_DU_CTL ((volatile un_SMARTIO_PRT_DU_CTL_t*) 0x40320DC4UL)
|
||||
#define CYREG_SMARTIO_PRT13_DATA ((volatile un_SMARTIO_PRT_DATA_t*) 0x40320DF0UL)
|
||||
|
||||
/**
|
||||
* \brief Programmable IO port registers (SMARTIO_PRT14)
|
||||
*/
|
||||
#define CYREG_SMARTIO_PRT14_CTL ((volatile un_SMARTIO_PRT_CTL_t*) 0x40320E00UL)
|
||||
#define CYREG_SMARTIO_PRT14_SYNC_CTL ((volatile un_SMARTIO_PRT_SYNC_CTL_t*) 0x40320E10UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_SEL0 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320E20UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_SEL1 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320E24UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_SEL2 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320E28UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_SEL3 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320E2CUL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_SEL4 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320E30UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_SEL5 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320E34UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_SEL6 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320E38UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_SEL7 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320E3CUL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_CTL0 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320E40UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_CTL1 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320E44UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_CTL2 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320E48UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_CTL3 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320E4CUL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_CTL4 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320E50UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_CTL5 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320E54UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_CTL6 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320E58UL)
|
||||
#define CYREG_SMARTIO_PRT14_LUT_CTL7 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320E5CUL)
|
||||
#define CYREG_SMARTIO_PRT14_DU_SEL ((volatile un_SMARTIO_PRT_DU_SEL_t*) 0x40320EC0UL)
|
||||
#define CYREG_SMARTIO_PRT14_DU_CTL ((volatile un_SMARTIO_PRT_DU_CTL_t*) 0x40320EC4UL)
|
||||
#define CYREG_SMARTIO_PRT14_DATA ((volatile un_SMARTIO_PRT_DATA_t*) 0x40320EF0UL)
|
||||
|
||||
/**
|
||||
* \brief Programmable IO port registers (SMARTIO_PRT15)
|
||||
*/
|
||||
#define CYREG_SMARTIO_PRT15_CTL ((volatile un_SMARTIO_PRT_CTL_t*) 0x40320F00UL)
|
||||
#define CYREG_SMARTIO_PRT15_SYNC_CTL ((volatile un_SMARTIO_PRT_SYNC_CTL_t*) 0x40320F10UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_SEL0 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320F20UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_SEL1 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320F24UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_SEL2 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320F28UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_SEL3 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320F2CUL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_SEL4 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320F30UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_SEL5 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320F34UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_SEL6 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320F38UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_SEL7 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40320F3CUL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_CTL0 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320F40UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_CTL1 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320F44UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_CTL2 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320F48UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_CTL3 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320F4CUL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_CTL4 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320F50UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_CTL5 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320F54UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_CTL6 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320F58UL)
|
||||
#define CYREG_SMARTIO_PRT15_LUT_CTL7 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40320F5CUL)
|
||||
#define CYREG_SMARTIO_PRT15_DU_SEL ((volatile un_SMARTIO_PRT_DU_SEL_t*) 0x40320FC0UL)
|
||||
#define CYREG_SMARTIO_PRT15_DU_CTL ((volatile un_SMARTIO_PRT_DU_CTL_t*) 0x40320FC4UL)
|
||||
#define CYREG_SMARTIO_PRT15_DATA ((volatile un_SMARTIO_PRT_DATA_t*) 0x40320FF0UL)
|
||||
|
||||
/**
|
||||
* \brief Programmable IO port registers (SMARTIO_PRT17)
|
||||
*/
|
||||
#define CYREG_SMARTIO_PRT17_CTL ((volatile un_SMARTIO_PRT_CTL_t*) 0x40321100UL)
|
||||
#define CYREG_SMARTIO_PRT17_SYNC_CTL ((volatile un_SMARTIO_PRT_SYNC_CTL_t*) 0x40321110UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_SEL0 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40321120UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_SEL1 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40321124UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_SEL2 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40321128UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_SEL3 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x4032112CUL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_SEL4 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40321130UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_SEL5 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40321134UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_SEL6 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x40321138UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_SEL7 ((volatile un_SMARTIO_PRT_LUT_SEL_t*) 0x4032113CUL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_CTL0 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40321140UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_CTL1 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40321144UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_CTL2 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40321148UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_CTL3 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x4032114CUL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_CTL4 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40321150UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_CTL5 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40321154UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_CTL6 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x40321158UL)
|
||||
#define CYREG_SMARTIO_PRT17_LUT_CTL7 ((volatile un_SMARTIO_PRT_LUT_CTL_t*) 0x4032115CUL)
|
||||
#define CYREG_SMARTIO_PRT17_DU_SEL ((volatile un_SMARTIO_PRT_DU_SEL_t*) 0x403211C0UL)
|
||||
#define CYREG_SMARTIO_PRT17_DU_CTL ((volatile un_SMARTIO_PRT_DU_CTL_t*) 0x403211C4UL)
|
||||
#define CYREG_SMARTIO_PRT17_DATA ((volatile un_SMARTIO_PRT_DATA_t*) 0x403211F0UL)
|
||||
|
||||
#endif /* _CYREG_SMARTIO_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,106 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_smif.h
|
||||
*
|
||||
* \brief
|
||||
* SMIF register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_SMIF_H_
|
||||
#define _CYREG_SMIF_H_
|
||||
|
||||
#include "cyip_smif_v2.h"
|
||||
|
||||
/**
|
||||
* \brief Device (only used in XIP mode) (SMIF_DEVICE0)
|
||||
*/
|
||||
#define CYREG_SMIF0_DEVICE0_CTL ((volatile un_SMIF_DEVICE_CTL_t*) 0x40420800UL)
|
||||
#define CYREG_SMIF0_DEVICE0_ADDR ((volatile un_SMIF_DEVICE_ADDR_t*) 0x40420808UL)
|
||||
#define CYREG_SMIF0_DEVICE0_MASK ((volatile un_SMIF_DEVICE_MASK_t*) 0x4042080CUL)
|
||||
#define CYREG_SMIF0_DEVICE0_ADDR_CTL ((volatile un_SMIF_DEVICE_ADDR_CTL_t*) 0x40420820UL)
|
||||
#define CYREG_SMIF0_DEVICE0_RD_CMD_CTL ((volatile un_SMIF_DEVICE_RD_CMD_CTL_t*) 0x40420840UL)
|
||||
#define CYREG_SMIF0_DEVICE0_RD_ADDR_CTL ((volatile un_SMIF_DEVICE_RD_ADDR_CTL_t*) 0x40420844UL)
|
||||
#define CYREG_SMIF0_DEVICE0_RD_MODE_CTL ((volatile un_SMIF_DEVICE_RD_MODE_CTL_t*) 0x40420848UL)
|
||||
#define CYREG_SMIF0_DEVICE0_RD_DUMMY_CTL ((volatile un_SMIF_DEVICE_RD_DUMMY_CTL_t*) 0x4042084CUL)
|
||||
#define CYREG_SMIF0_DEVICE0_RD_DATA_CTL ((volatile un_SMIF_DEVICE_RD_DATA_CTL_t*) 0x40420850UL)
|
||||
#define CYREG_SMIF0_DEVICE0_RD_BOUND_CTL ((volatile un_SMIF_DEVICE_RD_BOUND_CTL_t*) 0x40420858UL)
|
||||
#define CYREG_SMIF0_DEVICE0_WR_CMD_CTL ((volatile un_SMIF_DEVICE_WR_CMD_CTL_t*) 0x40420860UL)
|
||||
#define CYREG_SMIF0_DEVICE0_WR_ADDR_CTL ((volatile un_SMIF_DEVICE_WR_ADDR_CTL_t*) 0x40420864UL)
|
||||
#define CYREG_SMIF0_DEVICE0_WR_MODE_CTL ((volatile un_SMIF_DEVICE_WR_MODE_CTL_t*) 0x40420868UL)
|
||||
#define CYREG_SMIF0_DEVICE0_WR_DUMMY_CTL ((volatile un_SMIF_DEVICE_WR_DUMMY_CTL_t*) 0x4042086CUL)
|
||||
#define CYREG_SMIF0_DEVICE0_WR_DATA_CTL ((volatile un_SMIF_DEVICE_WR_DATA_CTL_t*) 0x40420870UL)
|
||||
|
||||
/**
|
||||
* \brief Device (only used in XIP mode) (SMIF_DEVICE1)
|
||||
*/
|
||||
#define CYREG_SMIF0_DEVICE1_CTL ((volatile un_SMIF_DEVICE_CTL_t*) 0x40420880UL)
|
||||
#define CYREG_SMIF0_DEVICE1_ADDR ((volatile un_SMIF_DEVICE_ADDR_t*) 0x40420888UL)
|
||||
#define CYREG_SMIF0_DEVICE1_MASK ((volatile un_SMIF_DEVICE_MASK_t*) 0x4042088CUL)
|
||||
#define CYREG_SMIF0_DEVICE1_ADDR_CTL ((volatile un_SMIF_DEVICE_ADDR_CTL_t*) 0x404208A0UL)
|
||||
#define CYREG_SMIF0_DEVICE1_RD_CMD_CTL ((volatile un_SMIF_DEVICE_RD_CMD_CTL_t*) 0x404208C0UL)
|
||||
#define CYREG_SMIF0_DEVICE1_RD_ADDR_CTL ((volatile un_SMIF_DEVICE_RD_ADDR_CTL_t*) 0x404208C4UL)
|
||||
#define CYREG_SMIF0_DEVICE1_RD_MODE_CTL ((volatile un_SMIF_DEVICE_RD_MODE_CTL_t*) 0x404208C8UL)
|
||||
#define CYREG_SMIF0_DEVICE1_RD_DUMMY_CTL ((volatile un_SMIF_DEVICE_RD_DUMMY_CTL_t*) 0x404208CCUL)
|
||||
#define CYREG_SMIF0_DEVICE1_RD_DATA_CTL ((volatile un_SMIF_DEVICE_RD_DATA_CTL_t*) 0x404208D0UL)
|
||||
#define CYREG_SMIF0_DEVICE1_RD_BOUND_CTL ((volatile un_SMIF_DEVICE_RD_BOUND_CTL_t*) 0x404208D8UL)
|
||||
#define CYREG_SMIF0_DEVICE1_WR_CMD_CTL ((volatile un_SMIF_DEVICE_WR_CMD_CTL_t*) 0x404208E0UL)
|
||||
#define CYREG_SMIF0_DEVICE1_WR_ADDR_CTL ((volatile un_SMIF_DEVICE_WR_ADDR_CTL_t*) 0x404208E4UL)
|
||||
#define CYREG_SMIF0_DEVICE1_WR_MODE_CTL ((volatile un_SMIF_DEVICE_WR_MODE_CTL_t*) 0x404208E8UL)
|
||||
#define CYREG_SMIF0_DEVICE1_WR_DUMMY_CTL ((volatile un_SMIF_DEVICE_WR_DUMMY_CTL_t*) 0x404208ECUL)
|
||||
#define CYREG_SMIF0_DEVICE1_WR_DATA_CTL ((volatile un_SMIF_DEVICE_WR_DATA_CTL_t*) 0x404208F0UL)
|
||||
|
||||
/**
|
||||
* \brief Serial Memory Interface (SMIF0)
|
||||
*/
|
||||
#define CYREG_SMIF0_CTL ((volatile un_SMIF_CTL_t*) 0x40420000UL)
|
||||
#define CYREG_SMIF0_STATUS ((volatile un_SMIF_STATUS_t*) 0x40420004UL)
|
||||
#define CYREG_SMIF0_DELAY_TAP_SEL ((volatile un_SMIF_DELAY_TAP_SEL_t*) 0x40420030UL)
|
||||
#define CYREG_SMIF0_TX_CMD_FIFO_STATUS ((volatile un_SMIF_TX_CMD_FIFO_STATUS_t*) 0x40420044UL)
|
||||
#define CYREG_SMIF0_TX_CMD_FIFO_WR ((volatile un_SMIF_TX_CMD_FIFO_WR_t*) 0x40420050UL)
|
||||
#define CYREG_SMIF0_TX_DATA_FIFO_CTL ((volatile un_SMIF_TX_DATA_FIFO_CTL_t*) 0x40420080UL)
|
||||
#define CYREG_SMIF0_TX_DATA_FIFO_STATUS ((volatile un_SMIF_TX_DATA_FIFO_STATUS_t*) 0x40420084UL)
|
||||
#define CYREG_SMIF0_TX_DATA_FIFO_WR1 ((volatile un_SMIF_TX_DATA_FIFO_WR1_t*) 0x40420090UL)
|
||||
#define CYREG_SMIF0_TX_DATA_FIFO_WR2 ((volatile un_SMIF_TX_DATA_FIFO_WR2_t*) 0x40420094UL)
|
||||
#define CYREG_SMIF0_TX_DATA_FIFO_WR4 ((volatile un_SMIF_TX_DATA_FIFO_WR4_t*) 0x40420098UL)
|
||||
#define CYREG_SMIF0_TX_DATA_FIFO_WR1ODD ((volatile un_SMIF_TX_DATA_FIFO_WR1ODD_t*) 0x4042009CUL)
|
||||
#define CYREG_SMIF0_RX_DATA_MMIO_FIFO_CTL ((volatile un_SMIF_RX_DATA_MMIO_FIFO_CTL_t*) 0x404200C0UL)
|
||||
#define CYREG_SMIF0_RX_DATA_MMIO_FIFO_STATUS ((volatile un_SMIF_RX_DATA_MMIO_FIFO_STATUS_t*) 0x404200C4UL)
|
||||
#define CYREG_SMIF0_RX_DATA_FIFO_STATUS ((volatile un_SMIF_RX_DATA_FIFO_STATUS_t*) 0x404200C8UL)
|
||||
#define CYREG_SMIF0_RX_DATA_MMIO_FIFO_RD1 ((volatile un_SMIF_RX_DATA_MMIO_FIFO_RD1_t*) 0x404200D0UL)
|
||||
#define CYREG_SMIF0_RX_DATA_MMIO_FIFO_RD2 ((volatile un_SMIF_RX_DATA_MMIO_FIFO_RD2_t*) 0x404200D4UL)
|
||||
#define CYREG_SMIF0_RX_DATA_MMIO_FIFO_RD4 ((volatile un_SMIF_RX_DATA_MMIO_FIFO_RD4_t*) 0x404200D8UL)
|
||||
#define CYREG_SMIF0_RX_DATA_MMIO_FIFO_RD1_SILENT ((volatile un_SMIF_RX_DATA_MMIO_FIFO_RD1_SILENT_t*) 0x404200E0UL)
|
||||
#define CYREG_SMIF0_SLOW_CA_CTL ((volatile un_SMIF_SLOW_CA_CTL_t*) 0x40420100UL)
|
||||
#define CYREG_SMIF0_SLOW_CA_CMD ((volatile un_SMIF_SLOW_CA_CMD_t*) 0x40420108UL)
|
||||
#define CYREG_SMIF0_CRYPTO_CMD ((volatile un_SMIF_CRYPTO_CMD_t*) 0x40420200UL)
|
||||
#define CYREG_SMIF0_CRYPTO_INPUT0 ((volatile un_SMIF_CRYPTO_INPUT0_t*) 0x40420220UL)
|
||||
#define CYREG_SMIF0_CRYPTO_INPUT1 ((volatile un_SMIF_CRYPTO_INPUT1_t*) 0x40420224UL)
|
||||
#define CYREG_SMIF0_CRYPTO_INPUT2 ((volatile un_SMIF_CRYPTO_INPUT2_t*) 0x40420228UL)
|
||||
#define CYREG_SMIF0_CRYPTO_INPUT3 ((volatile un_SMIF_CRYPTO_INPUT3_t*) 0x4042022CUL)
|
||||
#define CYREG_SMIF0_CRYPTO_KEY0 ((volatile un_SMIF_CRYPTO_KEY0_t*) 0x40420240UL)
|
||||
#define CYREG_SMIF0_CRYPTO_KEY1 ((volatile un_SMIF_CRYPTO_KEY1_t*) 0x40420244UL)
|
||||
#define CYREG_SMIF0_CRYPTO_KEY2 ((volatile un_SMIF_CRYPTO_KEY2_t*) 0x40420248UL)
|
||||
#define CYREG_SMIF0_CRYPTO_KEY3 ((volatile un_SMIF_CRYPTO_KEY3_t*) 0x4042024CUL)
|
||||
#define CYREG_SMIF0_CRYPTO_OUTPUT0 ((volatile un_SMIF_CRYPTO_OUTPUT0_t*) 0x40420260UL)
|
||||
#define CYREG_SMIF0_CRYPTO_OUTPUT1 ((volatile un_SMIF_CRYPTO_OUTPUT1_t*) 0x40420264UL)
|
||||
#define CYREG_SMIF0_CRYPTO_OUTPUT2 ((volatile un_SMIF_CRYPTO_OUTPUT2_t*) 0x40420268UL)
|
||||
#define CYREG_SMIF0_CRYPTO_OUTPUT3 ((volatile un_SMIF_CRYPTO_OUTPUT3_t*) 0x4042026CUL)
|
||||
#define CYREG_SMIF0_INTR ((volatile un_SMIF_INTR_t*) 0x404207C0UL)
|
||||
#define CYREG_SMIF0_INTR_SET ((volatile un_SMIF_INTR_SET_t*) 0x404207C4UL)
|
||||
#define CYREG_SMIF0_INTR_MASK ((volatile un_SMIF_INTR_MASK_t*) 0x404207C8UL)
|
||||
#define CYREG_SMIF0_INTR_MASKED ((volatile un_SMIF_INTR_MASKED_t*) 0x404207CCUL)
|
||||
|
||||
#endif /* _CYREG_SMIF_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
@@ -0,0 +1,313 @@
|
||||
/***************************************************************************//**
|
||||
* \file cyreg_srss.h
|
||||
*
|
||||
* \brief
|
||||
* SRSS register definition header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYREG_SRSS_H_
|
||||
#define _CYREG_SRSS_H_
|
||||
|
||||
#include "cyip_srss_v3.h"
|
||||
|
||||
/**
|
||||
* \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV0)
|
||||
*/
|
||||
#define CYREG_CSV_HF_CSV0_REF_CTL ((volatile un_CSV_HF_CSV_REF_CTL_t*) 0x40261400UL)
|
||||
#define CYREG_CSV_HF_CSV0_REF_LIMIT ((volatile un_CSV_HF_CSV_REF_LIMIT_t*) 0x40261404UL)
|
||||
#define CYREG_CSV_HF_CSV0_MON_CTL ((volatile un_CSV_HF_CSV_MON_CTL_t*) 0x40261408UL)
|
||||
|
||||
/**
|
||||
* \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV1)
|
||||
*/
|
||||
#define CYREG_CSV_HF_CSV1_REF_CTL ((volatile un_CSV_HF_CSV_REF_CTL_t*) 0x40261410UL)
|
||||
#define CYREG_CSV_HF_CSV1_REF_LIMIT ((volatile un_CSV_HF_CSV_REF_LIMIT_t*) 0x40261414UL)
|
||||
#define CYREG_CSV_HF_CSV1_MON_CTL ((volatile un_CSV_HF_CSV_MON_CTL_t*) 0x40261418UL)
|
||||
|
||||
/**
|
||||
* \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV2)
|
||||
*/
|
||||
#define CYREG_CSV_HF_CSV2_REF_CTL ((volatile un_CSV_HF_CSV_REF_CTL_t*) 0x40261420UL)
|
||||
#define CYREG_CSV_HF_CSV2_REF_LIMIT ((volatile un_CSV_HF_CSV_REF_LIMIT_t*) 0x40261424UL)
|
||||
#define CYREG_CSV_HF_CSV2_MON_CTL ((volatile un_CSV_HF_CSV_MON_CTL_t*) 0x40261428UL)
|
||||
|
||||
/**
|
||||
* \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV3)
|
||||
*/
|
||||
#define CYREG_CSV_HF_CSV3_REF_CTL ((volatile un_CSV_HF_CSV_REF_CTL_t*) 0x40261430UL)
|
||||
#define CYREG_CSV_HF_CSV3_REF_LIMIT ((volatile un_CSV_HF_CSV_REF_LIMIT_t*) 0x40261434UL)
|
||||
#define CYREG_CSV_HF_CSV3_MON_CTL ((volatile un_CSV_HF_CSV_MON_CTL_t*) 0x40261438UL)
|
||||
|
||||
/**
|
||||
* \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV4)
|
||||
*/
|
||||
#define CYREG_CSV_HF_CSV4_REF_CTL ((volatile un_CSV_HF_CSV_REF_CTL_t*) 0x40261440UL)
|
||||
#define CYREG_CSV_HF_CSV4_REF_LIMIT ((volatile un_CSV_HF_CSV_REF_LIMIT_t*) 0x40261444UL)
|
||||
#define CYREG_CSV_HF_CSV4_MON_CTL ((volatile un_CSV_HF_CSV_MON_CTL_t*) 0x40261448UL)
|
||||
|
||||
/**
|
||||
* \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV5)
|
||||
*/
|
||||
#define CYREG_CSV_HF_CSV5_REF_CTL ((volatile un_CSV_HF_CSV_REF_CTL_t*) 0x40261450UL)
|
||||
#define CYREG_CSV_HF_CSV5_REF_LIMIT ((volatile un_CSV_HF_CSV_REF_LIMIT_t*) 0x40261454UL)
|
||||
#define CYREG_CSV_HF_CSV5_MON_CTL ((volatile un_CSV_HF_CSV_MON_CTL_t*) 0x40261458UL)
|
||||
|
||||
/**
|
||||
* \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV6)
|
||||
*/
|
||||
#define CYREG_CSV_HF_CSV6_REF_CTL ((volatile un_CSV_HF_CSV_REF_CTL_t*) 0x40261460UL)
|
||||
#define CYREG_CSV_HF_CSV6_REF_LIMIT ((volatile un_CSV_HF_CSV_REF_LIMIT_t*) 0x40261464UL)
|
||||
#define CYREG_CSV_HF_CSV6_MON_CTL ((volatile un_CSV_HF_CSV_MON_CTL_t*) 0x40261468UL)
|
||||
|
||||
/**
|
||||
* \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV7)
|
||||
*/
|
||||
#define CYREG_CSV_HF_CSV7_REF_CTL ((volatile un_CSV_HF_CSV_REF_CTL_t*) 0x40261470UL)
|
||||
#define CYREG_CSV_HF_CSV7_REF_LIMIT ((volatile un_CSV_HF_CSV_REF_LIMIT_t*) 0x40261474UL)
|
||||
#define CYREG_CSV_HF_CSV7_MON_CTL ((volatile un_CSV_HF_CSV_MON_CTL_t*) 0x40261478UL)
|
||||
|
||||
/**
|
||||
* \brief Active domain Clock Supervisor (CSV) registers for CSV Reference clock (CSV_REF_CSV0)
|
||||
*/
|
||||
#define CYREG_CSV_REF_CSV_REF_CTL ((volatile un_CSV_REF_CSV_REF_CTL_t*) 0x40261710UL)
|
||||
#define CYREG_CSV_REF_CSV_REF_LIMIT ((volatile un_CSV_REF_CSV_REF_LIMIT_t*) 0x40261714UL)
|
||||
#define CYREG_CSV_REF_CSV_MON_CTL ((volatile un_CSV_REF_CSV_MON_CTL_t*) 0x40261718UL)
|
||||
|
||||
/**
|
||||
* \brief LF clock Clock Supervisor registers (CSV_LF_CSV0)
|
||||
*/
|
||||
#define CYREG_CSV_LF_CSV_REF_CTL ((volatile un_CSV_LF_CSV_REF_CTL_t*) 0x40261720UL)
|
||||
#define CYREG_CSV_LF_CSV_REF_LIMIT ((volatile un_CSV_LF_CSV_REF_LIMIT_t*) 0x40261724UL)
|
||||
#define CYREG_CSV_LF_CSV_MON_CTL ((volatile un_CSV_LF_CSV_MON_CTL_t*) 0x40261728UL)
|
||||
|
||||
/**
|
||||
* \brief HVILO clock DeepSleep domain Clock Supervisor registers (CSV_ILO_CSV0)
|
||||
*/
|
||||
#define CYREG_CSV_ILO_CSV_REF_CTL ((volatile un_CSV_ILO_CSV_REF_CTL_t*) 0x40261730UL)
|
||||
#define CYREG_CSV_ILO_CSV_REF_LIMIT ((volatile un_CSV_ILO_CSV_REF_LIMIT_t*) 0x40261734UL)
|
||||
#define CYREG_CSV_ILO_CSV_MON_CTL ((volatile un_CSV_ILO_CSV_MON_CTL_t*) 0x40261738UL)
|
||||
|
||||
/**
|
||||
* \brief 400MHz PLL Configuration Register (CLK_PLL400M0)
|
||||
*/
|
||||
#define CYREG_CLK_PLL400M0_CONFIG ((volatile un_CLK_PLL400M_CONFIG_t*) 0x40261900UL)
|
||||
#define CYREG_CLK_PLL400M0_CONFIG2 ((volatile un_CLK_PLL400M_CONFIG2_t*) 0x40261904UL)
|
||||
#define CYREG_CLK_PLL400M0_CONFIG3 ((volatile un_CLK_PLL400M_CONFIG3_t*) 0x40261908UL)
|
||||
#define CYREG_CLK_PLL400M0_STATUS ((volatile un_CLK_PLL400M_STATUS_t*) 0x4026190CUL)
|
||||
|
||||
/**
|
||||
* \brief 400MHz PLL Configuration Register (CLK_PLL400M1)
|
||||
*/
|
||||
#define CYREG_CLK_PLL400M1_CONFIG ((volatile un_CLK_PLL400M_CONFIG_t*) 0x40261910UL)
|
||||
#define CYREG_CLK_PLL400M1_CONFIG2 ((volatile un_CLK_PLL400M_CONFIG2_t*) 0x40261914UL)
|
||||
#define CYREG_CLK_PLL400M1_CONFIG3 ((volatile un_CLK_PLL400M_CONFIG3_t*) 0x40261918UL)
|
||||
#define CYREG_CLK_PLL400M1_STATUS ((volatile un_CLK_PLL400M_STATUS_t*) 0x4026191CUL)
|
||||
|
||||
/**
|
||||
* \brief MCWDT Configuration for Subcounter 0 and 1 (MCWDT_CTR0)
|
||||
*/
|
||||
#define CYREG_MCWDT0_CTR0_CTL ((volatile un_MCWDT_CTR_CTL_t*) 0x40268000UL)
|
||||
#define CYREG_MCWDT0_CTR0_LOWER_LIMIT ((volatile un_MCWDT_CTR_LOWER_LIMIT_t*) 0x40268004UL)
|
||||
#define CYREG_MCWDT0_CTR0_UPPER_LIMIT ((volatile un_MCWDT_CTR_UPPER_LIMIT_t*) 0x40268008UL)
|
||||
#define CYREG_MCWDT0_CTR0_WARN_LIMIT ((volatile un_MCWDT_CTR_WARN_LIMIT_t*) 0x4026800CUL)
|
||||
#define CYREG_MCWDT0_CTR0_CONFIG ((volatile un_MCWDT_CTR_CONFIG_t*) 0x40268010UL)
|
||||
#define CYREG_MCWDT0_CTR0_CNT ((volatile un_MCWDT_CTR_CNT_t*) 0x40268014UL)
|
||||
|
||||
/**
|
||||
* \brief MCWDT Configuration for Subcounter 0 and 1 (MCWDT_CTR1)
|
||||
*/
|
||||
#define CYREG_MCWDT0_CTR1_CTL ((volatile un_MCWDT_CTR_CTL_t*) 0x40268020UL)
|
||||
#define CYREG_MCWDT0_CTR1_LOWER_LIMIT ((volatile un_MCWDT_CTR_LOWER_LIMIT_t*) 0x40268024UL)
|
||||
#define CYREG_MCWDT0_CTR1_UPPER_LIMIT ((volatile un_MCWDT_CTR_UPPER_LIMIT_t*) 0x40268028UL)
|
||||
#define CYREG_MCWDT0_CTR1_WARN_LIMIT ((volatile un_MCWDT_CTR_WARN_LIMIT_t*) 0x4026802CUL)
|
||||
#define CYREG_MCWDT0_CTR1_CONFIG ((volatile un_MCWDT_CTR_CONFIG_t*) 0x40268030UL)
|
||||
#define CYREG_MCWDT0_CTR1_CNT ((volatile un_MCWDT_CTR_CNT_t*) 0x40268034UL)
|
||||
|
||||
/**
|
||||
* \brief Multi-Counter Watchdog Timer (MCWDT0)
|
||||
*/
|
||||
#define CYREG_MCWDT0_CPU_SELECT ((volatile un_MCWDT_CPU_SELECT_t*) 0x40268040UL)
|
||||
#define CYREG_MCWDT0_CTR2_CTL ((volatile un_MCWDT_CTR2_CTL_t*) 0x40268080UL)
|
||||
#define CYREG_MCWDT0_CTR2_CONFIG ((volatile un_MCWDT_CTR2_CONFIG_t*) 0x40268084UL)
|
||||
#define CYREG_MCWDT0_CTR2_CNT ((volatile un_MCWDT_CTR2_CNT_t*) 0x40268088UL)
|
||||
#define CYREG_MCWDT0_LOCK ((volatile un_MCWDT_LOCK_t*) 0x40268090UL)
|
||||
#define CYREG_MCWDT0_SERVICE ((volatile un_MCWDT_SERVICE_t*) 0x40268094UL)
|
||||
#define CYREG_MCWDT0_INTR ((volatile un_MCWDT_INTR_t*) 0x402680A0UL)
|
||||
#define CYREG_MCWDT0_INTR_SET ((volatile un_MCWDT_INTR_SET_t*) 0x402680A4UL)
|
||||
#define CYREG_MCWDT0_INTR_MASK ((volatile un_MCWDT_INTR_MASK_t*) 0x402680A8UL)
|
||||
#define CYREG_MCWDT0_INTR_MASKED ((volatile un_MCWDT_INTR_MASKED_t*) 0x402680ACUL)
|
||||
|
||||
/**
|
||||
* \brief MCWDT Configuration for Subcounter 0 and 1 (MCWDT_CTR0)
|
||||
*/
|
||||
#define CYREG_MCWDT1_CTR0_CTL ((volatile un_MCWDT_CTR_CTL_t*) 0x40268100UL)
|
||||
#define CYREG_MCWDT1_CTR0_LOWER_LIMIT ((volatile un_MCWDT_CTR_LOWER_LIMIT_t*) 0x40268104UL)
|
||||
#define CYREG_MCWDT1_CTR0_UPPER_LIMIT ((volatile un_MCWDT_CTR_UPPER_LIMIT_t*) 0x40268108UL)
|
||||
#define CYREG_MCWDT1_CTR0_WARN_LIMIT ((volatile un_MCWDT_CTR_WARN_LIMIT_t*) 0x4026810CUL)
|
||||
#define CYREG_MCWDT1_CTR0_CONFIG ((volatile un_MCWDT_CTR_CONFIG_t*) 0x40268110UL)
|
||||
#define CYREG_MCWDT1_CTR0_CNT ((volatile un_MCWDT_CTR_CNT_t*) 0x40268114UL)
|
||||
|
||||
/**
|
||||
* \brief MCWDT Configuration for Subcounter 0 and 1 (MCWDT_CTR1)
|
||||
*/
|
||||
#define CYREG_MCWDT1_CTR1_CTL ((volatile un_MCWDT_CTR_CTL_t*) 0x40268120UL)
|
||||
#define CYREG_MCWDT1_CTR1_LOWER_LIMIT ((volatile un_MCWDT_CTR_LOWER_LIMIT_t*) 0x40268124UL)
|
||||
#define CYREG_MCWDT1_CTR1_UPPER_LIMIT ((volatile un_MCWDT_CTR_UPPER_LIMIT_t*) 0x40268128UL)
|
||||
#define CYREG_MCWDT1_CTR1_WARN_LIMIT ((volatile un_MCWDT_CTR_WARN_LIMIT_t*) 0x4026812CUL)
|
||||
#define CYREG_MCWDT1_CTR1_CONFIG ((volatile un_MCWDT_CTR_CONFIG_t*) 0x40268130UL)
|
||||
#define CYREG_MCWDT1_CTR1_CNT ((volatile un_MCWDT_CTR_CNT_t*) 0x40268134UL)
|
||||
|
||||
/**
|
||||
* \brief Multi-Counter Watchdog Timer (MCWDT1)
|
||||
*/
|
||||
#define CYREG_MCWDT1_CPU_SELECT ((volatile un_MCWDT_CPU_SELECT_t*) 0x40268140UL)
|
||||
#define CYREG_MCWDT1_CTR2_CTL ((volatile un_MCWDT_CTR2_CTL_t*) 0x40268180UL)
|
||||
#define CYREG_MCWDT1_CTR2_CONFIG ((volatile un_MCWDT_CTR2_CONFIG_t*) 0x40268184UL)
|
||||
#define CYREG_MCWDT1_CTR2_CNT ((volatile un_MCWDT_CTR2_CNT_t*) 0x40268188UL)
|
||||
#define CYREG_MCWDT1_LOCK ((volatile un_MCWDT_LOCK_t*) 0x40268190UL)
|
||||
#define CYREG_MCWDT1_SERVICE ((volatile un_MCWDT_SERVICE_t*) 0x40268194UL)
|
||||
#define CYREG_MCWDT1_INTR ((volatile un_MCWDT_INTR_t*) 0x402681A0UL)
|
||||
#define CYREG_MCWDT1_INTR_SET ((volatile un_MCWDT_INTR_SET_t*) 0x402681A4UL)
|
||||
#define CYREG_MCWDT1_INTR_MASK ((volatile un_MCWDT_INTR_MASK_t*) 0x402681A8UL)
|
||||
#define CYREG_MCWDT1_INTR_MASKED ((volatile un_MCWDT_INTR_MASKED_t*) 0x402681ACUL)
|
||||
|
||||
/**
|
||||
* \brief MCWDT Configuration for Subcounter 0 and 1 (MCWDT_CTR0)
|
||||
*/
|
||||
#define CYREG_MCWDT2_CTR0_CTL ((volatile un_MCWDT_CTR_CTL_t*) 0x40268200UL)
|
||||
#define CYREG_MCWDT2_CTR0_LOWER_LIMIT ((volatile un_MCWDT_CTR_LOWER_LIMIT_t*) 0x40268204UL)
|
||||
#define CYREG_MCWDT2_CTR0_UPPER_LIMIT ((volatile un_MCWDT_CTR_UPPER_LIMIT_t*) 0x40268208UL)
|
||||
#define CYREG_MCWDT2_CTR0_WARN_LIMIT ((volatile un_MCWDT_CTR_WARN_LIMIT_t*) 0x4026820CUL)
|
||||
#define CYREG_MCWDT2_CTR0_CONFIG ((volatile un_MCWDT_CTR_CONFIG_t*) 0x40268210UL)
|
||||
#define CYREG_MCWDT2_CTR0_CNT ((volatile un_MCWDT_CTR_CNT_t*) 0x40268214UL)
|
||||
|
||||
/**
|
||||
* \brief MCWDT Configuration for Subcounter 0 and 1 (MCWDT_CTR1)
|
||||
*/
|
||||
#define CYREG_MCWDT2_CTR1_CTL ((volatile un_MCWDT_CTR_CTL_t*) 0x40268220UL)
|
||||
#define CYREG_MCWDT2_CTR1_LOWER_LIMIT ((volatile un_MCWDT_CTR_LOWER_LIMIT_t*) 0x40268224UL)
|
||||
#define CYREG_MCWDT2_CTR1_UPPER_LIMIT ((volatile un_MCWDT_CTR_UPPER_LIMIT_t*) 0x40268228UL)
|
||||
#define CYREG_MCWDT2_CTR1_WARN_LIMIT ((volatile un_MCWDT_CTR_WARN_LIMIT_t*) 0x4026822CUL)
|
||||
#define CYREG_MCWDT2_CTR1_CONFIG ((volatile un_MCWDT_CTR_CONFIG_t*) 0x40268230UL)
|
||||
#define CYREG_MCWDT2_CTR1_CNT ((volatile un_MCWDT_CTR_CNT_t*) 0x40268234UL)
|
||||
|
||||
/**
|
||||
* \brief Multi-Counter Watchdog Timer (MCWDT2)
|
||||
*/
|
||||
#define CYREG_MCWDT2_CPU_SELECT ((volatile un_MCWDT_CPU_SELECT_t*) 0x40268240UL)
|
||||
#define CYREG_MCWDT2_CTR2_CTL ((volatile un_MCWDT_CTR2_CTL_t*) 0x40268280UL)
|
||||
#define CYREG_MCWDT2_CTR2_CONFIG ((volatile un_MCWDT_CTR2_CONFIG_t*) 0x40268284UL)
|
||||
#define CYREG_MCWDT2_CTR2_CNT ((volatile un_MCWDT_CTR2_CNT_t*) 0x40268288UL)
|
||||
#define CYREG_MCWDT2_LOCK ((volatile un_MCWDT_LOCK_t*) 0x40268290UL)
|
||||
#define CYREG_MCWDT2_SERVICE ((volatile un_MCWDT_SERVICE_t*) 0x40268294UL)
|
||||
#define CYREG_MCWDT2_INTR ((volatile un_MCWDT_INTR_t*) 0x402682A0UL)
|
||||
#define CYREG_MCWDT2_INTR_SET ((volatile un_MCWDT_INTR_SET_t*) 0x402682A4UL)
|
||||
#define CYREG_MCWDT2_INTR_MASK ((volatile un_MCWDT_INTR_MASK_t*) 0x402682A8UL)
|
||||
#define CYREG_MCWDT2_INTR_MASKED ((volatile un_MCWDT_INTR_MASKED_t*) 0x402682ACUL)
|
||||
|
||||
/**
|
||||
* \brief Watchdog Timer (WDT0)
|
||||
*/
|
||||
#define CYREG_WDT_CTL ((volatile un_WDT_CTL_t*) 0x4026C000UL)
|
||||
#define CYREG_WDT_LOWER_LIMIT ((volatile un_WDT_LOWER_LIMIT_t*) 0x4026C004UL)
|
||||
#define CYREG_WDT_UPPER_LIMIT ((volatile un_WDT_UPPER_LIMIT_t*) 0x4026C008UL)
|
||||
#define CYREG_WDT_WARN_LIMIT ((volatile un_WDT_WARN_LIMIT_t*) 0x4026C00CUL)
|
||||
#define CYREG_WDT_CONFIG ((volatile un_WDT_CONFIG_t*) 0x4026C010UL)
|
||||
#define CYREG_WDT_CNT ((volatile un_WDT_CNT_t*) 0x4026C014UL)
|
||||
#define CYREG_WDT_LOCK ((volatile un_WDT_LOCK_t*) 0x4026C040UL)
|
||||
#define CYREG_WDT_SERVICE ((volatile un_WDT_SERVICE_t*) 0x4026C044UL)
|
||||
#define CYREG_WDT_INTR ((volatile un_WDT_INTR_t*) 0x4026C050UL)
|
||||
#define CYREG_WDT_INTR_SET ((volatile un_WDT_INTR_SET_t*) 0x4026C054UL)
|
||||
#define CYREG_WDT_INTR_MASK ((volatile un_WDT_INTR_MASK_t*) 0x4026C058UL)
|
||||
#define CYREG_WDT_INTR_MASKED ((volatile un_WDT_INTR_MASKED_t*) 0x4026C05CUL)
|
||||
|
||||
/**
|
||||
* \brief SRSS Core Registers (ver3) (SRSS0)
|
||||
*/
|
||||
#define CYREG_PWR_LVD_STATUS ((volatile un_PWR_LVD_STATUS_t*) 0x40260040UL)
|
||||
#define CYREG_PWR_LVD_STATUS2 ((volatile un_PWR_LVD_STATUS2_t*) 0x40260044UL)
|
||||
#define CYREG_CLK_DSI_SELECT0 ((volatile un_CLK_DSI_SELECT_t*) 0x40260100UL)
|
||||
#define CYREG_CLK_DSI_SELECT1 ((volatile un_CLK_DSI_SELECT_t*) 0x40260104UL)
|
||||
#define CYREG_CLK_DSI_SELECT2 ((volatile un_CLK_DSI_SELECT_t*) 0x40260108UL)
|
||||
#define CYREG_CLK_DSI_SELECT3 ((volatile un_CLK_DSI_SELECT_t*) 0x4026010CUL)
|
||||
#define CYREG_CLK_DSI_SELECT4 ((volatile un_CLK_DSI_SELECT_t*) 0x40260110UL)
|
||||
#define CYREG_CLK_DSI_SELECT5 ((volatile un_CLK_DSI_SELECT_t*) 0x40260114UL)
|
||||
#define CYREG_CLK_DSI_SELECT6 ((volatile un_CLK_DSI_SELECT_t*) 0x40260118UL)
|
||||
#define CYREG_CLK_OUTPUT_FAST ((volatile un_CLK_OUTPUT_FAST_t*) 0x40260140UL)
|
||||
#define CYREG_CLK_OUTPUT_SLOW ((volatile un_CLK_OUTPUT_SLOW_t*) 0x40260144UL)
|
||||
#define CYREG_CLK_CAL_CNT1 ((volatile un_CLK_CAL_CNT1_t*) 0x40260148UL)
|
||||
#define CYREG_CLK_CAL_CNT2 ((volatile un_CLK_CAL_CNT2_t*) 0x4026014CUL)
|
||||
#define CYREG_SRSS_INTR ((volatile un_SRSS_INTR_t*) 0x40260200UL)
|
||||
#define CYREG_SRSS_INTR_SET ((volatile un_SRSS_INTR_SET_t*) 0x40260204UL)
|
||||
#define CYREG_SRSS_INTR_MASK ((volatile un_SRSS_INTR_MASK_t*) 0x40260208UL)
|
||||
#define CYREG_SRSS_INTR_MASKED ((volatile un_SRSS_INTR_MASKED_t*) 0x4026020CUL)
|
||||
#define CYREG_PWR_CTL ((volatile un_PWR_CTL_t*) 0x40261000UL)
|
||||
#define CYREG_PWR_CTL2 ((volatile un_PWR_CTL2_t*) 0x40261004UL)
|
||||
#define CYREG_PWR_HIBERNATE ((volatile un_PWR_HIBERNATE_t*) 0x40261008UL)
|
||||
#define CYREG_PWR_SSV_CTL ((volatile un_PWR_SSV_CTL_t*) 0x40261018UL)
|
||||
#define CYREG_PWR_SSV_STATUS ((volatile un_PWR_SSV_STATUS_t*) 0x4026101CUL)
|
||||
#define CYREG_PWR_LVD_CTL ((volatile un_PWR_LVD_CTL_t*) 0x40261020UL)
|
||||
#define CYREG_PWR_LVD_CTL2 ((volatile un_PWR_LVD_CTL2_t*) 0x40261024UL)
|
||||
#define CYREG_PWR_REGHC_CTL ((volatile un_PWR_REGHC_CTL_t*) 0x40261028UL)
|
||||
#define CYREG_PWR_REGHC_STATUS ((volatile un_PWR_REGHC_STATUS_t*) 0x4026102CUL)
|
||||
#define CYREG_PWR_REGHC_CTL2 ((volatile un_PWR_REGHC_CTL2_t*) 0x40261030UL)
|
||||
#define CYREG_PWR_REGHC_CTL4 ((volatile un_PWR_REGHC_CTL4_t*) 0x40261038UL)
|
||||
#define CYREG_PWR_HIB_DATA0 ((volatile un_PWR_HIB_DATA_t*) 0x40261040UL)
|
||||
#define CYREG_CLK_PATH_SELECT0 ((volatile un_CLK_PATH_SELECT_t*) 0x40261200UL)
|
||||
#define CYREG_CLK_PATH_SELECT1 ((volatile un_CLK_PATH_SELECT_t*) 0x40261204UL)
|
||||
#define CYREG_CLK_PATH_SELECT2 ((volatile un_CLK_PATH_SELECT_t*) 0x40261208UL)
|
||||
#define CYREG_CLK_PATH_SELECT3 ((volatile un_CLK_PATH_SELECT_t*) 0x4026120CUL)
|
||||
#define CYREG_CLK_PATH_SELECT4 ((volatile un_CLK_PATH_SELECT_t*) 0x40261210UL)
|
||||
#define CYREG_CLK_PATH_SELECT5 ((volatile un_CLK_PATH_SELECT_t*) 0x40261214UL)
|
||||
#define CYREG_CLK_PATH_SELECT6 ((volatile un_CLK_PATH_SELECT_t*) 0x40261218UL)
|
||||
#define CYREG_CLK_ROOT_SELECT0 ((volatile un_CLK_ROOT_SELECT_t*) 0x40261240UL)
|
||||
#define CYREG_CLK_ROOT_SELECT1 ((volatile un_CLK_ROOT_SELECT_t*) 0x40261244UL)
|
||||
#define CYREG_CLK_ROOT_SELECT2 ((volatile un_CLK_ROOT_SELECT_t*) 0x40261248UL)
|
||||
#define CYREG_CLK_ROOT_SELECT3 ((volatile un_CLK_ROOT_SELECT_t*) 0x4026124CUL)
|
||||
#define CYREG_CLK_ROOT_SELECT4 ((volatile un_CLK_ROOT_SELECT_t*) 0x40261250UL)
|
||||
#define CYREG_CLK_ROOT_SELECT5 ((volatile un_CLK_ROOT_SELECT_t*) 0x40261254UL)
|
||||
#define CYREG_CLK_ROOT_SELECT6 ((volatile un_CLK_ROOT_SELECT_t*) 0x40261258UL)
|
||||
#define CYREG_CLK_ROOT_SELECT7 ((volatile un_CLK_ROOT_SELECT_t*) 0x4026125CUL)
|
||||
#define CYREG_CLK_SELECT ((volatile un_CLK_SELECT_t*) 0x40261500UL)
|
||||
#define CYREG_CLK_TIMER_CTL ((volatile un_CLK_TIMER_CTL_t*) 0x40261504UL)
|
||||
#define CYREG_CLK_ILO0_CONFIG ((volatile un_CLK_ILO0_CONFIG_t*) 0x40261508UL)
|
||||
#define CYREG_CLK_ILO1_CONFIG ((volatile un_CLK_ILO1_CONFIG_t*) 0x4026150CUL)
|
||||
#define CYREG_CLK_IMO_CONFIG ((volatile un_CLK_IMO_CONFIG_t*) 0x40261518UL)
|
||||
#define CYREG_CLK_ECO_CONFIG ((volatile un_CLK_ECO_CONFIG_t*) 0x4026151CUL)
|
||||
#define CYREG_CLK_ECO_PRESCALE ((volatile un_CLK_ECO_PRESCALE_t*) 0x40261520UL)
|
||||
#define CYREG_CLK_ECO_STATUS ((volatile un_CLK_ECO_STATUS_t*) 0x40261524UL)
|
||||
#define CYREG_CLK_FLL_CONFIG ((volatile un_CLK_FLL_CONFIG_t*) 0x40261530UL)
|
||||
#define CYREG_CLK_FLL_CONFIG2 ((volatile un_CLK_FLL_CONFIG2_t*) 0x40261534UL)
|
||||
#define CYREG_CLK_FLL_CONFIG3 ((volatile un_CLK_FLL_CONFIG3_t*) 0x40261538UL)
|
||||
#define CYREG_CLK_FLL_CONFIG4 ((volatile un_CLK_FLL_CONFIG4_t*) 0x4026153CUL)
|
||||
#define CYREG_CLK_FLL_STATUS ((volatile un_CLK_FLL_STATUS_t*) 0x40261540UL)
|
||||
#define CYREG_CLK_ECO_CONFIG2 ((volatile un_CLK_ECO_CONFIG2_t*) 0x40261544UL)
|
||||
#define CYREG_CLK_PLL_CONFIG0 ((volatile un_CLK_PLL_CONFIG_t*) 0x40261600UL)
|
||||
#define CYREG_CLK_PLL_CONFIG1 ((volatile un_CLK_PLL_CONFIG_t*) 0x40261604UL)
|
||||
#define CYREG_CLK_PLL_STATUS0 ((volatile un_CLK_PLL_STATUS_t*) 0x40261640UL)
|
||||
#define CYREG_CLK_PLL_STATUS1 ((volatile un_CLK_PLL_STATUS_t*) 0x40261644UL)
|
||||
#define CYREG_CSV_REF_SEL ((volatile un_CSV_REF_SEL_t*) 0x40261700UL)
|
||||
#define CYREG_RES_CAUSE ((volatile un_RES_CAUSE_t*) 0x40261800UL)
|
||||
#define CYREG_RES_CAUSE2 ((volatile un_RES_CAUSE2_t*) 0x40261804UL)
|
||||
#define CYREG_TST_XRES_KEY ((volatile un_TST_XRES_KEY_t*) 0x40262050UL)
|
||||
#define CYREG_TST_XRES_SECURE ((volatile un_TST_XRES_SECURE_t*) 0x40262054UL)
|
||||
#define CYREG_RES_PXRES_CTL ((volatile un_RES_PXRES_CTL_t*) 0x4026207CUL)
|
||||
#define CYREG_PWR_TRIM_WAKE_CTL ((volatile un_PWR_TRIM_WAKE_CTL_t*) 0x40263008UL)
|
||||
#define CYREG_CLK_TRIM_ILO0_CTL ((volatile un_CLK_TRIM_ILO0_CTL_t*) 0x40263014UL)
|
||||
#define CYREG_CLK_TRIM_ILO1_CTL ((volatile un_CLK_TRIM_ILO1_CTL_t*) 0x40263220UL)
|
||||
|
||||
#endif /* _CYREG_SRSS_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,57 @@
|
||||
/***************************************************************************//**
|
||||
* \file mcureg.h
|
||||
*
|
||||
* \brief
|
||||
* Common register header file.
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1277
|
||||
* Database revision: TVIIBH8M_B0_CFR_WW1922
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _MCUREG_H_
|
||||
#define _MCUREG_H_
|
||||
|
||||
#include "cyreg_sflash.h"
|
||||
#include "cyreg_peri.h"
|
||||
#include "cyreg_peri_ms.h"
|
||||
#include "cyreg_peri_pclk.h"
|
||||
#include "cyreg_crypto.h"
|
||||
#include "cyreg_cpuss.h"
|
||||
#include "cyreg_fault.h"
|
||||
#include "cyreg_ipc.h"
|
||||
#include "cyreg_prot.h"
|
||||
#include "cyreg_flashc.h"
|
||||
#include "cyreg_srss.h"
|
||||
#include "cyreg_backup.h"
|
||||
#include "cyreg_dw.h"
|
||||
#include "cyreg_dmac.h"
|
||||
#include "cyreg_efuse.h"
|
||||
#include "cyreg_efuse_data.h"
|
||||
#include "cyreg_hsiom.h"
|
||||
#include "cyreg_gpio.h"
|
||||
#include "cyreg_smartio.h"
|
||||
#include "cyreg_tcpwm.h"
|
||||
#include "cyreg_evtgen.h"
|
||||
#include "cyreg_smif.h"
|
||||
#include "cyreg_sdhc.h"
|
||||
#include "cyreg_eth.h"
|
||||
#include "cyreg_lin.h"
|
||||
#include "cyreg_canfd.h"
|
||||
#include "cyreg_flexray.h"
|
||||
#include "cyreg_tcpwm.h"
|
||||
#include "cyreg_scb.h"
|
||||
#include "cyreg_i2s.h"
|
||||
#include "cyreg_pass.h"
|
||||
|
||||
#endif /* _MCUREG_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,55 @@
|
||||
/***************************************************************************//**
|
||||
* \file cy_device_headers.h
|
||||
*
|
||||
* \brief
|
||||
* Common header file to be included by the drivers.
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.5.0.1299
|
||||
* Database revision: TVIIBH8M_WW1940_B1_CFR
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* You may use this file only in accordance with the license, terms, conditions,
|
||||
* disclaimers, and limitations in the end user license agreement accompanying
|
||||
* the software package with which this file was provided.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY_DEVICE_HEADERS_H_
|
||||
#define _CY_DEVICE_HEADERS_H_
|
||||
|
||||
#if defined (CYT4BF8CES)
|
||||
#include "cyt4bf8ces.h"
|
||||
#elif defined (CYT4BF8CEE)
|
||||
#include "cyt4bf8cee.h"
|
||||
#elif defined (CYT4BF8CDS)
|
||||
#include "cyt4bf8cds.h"
|
||||
#elif defined (CYT4BF8CDE)
|
||||
#include "cyt4bf8cde.h"
|
||||
#elif defined (CYT4BFBCJS)
|
||||
#include "cyt4bfbcjs.h"
|
||||
#elif defined (CYT4BFBCJE)
|
||||
#include "cyt4bfbcje.h"
|
||||
#elif defined (CYT4BFBCHS)
|
||||
#include "cyt4bfbchs.h"
|
||||
#elif defined (CYT4BFBCHE)
|
||||
#include "cyt4bfbche.h"
|
||||
#elif defined (CYT4BFCCJS)
|
||||
#include "cyt4bfccjs.h"
|
||||
#elif defined (CYT4BFCCJE)
|
||||
#include "cyt4bfccje.h"
|
||||
#elif defined (CYT4BFCCHS)
|
||||
#include "cyt4bfcchs.h"
|
||||
#elif defined (CYT4BFCCHE)
|
||||
#include "cyt4bfcche.h"
|
||||
#elif defined (CYT4A0100S)
|
||||
#include "cyt4a0100s.h"
|
||||
#else
|
||||
#error Undefined part number
|
||||
#endif
|
||||
|
||||
#endif /* _CY_DEVICE_HEADERS_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user