334 lines
17 KiB
Plaintext
334 lines
17 KiB
Plaintext
/***************************************************************************//**
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* \file linker_directives.icf
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* \version 1.0
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*
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* \brief Linker file for the IAR compiler.
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*
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*
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********************************************************************************
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* \copyright
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* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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define symbol use_psvp = 0; // 0 - Silicon, 1 - PSVP
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// Check that necessary symbols have been passed to linker via command line interface
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if((!isdefinedsymbol(_LINK_sram_)) && (!isdefinedsymbol(_LINK_flash_))) {
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error "Link location not defined or not supported!";
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}
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if((!isdefinedsymbol(_CORE_cm0plus_)) && (!isdefinedsymbol(_CORE_cm7_0_)) && (!isdefinedsymbol(_CORE_cm7_1_))) {
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error "Core type not defined or not supported!";
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}
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//============================================================
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// Memory address and size definitions
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//============================================================
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// Specify how much SRAM and CODE_FLASH (starting from the first address of the respective memory) shall
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// be used by CM0+ application, the rest of the memory will be assigned to CM7_0/1 application
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define symbol sram_total_size = 1024K;
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define symbol sram_private_for_srom = 2K; // Private SRAM for SROM (e.g. API processing). Reserved at the beginning.
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// Used during boot by Cypress firmware
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// (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations)
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// SRAM_MAX-4KB to SRAM_MAX-2KB is only affected
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define symbol sram_used_by_boot = 6K;
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define symbol cm0plus_sram_reserve = 128K; // (SRAM0/~128KB) -> cm0plus
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define symbol cm7_0_sram_reserve = 512K - cm0plus_sram_reserve; // (SRAM0/384KB) -> cm7_0
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// define symbol cm7_1_sram_reserve = 512K; // (SRAM1/256KB + SRAM2/~256KB) -> cm7_1
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if(use_psvp)
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{
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// PSVP
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define symbol code_flash_total_size = 2048K;
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define symbol cm0plus_code_flash_reserve = 512K;
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define symbol cm7_0_code_flash_reserve = 512K;
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define symbol cm7_1_code_flash_reserve = 1024K;
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}
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else
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{
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// Silicon
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define symbol code_flash_total_size = 8384K;
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define symbol cm0plus_code_flash_reserve = 512K;
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define symbol cm7_0_code_flash_reserve = 2048K;
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// define symbol cm7_1_code_flash_reserve = 5824K; // 8384K-512K-2048K = 5824K
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}
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define symbol code_flash_base_address = 0x10000000;
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define symbol sram_base_address = 0x28000000;
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define symbol cm7_0_itcm_base_address = 0xA0000000;
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define symbol cm7_0_dtcm_base_address = 0xA0010000;
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define symbol cm7_1_itcm_base_address = 0xA0100000;
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define symbol cm7_1_dtcm_base_address = 0xA0110000;
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define symbol ecc_init_width = 8; // Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic
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//----------------------------------------------
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// Specify stack and heap sizes for CM0+ and CM7 application independently
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define symbol cm0plus_heap_reserve = 1K;
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define symbol cm0plus_stack_reserve = 1K;
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define symbol cm7_heap_reserve = 1K;
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define symbol cm7_stack_reserve = 8K;
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define symbol cm7_itcm_reserve = 16K;
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define symbol cm7_dtcm_reserve = 16K;
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// Map core dependent definition to generic symbol for block definition
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if(isdefinedsymbol(_CORE_cm0plus_))
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{
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define symbol heap_reserve = cm0plus_heap_reserve;
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define symbol stack_reserve = (cm0plus_stack_reserve + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); // Ensure that stack size is an integer multiple of ECC init width (round up)
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}
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else // CM7
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{
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define symbol heap_reserve = cm7_heap_reserve;
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define symbol stack_reserve = (cm7_stack_reserve + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); // Ensure that stack size is an integer multiple of ECC init width (round up)
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}
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if(isdefinedsymbol(_LINK_sram_))
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{
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// Subtract 'sram_used_by_boot' beause content will be overwritten on reset, so it should not be used for loadable sections of RAM build configurations, which are only downloaded once by debugger)
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// Note: Could be removed if you ensure that no loadable section types (e.g. .text or .rodata) would be linked to this area
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define symbol sram_total_size_user = sram_total_size - sram_used_by_boot;
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}
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else
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{
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// Please note that 'sram_used_by_boot' is not subtracted from total size, but will have to be considered if certain sections need to preserve their content over a boot cycle
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define symbol sram_total_size_user = sram_total_size;
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}
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//----------------------------------------------
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// CM_0/1 definitions are required in CM0+ linker script for assigning the CM7 binary further below. (IAR multi core debugging)
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// SRAM reservations
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define symbol _base_SRAM_CM0P = sram_base_address + sram_private_for_srom;
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define symbol _size_SRAM_CM0P = cm0plus_sram_reserve - sram_private_for_srom;
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define symbol _base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve;
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define symbol _size_SRAM_CM7_0 = cm7_0_sram_reserve;
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define symbol _base_SRAM_CM7_1 = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
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define symbol _size_SRAM_CM7_1 = sram_total_size_user - cm0plus_sram_reserve - cm7_0_sram_reserve;
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// Code flash reservations
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// OTA-aware applications are linked after the immutable 64 KiB bootloader.
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define symbol _base_CODE_FLASH_CM0P = 0x10010000;
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define symbol _size_CODE_FLASH_CM0P = 448K;
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define symbol _base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve;
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define symbol _size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve;
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if(use_psvp)
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{
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define symbol _base_CODE_FLASH_CM7_1 = 0x10400000;
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define symbol _size_CODE_FLASH_CM7_1 = cm7_1_code_flash_reserve;
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}
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else
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{
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define symbol _base_CODE_FLASH_CM7_1 = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;
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define symbol _size_CODE_FLASH_CM7_1 = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;
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}
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if(isdefinedsymbol(_CORE_cm0plus_))
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{
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define symbol _base_SRAM = _base_SRAM_CM0P;
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define symbol _size_SRAM = _size_SRAM_CM0P;
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define symbol _base_CODE_FLASH = _base_CODE_FLASH_CM0P;
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define symbol _size_CODE_FLASH = _size_CODE_FLASH_CM0P;
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define symbol _base_ITCM = 0;
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define symbol _size_ITCM = 0;
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define symbol _base_DTCM = 0;
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define symbol _size_DTCM = 0;
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define symbol _base_SELF_ITCM = 0;
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define symbol _size_SELF_ITCM = 0;
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define symbol _base_SELF_DTCM = 0x20000000;
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define symbol _size_SELF_DTCM = 0;
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}
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else if(isdefinedsymbol(_CORE_cm7_0_))
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{
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define symbol _base_SRAM = _base_SRAM_CM7_0;
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define symbol _size_SRAM = _size_SRAM_CM7_0;
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define symbol _base_CODE_FLASH = _base_CODE_FLASH_CM7_0;
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define symbol _size_CODE_FLASH = _size_CODE_FLASH_CM7_0;
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define symbol _base_ITCM = cm7_0_itcm_base_address;
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define symbol _size_ITCM = cm7_itcm_reserve;
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define symbol _base_DTCM = cm7_0_dtcm_base_address;
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define symbol _size_DTCM = cm7_dtcm_reserve;
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define symbol _base_SELF_ITCM = 0;
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define symbol _size_SELF_ITCM = 16K;
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define symbol _base_SELF_DTCM = 0x20000000;
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define symbol _size_SELF_DTCM = 16K;
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}
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else if(isdefinedsymbol(_CORE_cm7_1_))
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{
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define symbol _base_SRAM = _base_SRAM_CM7_1;
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define symbol _size_SRAM = _size_SRAM_CM7_1;
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define symbol _base_CODE_FLASH = _base_CODE_FLASH_CM7_1;
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define symbol _size_CODE_FLASH = _size_CODE_FLASH_CM7_1;
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define symbol _base_ITCM = cm7_1_itcm_base_address;
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define symbol _size_ITCM = cm7_itcm_reserve;
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define symbol _base_DTCM = cm7_1_dtcm_base_address;
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define symbol _size_DTCM = cm7_dtcm_reserve;
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define symbol _base_SELF_ITCM = 0;
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define symbol _size_SELF_ITCM = 16K;
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define symbol _base_SELF_DTCM = 0x20000000;
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define symbol _size_SELF_DTCM = 16K;
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}
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define symbol _base_WORK_FLASH = 0x14000000;
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define symbol _size_WORK_FLASH = 0x00040000; // 256 KB
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define symbol _base_SFLASH = 0x17000000;
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define symbol _size_SFLASH = 0x00008000; // 32 KB
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define symbol _base_SFLASH_ALT = 0x17800000;
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define symbol _size_SFLASH_ALT = 0x00008000; // 32 KB
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define symbol _base_SMIF_MEMMAP = 0x60000000;
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define symbol _size_SMIF_MEMMAP = 0x08000000; // 128 MB
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define symbol _base_SFLASH_UF_ROWS = 0x17000800;
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define symbol _size_SFLASH_UF_ROWS = 0x00000800; // 2 KB
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define symbol _base_SFLASH_NAR = 0x17001A00;
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define symbol _size_SFLASH_NAR = 0x00000200; // 512 B
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define symbol _base_SFLASH_PKEY = 0x17006400;
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define symbol _size_SFLASH_PKEY = 0x00000C00; // 3 KB
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define symbol _base_SFLASH_APP_PROT = 0x17007600;
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define symbol _size_SFLASH_APP_PROT = 0x00000200; // 512 B
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define symbol _base_SFLASH_TOC2 = 0x17007C00;
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define symbol _size_SFLASH_TOC2 = 0x00000200; // 512 B
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//============================================================
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// Memory definitions
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//============================================================
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define memory mem with size = 4G;
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define region SELF_ITCM = mem:[from _base_SELF_ITCM size _size_SELF_ITCM ];
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define region CODE_FLASH = mem:[from _base_CODE_FLASH size _size_CODE_FLASH ];
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define region WORK_FLASH = mem:[from _base_WORK_FLASH size _size_WORK_FLASH ];
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define region SFLASH = mem:[from _base_SFLASH size _size_SFLASH ];
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define region SFLASH_ALT = mem:[from _base_SFLASH_ALT size _size_SFLASH_ALT ];
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define region SELF_DTCM = mem:[from _base_SELF_DTCM size _size_SELF_DTCM ];
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define region SRAM = mem:[from _base_SRAM size _size_SRAM ];
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define region SMIF_MEM = mem:[from _base_SMIF_MEMMAP size _size_SMIF_MEMMAP ];
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define region ITCM = mem:[from _base_ITCM size _size_ITCM ];
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define region DTCM = mem:[from _base_DTCM size _size_DTCM ];
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define region SFLASH_UF_ROWS = mem:[from _base_SFLASH_UF_ROWS size _size_SFLASH_UF_ROWS ];
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define region SFLASH_NAR = mem:[from _base_SFLASH_NAR size _size_SFLASH_NAR ];
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define region SFLASH_PKEY = mem:[from _base_SFLASH_PKEY size _size_SFLASH_PKEY ];
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define region SFLASH_APP_PROT = mem:[from _base_SFLASH_APP_PROT size _size_SFLASH_APP_PROT ];
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define region SFLASH_TOC2 = mem:[from _base_SFLASH_TOC2 size _size_SFLASH_TOC2 ];
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// CM7 regions are required in CM0+ linker script for assigning the CM7 binary further below. (IAR multi core debugging)
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if(isdefinedsymbol(_CORE_cm0plus_)) {
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define region SRAM_CM7_0 = mem:[from _base_SRAM_CM7_0 size _size_SRAM_CM7_0 ];
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define region CODE_FLASH_CM7_0 = mem:[from _base_CODE_FLASH_CM7_0 size _size_CODE_FLASH_CM7_0 ];
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define region SRAM_CM7_1 = mem:[from _base_SRAM_CM7_1 size _size_SRAM_CM7_1 ];
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define region CODE_FLASH_CM7_1 = mem:[from _base_CODE_FLASH_CM7_1 size _size_CODE_FLASH_CM7_1 ];
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}
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//============================================================
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// Block definitions
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//============================================================
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define block CSTACK with alignment = 8, size = stack_reserve { };
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define block HEAP with alignment = 8, size = heap_reserve { };
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define block HEAP_STACK { block HEAP, last block CSTACK };
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//============================================================
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// Initialization
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//============================================================
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initialize by copy { readwrite };
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do not initialize { section .intvec_ram };
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//============================================================
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// Placement
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//============================================================
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// Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH
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// Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated!
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if(isdefinedsymbol(_LINK_flash_))
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{
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place at start of CODE_FLASH { section .intvec };
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place in CODE_FLASH { readonly };
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// Include CM7 binary in the CM0+ output. (IAR multi core debugging)
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if(isdefinedsymbol(_CORE_cm0plus_))
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{
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place at start of CODE_FLASH_CM7_0 { section .cm7_0_rom };
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place at start of CODE_FLASH_CM7_1 { section .cm7_1_rom };
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}
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}
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else if(isdefinedsymbol(_LINK_sram_))
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{
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place at start of SRAM { section .intvec };
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place in SRAM { readonly };
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// Include CM7 binary in the CM0+ output. (IAR multi core debugging)
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if(isdefinedsymbol(_CORE_cm0plus_))
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{
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place at start of SRAM_CM7_0 { section .cm7_0_rom };
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place at start of SRAM_CM7_1 { section .cm7_1_rom };
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}
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}
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place in SRAM { readwrite };
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place at end of SRAM { block HEAP_STACK };
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//============================================================
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// Symbols for use by application
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//============================================================
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// The start of CM7_0/1 vector table is required by CM0+ application to correctly
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// set CPUSS->CM7_0/1_VECTOR_TABLE_BASE register before releasing CM7_0 or CM7_1 from reset
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if(isdefinedsymbol(_CORE_cm0plus_))
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{
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if(isdefinedsymbol(_LINK_flash_))
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{
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define exported symbol __cm7_0_vector_base_linker_symbol = start(CODE_FLASH_CM7_0);
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define exported symbol __cm7_1_vector_base_linker_symbol = start(CODE_FLASH_CM7_1);
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}
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else if(isdefinedsymbol(_LINK_sram_))
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{
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define exported symbol __cm7_0_vector_base_linker_symbol = start(SRAM_CM7_0);
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define exported symbol __cm7_1_vector_base_linker_symbol = start(SRAM_CM7_1);
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}
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}
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// These symbols will be used by startup.c / startup_customize.h for RAM ECC initialisation
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if(isdefinedsymbol(_LINK_sram_))
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{
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// Following definitions ensure that SRAM will not be touched at all by startup ECC initialization when code is linked to SRAM,
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// use debugger script to initialize the SRAM before downloading the application or adjust below symbols to not include
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// the area of SRAM where "ROM type" sections are linked to
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define exported symbol __ecc_init_sram_start_address = start(SRAM);
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define exported symbol __ecc_init_sram_end_address = start(SRAM) - 1;
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}
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else
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{
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define exported symbol __ecc_init_sram_start_address = start(SRAM);
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define exported symbol __ecc_init_sram_end_address = end(SRAM);
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}
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if(isdefinedsymbol(_CORE_cm7_0_) || isdefinedsymbol(_CORE_cm7_1_))
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{
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define exported symbol __ecc_init_dtcm_start_address = start(SELF_DTCM);
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define exported symbol __ecc_init_dtcm_end_address = end(SELF_DTCM);
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define exported symbol __ecc_init_itcm_start_address = start(SELF_ITCM);
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define exported symbol __ecc_init_itcm_end_address = end(SELF_ITCM);
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}
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place in SFLASH_UF_ROWS {readonly section .sflash_uf_rows};
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place in SFLASH_NAR {readonly section .sflash_nar};
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place in SFLASH_PKEY {readonly section .sflash_pkey};
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place in SFLASH_APP_PROT {readonly section .sflash_app_prot};
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place in SFLASH_TOC2 {readonly section .sflash_toc2};
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place in WORK_FLASH {readonly section .work_flash};
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